1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2014-2020 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 model = "Toradex Apalis iMX6Q/D Module"; 12 compatible = "toradex,apalis_imx6q", "fsl,imx6q"; 13 14 /* Will be filled by the bootloader */ 15 memory@10000000 { 16 device_type = "memory"; 17 reg = <0x10000000 0>; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&pinctrl_gpio_bl_on>; 24 pwms = <&pwm4 0 5000000>; 25 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 26 status = "disabled"; 27 }; 28 29 reg_module_3v3: regulator-module-3v3 { 30 compatible = "regulator-fixed"; 31 regulator-name = "+V3.3"; 32 regulator-min-microvolt = <3300000>; 33 regulator-max-microvolt = <3300000>; 34 regulator-always-on; 35 }; 36 37 reg_module_3v3_audio: regulator-module-3v3-audio { 38 compatible = "regulator-fixed"; 39 regulator-name = "+V3.3_AUDIO"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 regulator-always-on; 43 }; 44 45 reg_usb_otg_vbus: regulator-usb-otg-vbus { 46 compatible = "regulator-fixed"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 49 regulator-name = "usb_otg_vbus"; 50 regulator-min-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>; 52 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 53 enable-active-high; 54 status = "disabled"; 55 }; 56 57 /* on module USB hub */ 58 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 59 compatible = "regulator-fixed"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 62 regulator-name = "usb_host_vbus_hub"; 63 regulator-min-microvolt = <5000000>; 64 regulator-max-microvolt = <5000000>; 65 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 66 startup-delay-us = <2000>; 67 enable-active-high; 68 status = "okay"; 69 }; 70 71 reg_usb_host_vbus: regulator-usb-host-vbus { 72 compatible = "regulator-fixed"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 75 regulator-name = "usb_host_vbus"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 vin-supply = <®_usb_host_vbus_hub>; 81 status = "disabled"; 82 }; 83 84 sound { 85 compatible = "fsl,imx-audio-sgtl5000"; 86 model = "imx6q-apalis-sgtl5000"; 87 ssi-controller = <&ssi1>; 88 audio-codec = <&codec>; 89 audio-routing = 90 "LINE_IN", "Line In Jack", 91 "MIC_IN", "Mic Jack", 92 "Mic Jack", "Mic Bias", 93 "Headphone Jack", "HP_OUT"; 94 mux-int-port = <1>; 95 mux-ext-port = <4>; 96 }; 97 98 sound_spdif: sound-spdif { 99 compatible = "fsl,imx-audio-spdif"; 100 model = "imx-spdif"; 101 spdif-controller = <&spdif>; 102 spdif-in; 103 spdif-out; 104 status = "disabled"; 105 }; 106}; 107 108&audmux { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_audmux>; 111 status = "okay"; 112}; 113 114&can1 { 115 pinctrl-names = "default", "sleep"; 116 pinctrl-0 = <&pinctrl_flexcan1_default>; 117 pinctrl-1 = <&pinctrl_flexcan1_sleep>; 118 status = "disabled"; 119}; 120 121&can2 { 122 pinctrl-names = "default", "sleep"; 123 pinctrl-0 = <&pinctrl_flexcan2_default>; 124 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 125 status = "disabled"; 126}; 127 128/* Apalis SPI1 */ 129&ecspi1 { 130 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_ecspi1>; 133 status = "disabled"; 134}; 135 136/* Apalis SPI2 */ 137&ecspi2 { 138 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_ecspi2>; 141 status = "disabled"; 142}; 143 144&fec { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_enet>; 147 phy-mode = "rgmii-id"; 148 phy-handle = <ðphy>; 149 phy-reset-duration = <10>; 150 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 151 status = "okay"; 152 153 mdio { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 ethphy: ethernet-phy@7 { 158 interrupt-parent = <&gpio1>; 159 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 160 reg = <7>; 161 }; 162 }; 163}; 164 165&hdmi { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; 168 status = "disabled"; 169}; 170 171/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ 172&i2c1 { 173 clock-frequency = <100000>; 174 pinctrl-names = "default", "gpio"; 175 pinctrl-0 = <&pinctrl_i2c1>; 176 pinctrl-1 = <&pinctrl_i2c1_gpio>; 177 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 178 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 179 status = "disabled"; 180}; 181 182/* 183 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 184 * touch screen controller 185 */ 186&i2c2 { 187 clock-frequency = <100000>; 188 pinctrl-names = "default", "gpio"; 189 pinctrl-0 = <&pinctrl_i2c2>; 190 pinctrl-1 = <&pinctrl_i2c2_gpio>; 191 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 192 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 193 status = "okay"; 194 195 pmic: pfuze100@8 { 196 compatible = "fsl,pfuze100"; 197 reg = <0x08>; 198 199 regulators { 200 sw1a_reg: sw1ab { 201 regulator-min-microvolt = <300000>; 202 regulator-max-microvolt = <1875000>; 203 regulator-boot-on; 204 regulator-always-on; 205 regulator-ramp-delay = <6250>; 206 }; 207 208 sw1c_reg: sw1c { 209 regulator-min-microvolt = <300000>; 210 regulator-max-microvolt = <1875000>; 211 regulator-boot-on; 212 regulator-always-on; 213 regulator-ramp-delay = <6250>; 214 }; 215 216 sw3a_reg: sw3a { 217 regulator-min-microvolt = <400000>; 218 regulator-max-microvolt = <1975000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 swbst_reg: swbst { 224 regulator-min-microvolt = <5000000>; 225 regulator-max-microvolt = <5150000>; 226 regulator-boot-on; 227 regulator-always-on; 228 }; 229 230 snvs_reg: vsnvs { 231 regulator-min-microvolt = <1000000>; 232 regulator-max-microvolt = <3000000>; 233 regulator-boot-on; 234 regulator-always-on; 235 }; 236 237 vref_reg: vrefddr { 238 regulator-boot-on; 239 regulator-always-on; 240 }; 241 242 vgen1_reg: vgen1 { 243 regulator-min-microvolt = <800000>; 244 regulator-max-microvolt = <1550000>; 245 regulator-boot-on; 246 regulator-always-on; 247 }; 248 249 vgen2_reg: vgen2 { 250 regulator-min-microvolt = <800000>; 251 regulator-max-microvolt = <1550000>; 252 regulator-boot-on; 253 regulator-always-on; 254 }; 255 256 vgen3_reg: vgen3 { 257 regulator-min-microvolt = <1800000>; 258 regulator-max-microvolt = <3300000>; 259 regulator-boot-on; 260 regulator-always-on; 261 }; 262 263 vgen4_reg: vgen4 { 264 regulator-min-microvolt = <1800000>; 265 regulator-max-microvolt = <1800000>; 266 regulator-boot-on; 267 regulator-always-on; 268 }; 269 270 vgen5_reg: vgen5 { 271 regulator-min-microvolt = <1800000>; 272 regulator-max-microvolt = <3300000>; 273 regulator-boot-on; 274 regulator-always-on; 275 }; 276 277 vgen6_reg: vgen6 { 278 regulator-min-microvolt = <1800000>; 279 regulator-max-microvolt = <3300000>; 280 regulator-boot-on; 281 regulator-always-on; 282 }; 283 }; 284 }; 285 286 codec: sgtl5000@a { 287 compatible = "fsl,sgtl5000"; 288 reg = <0x0a>; 289 clocks = <&clks IMX6QDL_CLK_CKO>; 290 VDDA-supply = <®_module_3v3_audio>; 291 VDDIO-supply = <®_module_3v3>; 292 VDDD-supply = <&vgen4_reg>; 293 }; 294 295 /* STMPE811 touch screen controller */ 296 stmpe811@41 { 297 compatible = "st,stmpe811"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_touch_int>; 300 reg = <0x41>; 301 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 302 interrupt-parent = <&gpio4>; 303 interrupt-controller; 304 id = <0>; 305 blocks = <0x5>; 306 irq-trigger = <0x1>; 307 /* 3.25 MHz ADC clock speed */ 308 st,adc-freq = <1>; 309 /* 12-bit ADC */ 310 st,mod-12b = <1>; 311 /* internal ADC reference */ 312 st,ref-sel = <0>; 313 /* ADC converstion time: 80 clocks */ 314 st,sample-time = <4>; 315 316 stmpe_touchscreen { 317 compatible = "st,stmpe-ts"; 318 /* 8 sample average control */ 319 st,ave-ctrl = <3>; 320 /* 7 length fractional part in z */ 321 st,fraction-z = <7>; 322 /* 323 * 50 mA typical 80 mA max touchscreen drivers 324 * current limit value 325 */ 326 st,i-drive = <1>; 327 /* 1 ms panel driver settling time */ 328 st,settling = <3>; 329 /* 5 ms touch detect interrupt delay */ 330 st,touch-det-delay = <5>; 331 }; 332 333 stmpe_adc { 334 compatible = "st,stmpe-adc"; 335 /* forbid to use ADC channels 3-0 (touch) */ 336 st,norequest-mask = <0x0F>; 337 }; 338 }; 339}; 340 341/* 342 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier 343 * board) 344 */ 345&i2c3 { 346 clock-frequency = <100000>; 347 pinctrl-names = "default", "gpio"; 348 pinctrl-0 = <&pinctrl_i2c3>; 349 pinctrl-1 = <&pinctrl_i2c3_gpio>; 350 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 351 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 352 status = "disabled"; 353}; 354 355&pwm1 { 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_pwm1>; 358 status = "disabled"; 359}; 360 361&pwm2 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_pwm2>; 364 status = "disabled"; 365}; 366 367&pwm3 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_pwm3>; 370 status = "disabled"; 371}; 372 373&pwm4 { 374 #pwm-cells = <2>; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_pwm4>; 377 status = "disabled"; 378}; 379 380&spdif { 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_spdif>; 383 status = "disabled"; 384}; 385 386&ssi1 { 387 status = "okay"; 388}; 389 390&uart1 { 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 393 fsl,dte-mode; 394 uart-has-rtscts; 395 status = "disabled"; 396}; 397 398&uart2 { 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_uart2_dte>; 401 fsl,dte-mode; 402 uart-has-rtscts; 403 status = "disabled"; 404}; 405 406&uart4 { 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_uart4_dte>; 409 fsl,dte-mode; 410 status = "disabled"; 411}; 412 413&uart5 { 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_uart5_dte>; 416 fsl,dte-mode; 417 status = "disabled"; 418}; 419 420&usbotg { 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_usbotg>; 423 disable-over-current; 424 status = "disabled"; 425}; 426 427/* MMC1 */ 428&usdhc1 { 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; 431 vqmmc-supply = <®_module_3v3>; 432 bus-width = <8>; 433 disable-wp; 434 no-1-8-v; 435 status = "disabled"; 436}; 437 438/* SD1 */ 439&usdhc2 { 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pinctrl_usdhc2>; 442 vqmmc-supply = <®_module_3v3>; 443 bus-width = <4>; 444 disable-wp; 445 no-1-8-v; 446 status = "disabled"; 447}; 448 449/* eMMC */ 450&usdhc3 { 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pinctrl_usdhc3>; 453 vqmmc-supply = <®_module_3v3>; 454 bus-width = <8>; 455 no-1-8-v; 456 non-removable; 457 status = "okay"; 458}; 459 460&weim { 461 status = "disabled"; 462}; 463 464&iomuxc { 465 pinctrl_apalis_gpio1: gpio2io04grp { 466 fsl,pins = < 467 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 468 >; 469 }; 470 471 pinctrl_apalis_gpio2: gpio2io05grp { 472 fsl,pins = < 473 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 474 >; 475 }; 476 477 pinctrl_apalis_gpio3: gpio2io06grp { 478 fsl,pins = < 479 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 480 >; 481 }; 482 483 pinctrl_apalis_gpio4: gpio2io07grp { 484 fsl,pins = < 485 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 486 >; 487 }; 488 489 pinctrl_apalis_gpio5: gpio6io10grp { 490 fsl,pins = < 491 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 492 >; 493 }; 494 495 pinctrl_apalis_gpio6: gpio6io09grp { 496 fsl,pins = < 497 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 498 >; 499 }; 500 501 pinctrl_apalis_gpio7: gpio1io02grp { 502 fsl,pins = < 503 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 504 >; 505 }; 506 507 pinctrl_apalis_gpio8: gpio1io06grp { 508 fsl,pins = < 509 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 510 >; 511 }; 512 513 pinctrl_audmux: audmuxgrp { 514 fsl,pins = < 515 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 516 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 517 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 518 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 519 /* SGTL5000 sys_mclk */ 520 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 521 >; 522 }; 523 524 pinctrl_cam_mclk: cammclkgrp { 525 fsl,pins = < 526 /* CAM sys_mclk */ 527 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 528 >; 529 }; 530 531 pinctrl_ecspi1: ecspi1grp { 532 fsl,pins = < 533 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 534 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 535 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 536 /* SPI1 cs */ 537 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 538 >; 539 }; 540 541 pinctrl_ecspi2: ecspi2grp { 542 fsl,pins = < 543 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 544 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 545 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 546 /* SPI2 cs */ 547 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 548 >; 549 }; 550 551 pinctrl_enet: enetgrp { 552 fsl,pins = < 553 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 554 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 555 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 556 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 557 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 558 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 559 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 560 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 561 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 562 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 563 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 564 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 565 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 566 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 567 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 568 /* Ethernet PHY reset */ 569 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 570 /* Ethernet PHY interrupt */ 571 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 572 >; 573 }; 574 575 pinctrl_flexcan1_default: flexcan1defgrp { 576 fsl,pins = < 577 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 578 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 579 >; 580 }; 581 582 pinctrl_flexcan1_sleep: flexcan1slpgrp { 583 fsl,pins = < 584 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 585 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 586 >; 587 }; 588 589 pinctrl_flexcan2_default: flexcan2defgrp { 590 fsl,pins = < 591 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 592 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 593 >; 594 }; 595 pinctrl_flexcan2_sleep: flexcan2slpgrp { 596 fsl,pins = < 597 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 598 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 599 >; 600 }; 601 602 pinctrl_gpio_bl_on: gpioblon { 603 fsl,pins = < 604 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 605 >; 606 }; 607 608 pinctrl_gpio_keys: gpio1io04grp { 609 fsl,pins = < 610 /* Power button */ 611 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 612 >; 613 }; 614 615 pinctrl_hdmi_cec: hdmicecgrp { 616 fsl,pins = < 617 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 618 >; 619 }; 620 621 pinctrl_hdmi_ddc: hdmiddcgrp { 622 fsl,pins = < 623 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 624 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 625 >; 626 }; 627 628 pinctrl_i2c1: i2c1grp { 629 fsl,pins = < 630 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 631 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 632 >; 633 }; 634 635 pinctrl_i2c1_gpio: i2c1gpiogrp { 636 fsl,pins = < 637 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 638 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 639 >; 640 }; 641 642 pinctrl_i2c2: i2c2grp { 643 fsl,pins = < 644 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 645 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 646 >; 647 }; 648 649 pinctrl_i2c2_gpio: i2c2gpiogrp { 650 fsl,pins = < 651 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 652 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 653 >; 654 }; 655 656 pinctrl_i2c3: i2c3grp { 657 fsl,pins = < 658 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 659 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 660 >; 661 }; 662 663 pinctrl_i2c3_gpio: i2c3gpiogrp { 664 fsl,pins = < 665 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 666 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 667 >; 668 }; 669 670 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 671 fsl,pins = < 672 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 673 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 674 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 675 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 676 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 677 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 678 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 679 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 680 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 681 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 682 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 683 >; 684 }; 685 686 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 687 fsl,pins = < 688 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 689 /* DE */ 690 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 691 /* HSync */ 692 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 693 /* VSync */ 694 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 695 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 696 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 697 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 698 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 699 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 700 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 701 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 702 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 703 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 704 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 705 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 706 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 707 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 708 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 709 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 710 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 711 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 712 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 713 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 714 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 715 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 716 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 717 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 718 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 719 >; 720 }; 721 722 pinctrl_ipu2_vdac: ipu2vdacgrp { 723 fsl,pins = < 724 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 725 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 726 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 727 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 728 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 729 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 730 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 731 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 732 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 733 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 734 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 735 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 736 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 737 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 738 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 739 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 740 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 741 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 742 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 743 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 744 >; 745 }; 746 747 pinctrl_mmc_cd: gpiommccdgrp { 748 fsl,pins = < 749 /* MMC1 CD */ 750 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 751 >; 752 }; 753 754 pinctrl_pwm1: pwm1grp { 755 fsl,pins = < 756 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 757 >; 758 }; 759 760 pinctrl_pwm2: pwm2grp { 761 fsl,pins = < 762 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 763 >; 764 }; 765 766 pinctrl_pwm3: pwm3grp { 767 fsl,pins = < 768 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 769 >; 770 }; 771 772 pinctrl_pwm4: pwm4grp { 773 fsl,pins = < 774 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 775 >; 776 }; 777 778 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 779 fsl,pins = < 780 /* USBH_EN */ 781 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 782 >; 783 }; 784 785 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { 786 fsl,pins = < 787 /* USBH_HUB_EN */ 788 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 789 >; 790 }; 791 792 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { 793 fsl,pins = < 794 /* USBO1 power en */ 795 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 796 >; 797 }; 798 799 pinctrl_reset_moci: gpioresetmocigrp { 800 fsl,pins = < 801 /* RESET_MOCI control */ 802 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 803 >; 804 }; 805 806 pinctrl_sd_cd: gpiosdcdgrp { 807 fsl,pins = < 808 /* SD1 CD */ 809 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 810 >; 811 }; 812 813 pinctrl_spdif: spdifgrp { 814 fsl,pins = < 815 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 816 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 817 >; 818 }; 819 820 pinctrl_touch_int: gpiotouchintgrp { 821 fsl,pins = < 822 /* STMPE811 interrupt */ 823 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 824 >; 825 }; 826 827 pinctrl_uart1_dce: uart1dcegrp { 828 fsl,pins = < 829 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 830 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 831 >; 832 }; 833 834 /* DTE mode */ 835 pinctrl_uart1_dte: uart1dtegrp { 836 fsl,pins = < 837 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 838 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 839 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 840 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 841 >; 842 }; 843 844 /* Additional DTR, DSR, DCD */ 845 pinctrl_uart1_ctrl: uart1ctrlgrp { 846 fsl,pins = < 847 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 848 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 849 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 850 >; 851 }; 852 853 pinctrl_uart2_dce: uart2dcegrp { 854 fsl,pins = < 855 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 856 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 857 >; 858 }; 859 860 /* DTE mode */ 861 pinctrl_uart2_dte: uart2dtegrp { 862 fsl,pins = < 863 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 864 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 865 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 866 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 867 >; 868 }; 869 870 pinctrl_uart4_dce: uart4dcegrp { 871 fsl,pins = < 872 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 873 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 874 >; 875 }; 876 877 /* DTE mode */ 878 pinctrl_uart4_dte: uart4dtegrp { 879 fsl,pins = < 880 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 881 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 882 >; 883 }; 884 885 pinctrl_uart5_dce: uart5dcegrp { 886 fsl,pins = < 887 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 888 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 889 >; 890 }; 891 892 /* DTE mode */ 893 pinctrl_uart5_dte: uart5dtegrp { 894 fsl,pins = < 895 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 896 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 897 >; 898 }; 899 900 pinctrl_usbotg: usbotggrp { 901 fsl,pins = < 902 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 903 >; 904 }; 905 906 pinctrl_usdhc1_4bit: usdhc1grp_4bit { 907 fsl,pins = < 908 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 909 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 910 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 911 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 912 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 913 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 914 >; 915 }; 916 917 pinctrl_usdhc1_8bit: usdhc1grp_8bit { 918 fsl,pins = < 919 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 920 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 921 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 922 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 923 >; 924 }; 925 926 pinctrl_usdhc2: usdhc2grp { 927 fsl,pins = < 928 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 929 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 930 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 931 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 932 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 933 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 934 >; 935 }; 936 937 pinctrl_usdhc3: usdhc3grp { 938 fsl,pins = < 939 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 940 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 941 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 942 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 943 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 944 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 945 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 946 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 947 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 948 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 949 /* eMMC reset */ 950 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 951 >; 952 }; 953}; 954