1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	/* these are used by bootloader for disabling nodes */
12	aliases {
13		led0 = &led0;
14		led1 = &led1;
15		led2 = &led2;
16		nand = &gpmi;
17		ssi0 = &ssi1;
18		usb0 = &usbh1;
19		usb1 = &usbotg;
20	};
21
22	chosen {
23		bootargs = "console=ttymxc1,115200";
24	};
25
26	backlight {
27		compatible = "pwm-backlight";
28		pwms = <&pwm4 0 5000000>;
29		brightness-levels = <0 4 8 16 32 64 128 255>;
30		default-brightness-level = <7>;
31	};
32
33	gpio-keys {
34		compatible = "gpio-keys";
35
36		user-pb {
37			label = "user_pb";
38			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
39			linux,code = <BTN_0>;
40		};
41
42		user-pb1x {
43			label = "user_pb1x";
44			linux,code = <BTN_1>;
45			interrupt-parent = <&gsc>;
46			interrupts = <0>;
47		};
48
49		key-erased {
50			label = "key-erased";
51			linux,code = <BTN_2>;
52			interrupt-parent = <&gsc>;
53			interrupts = <1>;
54		};
55
56		eeprom-wp {
57			label = "eeprom_wp";
58			linux,code = <BTN_3>;
59			interrupt-parent = <&gsc>;
60			interrupts = <2>;
61		};
62
63		tamper {
64			label = "tamper";
65			linux,code = <BTN_4>;
66			interrupt-parent = <&gsc>;
67			interrupts = <5>;
68		};
69
70		switch-hold {
71			label = "switch_hold";
72			linux,code = <BTN_5>;
73			interrupt-parent = <&gsc>;
74			interrupts = <7>;
75		};
76	};
77
78	leds {
79		compatible = "gpio-leds";
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_gpio_leds>;
82
83		led0: user1 {
84			label = "user1";
85			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
86			default-state = "on";
87			linux,default-trigger = "heartbeat";
88		};
89
90		led1: user2 {
91			label = "user2";
92			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
93			default-state = "off";
94		};
95
96		led2: user3 {
97			label = "user3";
98			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
99			default-state = "off";
100		};
101	};
102
103	memory@10000000 {
104		device_type = "memory";
105		reg = <0x10000000 0x40000000>;
106	};
107
108	pps {
109		compatible = "pps-gpio";
110		pinctrl-names = "default";
111		pinctrl-0 = <&pinctrl_pps>;
112		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
113		status = "okay";
114	};
115
116	reg_1p0v: regulator-1p0v {
117		compatible = "regulator-fixed";
118		regulator-name = "1P0V";
119		regulator-min-microvolt = <1000000>;
120		regulator-max-microvolt = <1000000>;
121		regulator-always-on;
122	};
123
124	reg_3p3v: regulator-3p3v {
125		compatible = "regulator-fixed";
126		regulator-name = "3P3V";
127		regulator-min-microvolt = <3300000>;
128		regulator-max-microvolt = <3300000>;
129		regulator-always-on;
130	};
131
132	reg_usb_h1_vbus: regulator-usb-h1-vbus {
133		compatible = "regulator-fixed";
134		regulator-name = "usb_h1_vbus";
135		regulator-min-microvolt = <5000000>;
136		regulator-max-microvolt = <5000000>;
137		regulator-always-on;
138	};
139
140	reg_usb_otg_vbus: regulator-usb-otg-vbus {
141		compatible = "regulator-fixed";
142		regulator-name = "usb_otg_vbus";
143		regulator-min-microvolt = <5000000>;
144		regulator-max-microvolt = <5000000>;
145		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
146		enable-active-high;
147	};
148
149	sound {
150		compatible = "fsl,imx6q-ventana-sgtl5000",
151			     "fsl,imx-audio-sgtl5000";
152		model = "sgtl5000-audio";
153		ssi-controller = <&ssi1>;
154		audio-codec = <&codec>;
155		audio-routing =
156			"MIC_IN", "Mic Jack",
157			"Mic Jack", "Mic Bias",
158			"Headphone Jack", "HP_OUT";
159		mux-int-port = <1>;
160		mux-ext-port = <4>;
161	};
162};
163
164&audmux {
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_audmux>;
167	status = "okay";
168};
169
170&can1 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_flexcan1>;
173	status = "okay";
174};
175
176&clks {
177	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
178			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
179	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
180				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
181};
182
183&fec {
184	pinctrl-names = "default";
185	pinctrl-0 = <&pinctrl_enet>;
186	phy-mode = "rgmii-id";
187	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
188	status = "okay";
189};
190
191&gpmi {
192	pinctrl-names = "default";
193	pinctrl-0 = <&pinctrl_gpmi_nand>;
194	status = "okay";
195};
196
197&hdmi {
198	ddc-i2c-bus = <&i2c3>;
199	status = "okay";
200};
201
202&i2c1 {
203	clock-frequency = <100000>;
204	pinctrl-names = "default";
205	pinctrl-0 = <&pinctrl_i2c1>;
206	status = "okay";
207
208	gsc: gsc@20 {
209		compatible = "gw,gsc";
210		reg = <0x20>;
211		interrupt-parent = <&gpio1>;
212		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
213		interrupt-controller;
214		#interrupt-cells = <1>;
215		#size-cells = <0>;
216
217		adc {
218			compatible = "gw,gsc-adc";
219			#address-cells = <1>;
220			#size-cells = <0>;
221
222			channel@0 {
223				gw,mode = <0>;
224				reg = <0x00>;
225				label = "temp";
226			};
227
228			channel@2 {
229				gw,mode = <1>;
230				reg = <0x02>;
231				label = "vdd_vin";
232			};
233
234			channel@5 {
235				gw,mode = <1>;
236				reg = <0x05>;
237				label = "vdd_3p3";
238			};
239
240			channel@8 {
241				gw,mode = <1>;
242				reg = <0x08>;
243				label = "vdd_bat";
244			};
245
246			channel@b {
247				gw,mode = <1>;
248				reg = <0x0b>;
249				label = "vdd_5p0";
250			};
251
252			channel@e {
253				gw,mode = <1>;
254				reg = <0xe>;
255				label = "vdd_arm";
256			};
257
258			channel@11 {
259				gw,mode = <1>;
260				reg = <0x11>;
261				label = "vdd_soc";
262			};
263
264			channel@14 {
265				gw,mode = <1>;
266				reg = <0x14>;
267				label = "vdd_3p0";
268			};
269
270			channel@17 {
271				gw,mode = <1>;
272				reg = <0x17>;
273				label = "vdd_1p5";
274			};
275
276			channel@1d {
277				gw,mode = <1>;
278				reg = <0x1d>;
279				label = "vdd_1p8";
280			};
281
282			channel@20 {
283				gw,mode = <1>;
284				reg = <0x20>;
285				label = "vdd_1p0";
286			};
287
288			channel@23 {
289				gw,mode = <1>;
290				reg = <0x23>;
291				label = "vdd_2p5";
292			};
293
294			channel@26 {
295				gw,mode = <1>;
296				reg = <0x26>;
297				label = "vdd_gps";
298			};
299
300			channel@29 {
301				gw,mode = <1>;
302				reg = <0x29>;
303				label = "vdd_an1";
304			};
305		};
306	};
307
308	gsc_gpio: gpio@23 {
309		compatible = "nxp,pca9555";
310		reg = <0x23>;
311		gpio-controller;
312		#gpio-cells = <2>;
313		interrupt-parent = <&gsc>;
314		interrupts = <4>;
315	};
316
317	eeprom1: eeprom@50 {
318		compatible = "atmel,24c02";
319		reg = <0x50>;
320		pagesize = <16>;
321	};
322
323	eeprom2: eeprom@51 {
324		compatible = "atmel,24c02";
325		reg = <0x51>;
326		pagesize = <16>;
327	};
328
329	eeprom3: eeprom@52 {
330		compatible = "atmel,24c02";
331		reg = <0x52>;
332		pagesize = <16>;
333	};
334
335	eeprom4: eeprom@53 {
336		compatible = "atmel,24c02";
337		reg = <0x53>;
338		pagesize = <16>;
339	};
340
341	rtc: ds1672@68 {
342		compatible = "dallas,ds1672";
343		reg = <0x68>;
344	};
345};
346
347&i2c2 {
348	clock-frequency = <100000>;
349	pinctrl-names = "default";
350	pinctrl-0 = <&pinctrl_i2c2>;
351	status = "okay";
352
353	ltc3676: pmic@3c {
354		compatible = "lltc,ltc3676";
355		reg = <0x3c>;
356		interrupt-parent = <&gpio1>;
357		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
358
359		regulators {
360			/* VDD_SOC (1+R1/R2 = 1.635) */
361			reg_vdd_soc: sw1 {
362				regulator-name = "vddsoc";
363				regulator-min-microvolt = <674400>;
364				regulator-max-microvolt = <1308000>;
365				lltc,fb-voltage-divider = <127000 200000>;
366				regulator-ramp-delay = <7000>;
367				regulator-boot-on;
368				regulator-always-on;
369			};
370
371			/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
372			reg_1p8v: sw2 {
373				regulator-name = "vdd1p8";
374				regulator-min-microvolt = <1033310>;
375				regulator-max-microvolt = <2004000>;
376				lltc,fb-voltage-divider = <301000 200000>;
377				regulator-ramp-delay = <7000>;
378				regulator-boot-on;
379				regulator-always-on;
380			};
381
382			/* VDD_ARM (1+R1/R2 = 1.635) */
383			reg_vdd_arm: sw3 {
384				regulator-name = "vddarm";
385				regulator-min-microvolt = <674400>;
386				regulator-max-microvolt = <1308000>;
387				lltc,fb-voltage-divider = <127000 200000>;
388				regulator-ramp-delay = <7000>;
389				regulator-boot-on;
390				regulator-always-on;
391			};
392
393			/* VDD_DDR (1+R1/R2 = 2.105) */
394			reg_vdd_ddr: sw4 {
395				regulator-name = "vddddr";
396				regulator-min-microvolt = <868310>;
397				regulator-max-microvolt = <1684000>;
398				lltc,fb-voltage-divider = <221000 200000>;
399				regulator-ramp-delay = <7000>;
400				regulator-boot-on;
401				regulator-always-on;
402			};
403
404			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
405			reg_2p5v: ldo2 {
406				regulator-name = "vdd2p5";
407				regulator-min-microvolt = <2490375>;
408				regulator-max-microvolt = <2490375>;
409				lltc,fb-voltage-divider = <487000 200000>;
410				regulator-boot-on;
411				regulator-always-on;
412			};
413
414			/* VDD_AUD_1P8: Audio codec */
415			reg_aud_1p8v: ldo3 {
416				regulator-name = "vdd1p8a";
417				regulator-min-microvolt = <1800000>;
418				regulator-max-microvolt = <1800000>;
419				regulator-boot-on;
420			};
421
422			/* VDD_HIGH (1+R1/R2 = 4.17) */
423			reg_3p0v: ldo4 {
424				regulator-name = "vdd3p0";
425				regulator-min-microvolt = <3023250>;
426				regulator-max-microvolt = <3023250>;
427				lltc,fb-voltage-divider = <634000 200000>;
428				regulator-boot-on;
429				regulator-always-on;
430			};
431		};
432	};
433};
434
435&i2c3 {
436	clock-frequency = <100000>;
437	pinctrl-names = "default";
438	pinctrl-0 = <&pinctrl_i2c3>;
439	status = "okay";
440
441	codec: sgtl5000@a {
442		compatible = "fsl,sgtl5000";
443		reg = <0x0a>;
444		clocks = <&clks IMX6QDL_CLK_CKO>;
445		VDDA-supply = <&reg_1p8v>;
446		VDDIO-supply = <&reg_3p3v>;
447	};
448
449	touchscreen: egalax_ts@4 {
450		compatible = "eeti,egalax_ts";
451		reg = <0x04>;
452		interrupt-parent = <&gpio1>;
453		interrupts = <11 2>;
454		wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
455	};
456
457	accel@1e {
458		compatible = "nxp,fxos8700";
459		reg = <0x1e>;
460	};
461};
462
463&ldb {
464	status = "okay";
465
466	lvds-channel@0 {
467		fsl,data-mapping = "spwg";
468		fsl,data-width = <18>;
469		status = "okay";
470
471		display-timings {
472			native-mode = <&timing0>;
473			timing0: hsd100pxn1 {
474				clock-frequency = <65000000>;
475				hactive = <1024>;
476				vactive = <768>;
477				hback-porch = <220>;
478				hfront-porch = <40>;
479				vback-porch = <21>;
480				vfront-porch = <7>;
481				hsync-len = <60>;
482				vsync-len = <10>;
483			};
484		};
485	};
486};
487
488&pcie {
489	pinctrl-names = "default";
490	pinctrl-0 = <&pinctrl_pcie>;
491	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
492	status = "okay";
493};
494
495&pwm2 {
496	pinctrl-names = "default";
497	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
498	status = "disabled";
499};
500
501&pwm3 {
502	pinctrl-names = "default";
503	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
504	status = "disabled";
505};
506
507&pwm4 {
508	#pwm-cells = <2>;
509	pinctrl-names = "default";
510	pinctrl-0 = <&pinctrl_pwm4>;
511	status = "okay";
512};
513
514&ssi1 {
515	status = "okay";
516};
517
518&uart1 {
519	pinctrl-names = "default";
520	pinctrl-0 = <&pinctrl_uart1>;
521	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
522	status = "okay";
523};
524
525&uart2 {
526	pinctrl-names = "default";
527	pinctrl-0 = <&pinctrl_uart2>;
528	status = "okay";
529};
530
531&uart5 {
532	pinctrl-names = "default";
533	pinctrl-0 = <&pinctrl_uart5>;
534	status = "okay";
535};
536
537&usbotg {
538	vbus-supply = <&reg_usb_otg_vbus>;
539	pinctrl-names = "default";
540	pinctrl-0 = <&pinctrl_usbotg>;
541	disable-over-current;
542	status = "okay";
543};
544
545&usbh1 {
546	vbus-supply = <&reg_usb_h1_vbus>;
547	status = "okay";
548};
549
550&usdhc3 {
551	pinctrl-names = "default", "state_100mhz", "state_200mhz";
552	pinctrl-0 = <&pinctrl_usdhc3>;
553	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
554	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
555	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
556	vmmc-supply = <&reg_3p3v>;
557	no-1-8-v; /* firmware will remove if board revision supports */
558	status = "okay";
559};
560
561&wdog1 {
562	pinctrl-names = "default";
563	pinctrl-0 = <&pinctrl_wdog>;
564	fsl,ext-reset-output;
565};
566
567&iomuxc {
568	pinctrl_audmux: audmuxgrp {
569		fsl,pins = <
570			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
571			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
572			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
573			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
574			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0 /* AUD4_MCK */
575		>;
576	};
577
578	pinctrl_enet: enetgrp {
579		fsl,pins = <
580			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
581			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
582			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
583			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
584			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
585			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
586			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
587			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
588			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
589			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
590			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
591			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
592			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
593			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
594			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
595			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
596		>;
597	};
598
599	pinctrl_flexcan1: flexcan1grp {
600		fsl,pins = <
601			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
602			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
603			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0 /* CAN_STBY */
604		>;
605	};
606
607	pinctrl_gpio_leds: gpioledsgrp {
608		fsl,pins = <
609			MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x1b0b0
610			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
611			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x1b0b0
612		>;
613	};
614
615	pinctrl_gpmi_nand: gpminandgrp {
616		fsl,pins = <
617			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
618			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
619			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
620			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
621			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
622			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
623			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
624			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
625			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
626			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
627			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
628			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
629			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
630			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
631			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
632		>;
633	};
634
635	pinctrl_i2c1: i2c1grp {
636		fsl,pins = <
637			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
638			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
639			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
640		>;
641	};
642
643	pinctrl_i2c2: i2c2grp {
644		fsl,pins = <
645			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
646			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
647		>;
648	};
649
650	pinctrl_i2c3: i2c3grp {
651		fsl,pins = <
652			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
653			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
654		>;
655	};
656
657	pinctrl_pcie: pciegrp {
658		fsl,pins = <
659			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
660			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x1b0b0 /* PCIE RST */
661		>;
662	};
663
664	pinctrl_pmic: pmicgrp {
665		fsl,pins = <
666			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x0001b0b0 /* PMIC_IRQ# */
667		>;
668	};
669
670	pinctrl_pps: ppsgrp {
671		fsl,pins = <
672			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
673		>;
674	};
675
676	pinctrl_pwm2: pwm2grp {
677		fsl,pins = <
678			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
679		>;
680	};
681
682	pinctrl_pwm3: pwm3grp {
683		fsl,pins = <
684			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
685		>;
686	};
687
688	pinctrl_pwm4: pwm4grp {
689		fsl,pins = <
690			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
691		>;
692	};
693
694	pinctrl_uart1: uart1grp {
695		fsl,pins = <
696			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
697			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
698			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
699		>;
700	};
701
702	pinctrl_uart2: uart2grp {
703		fsl,pins = <
704			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
705			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
706		>;
707	};
708
709	pinctrl_uart5: uart5grp {
710		fsl,pins = <
711			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
712			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
713		>;
714	};
715
716	pinctrl_usbotg: usbotggrp {
717		fsl,pins = <
718			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
719			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
720			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0 /* OC */
721		>;
722	};
723
724	pinctrl_usdhc3: usdhc3grp {
725		fsl,pins = <
726			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
727			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
728			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
729			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
730			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
731			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
732			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
733			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
734		>;
735	};
736
737	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
738		fsl,pins = <
739			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
740			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
741			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
742			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
743			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
744			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
745			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
746			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
747		>;
748	};
749
750	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
751		fsl,pins = <
752			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
753			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
754			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
755			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
756			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
757			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
758			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
759			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
760		>;
761	};
762
763	pinctrl_wdog: wdoggrp {
764		fsl,pins = <
765			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
766		>;
767	};
768};
769