1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (c) 2018 Protonic Holland 4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix 5 */ 6 7/dts-v1/; 8#include <dt-bindings/gpio/gpio.h> 9#include "imx6qp.dtsi" 10 11/ { 12 model = "Protonic WD3 board"; 13 compatible = "prt,prtwd3", "fsl,imx6qp"; 14 15 chosen { 16 stdout-path = &uart4; 17 }; 18 19 memory@10000000 { 20 device_type = "memory"; 21 reg = <0x10000000 0x20000000>; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 reg = <0x80000000 0x20000000>; 27 }; 28 29 clock_ksz8081: clock-ksz8081 { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <50000000>; 33 }; 34 35 clock_ksz9031: clock-ksz9031 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <25000000>; 39 }; 40 41 clock_mcp251xfd: clock-mcp251xfd { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <20000000>; 45 }; 46 47 clock_sja1105: clock-sja1105 { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <25000000>; 51 }; 52 53 mdio { 54 compatible = "virtual,mdio-gpio"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_mdio>; 57 58 #address-cells = <1>; 59 #size-cells = <0>; 60 gpios = <&gpio5 6 GPIO_ACTIVE_HIGH 61 &gpio5 7 GPIO_ACTIVE_HIGH>; 62 63 /* Microchip KSZ8081 */ 64 usbeth_phy: ethernet-phy@3 { 65 reg = <0x3>; 66 67 interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; 68 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 69 reset-assert-us = <500>; 70 reset-deassert-us = <1000>; 71 clocks = <&clock_ksz8081>; 72 clock-names = "rmii-ref"; 73 micrel,led-mode = <0>; 74 }; 75 76 tja1102_phy0: ethernet-phy@4 { 77 reg = <0x4>; 78 79 interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; 80 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 81 reset-assert-us = <20>; 82 reset-deassert-us = <2000>; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 tja1102_phy1: ethernet-phy@5 { 87 reg = <0x5>; 88 89 interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; 90 }; 91 }; 92 }; 93 94 reg_5v0: regulator-5v0 { 95 compatible = "regulator-fixed"; 96 regulator-name = "5v0"; 97 regulator-min-microvolt = <5000000>; 98 regulator-max-microvolt = <5000000>; 99 }; 100 101 reg_otg_vbus: regulator-otg-vbus { 102 compatible = "regulator-fixed"; 103 regulator-name = "otg-vbus"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { 111 compatible = "mmc-pwrseq-simple"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_wifi_npd>; 114 reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; 115 }; 116}; 117 118&can1 { 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_can1>; 121 xceiver-supply = <®_5v0>; 122 status = "okay"; 123}; 124 125&ecspi2 { 126 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_ecspi2>; 129 status = "okay"; 130 131 switch@0 { 132 compatible = "nxp,sja1105q"; 133 reg = <0>; 134 spi-max-frequency = <4000000>; 135 spi-rx-delay-us = <1>; 136 spi-tx-delay-us = <1>; 137 spi-cpha; 138 139 reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; 140 141 clocks = <&clock_sja1105>; 142 143 ports { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 port@0 { 148 reg = <0>; 149 label = "usb"; 150 phy-handle = <&usbeth_phy>; 151 phy-mode = "rmii"; 152 }; 153 154 port@1 { 155 reg = <1>; 156 label = "t1slave"; 157 phy-handle = <&tja1102_phy1>; 158 phy-mode = "rmii"; 159 }; 160 161 port@2 { 162 reg = <2>; 163 label = "t1master"; 164 phy-handle = <&tja1102_phy0>; 165 phy-mode = "rmii"; 166 167 }; 168 169 port@3 { 170 reg = <3>; 171 label = "rj45"; 172 phy-handle = <&rgmii_phy>; 173 phy-mode = "rgmii-id"; 174 }; 175 176 port@4 { 177 reg = <4>; 178 label = "cpu"; 179 ethernet = <&fec>; 180 phy-mode = "rgmii-id"; 181 182 fixed-link { 183 speed = <100>; 184 full-duplex; 185 }; 186 }; 187 }; 188 }; 189}; 190 191&ecspi3 { 192 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_ecspi3>; 195 status = "okay"; 196 197 can@0 { 198 compatible = "microchip,mcp251xfd"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_can2>; 201 reg = <0>; 202 clocks = <&clock_mcp251xfd>; 203 spi-max-frequency = <10000000>; 204 interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; 205 }; 206}; 207 208&fec { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_enet>; 211 status = "okay"; 212 213 phy-mode = "rgmii"; 214 215 fixed-link { 216 speed = <100>; 217 full-duplex; 218 }; 219 220 mdio { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 /* Microchip KSZ9031 */ 225 rgmii_phy: ethernet-phy@2 { 226 reg = <2>; 227 228 interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; 229 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 230 reset-assert-us = <10000>; 231 reset-deassert-us = <1000>; 232 233 clocks = <&clock_ksz9031>; 234 }; 235 }; 236}; 237 238&gpio1 { 239 gpio-line-names = 240 "", "SD1_CD", "", "", "", "", "", "", 241 "", "", "", "", "", "", "", "", 242 "", "", "", "", "", "", "", "", 243 "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; 244}; 245 246&gpio2 { 247 gpio-line-names = 248 "", "", "", "", "", "", "", "", 249 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", 250 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", 251 "", "", "", "", "", "", "", "", 252 "", "", "ECSPI2_SS0", "", "", "", "", ""; 253}; 254 255&gpio3 { 256 gpio-line-names = 257 "", "", "", "", "", "", "", "", 258 "", "", "", "", "", "", "", "", 259 "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", 260 "", "", "", "", "", "", "", ""; 261}; 262 263&gpio4 { 264 gpio-line-names = 265 "", "", "", "", "", "", "", "", 266 "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", 267 "", "", "", "", "", "", "", "", 268 "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; 269}; 270 271&gpio5 { 272 gpio-line-names = 273 "", "", "", "", "", "SW_RESET", "", "", 274 "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", 275 "PHY0_INT", "", "", "", 276 "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", 277 "", "", 278 "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", 279 "DISP0_EN", "CAM_GPIO0"; 280}; 281 282&gpio6 { 283 gpio-line-names = 284 "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", 285 "CAM_LOCK", "", "POWER_TG", 286 "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", 287 "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", 288 "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", 289 "", "", "", "", "", "", "", ""; 290}; 291 292&i2c1 { 293 clock-frequency = <100000>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_i2c1>; 296 status = "okay"; 297 298 /* additional i2c devices are added automatically by the boot loader */ 299}; 300 301&i2c3 { 302 adc@49 { 303 compatible = "ti,ads1015"; 304 reg = <0x49>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 /* VIN */ 309 channel@4 { 310 reg = <4>; 311 ti,gain = <1>; 312 ti,datarate = <3>; 313 }; 314 315 /* VBUS */ 316 channel@5 { 317 reg = <5>; 318 ti,gain = <1>; 319 ti,datarate = <3>; 320 }; 321 322 /* ICHG */ 323 channel@6 { 324 reg = <6>; 325 ti,gain = <1>; 326 ti,datarate = <3>; 327 }; 328 329 channel@7 { 330 reg = <7>; 331 ti,gain = <1>; 332 ti,datarate = <3>; 333 }; 334 }; 335}; 336 337&uart4 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_uart4>; 340 status = "okay"; 341}; 342 343&usbotg { 344 vbus-supply = <®_otg_vbus>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_usbotg>; 347 phy_type = "utmi"; 348 dr_mode = "host"; 349 disable-over-current; 350 status = "okay"; 351}; 352 353&usbphynop1 { 354 status = "disabled"; 355}; 356 357&usbphynop2 { 358 status = "disabled"; 359}; 360 361&usdhc1 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_usdhc1>; 364 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 365 no-1-8-v; 366 disable-wp; 367 cap-sd-highspeed; 368 no-mmc; 369 no-sdio; 370 status = "okay"; 371}; 372 373&usdhc2 { 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_usdhc2>; 376 no-1-8-v; 377 non-removable; 378 mmc-pwrseq = <&usdhc2_wifi_pwrseq>; 379 status = "okay"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 383 brcmf: bcrmf@1 { 384 reg = <1>; 385 compatible = "brcm,bcm4329-fmac"; 386 }; 387}; 388 389&usdhc3 { 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_usdhc3>; 392 bus-width = <8>; 393 no-1-8-v; 394 non-removable; 395 no-sd; 396 no-sdio; 397 status = "okay"; 398}; 399 400&iomuxc { 401 pinctrl_can1: can1grp { 402 fsl,pins = < 403 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 404 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 405 /* CAN1_SR */ 406 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 407 >; 408 }; 409 410 pinctrl_can2: can2grp { 411 fsl,pins = < 412 /* CAN2_nINT */ 413 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 414 /* CAN2_SR */ 415 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 416 >; 417 }; 418 419 pinctrl_ecspi2: ecspi2grp { 420 fsl,pins = < 421 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 422 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 423 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 424 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 425 >; 426 }; 427 428 pinctrl_ecspi3: ecspi3grp { 429 fsl,pins = < 430 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 431 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 432 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 433 /* CS */ 434 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 435 >; 436 }; 437 438 pinctrl_enet: enetgrp { 439 fsl,pins = < 440 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 441 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 442 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 443 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 444 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 445 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 446 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 447 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 448 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 449 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 450 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 451 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 452 453 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 454 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 455 456 /* Configure clock provider for RGMII ref clock */ 457 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 458 /* Configure clock consumer for RGMII ref clock */ 459 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 460 461 /* SJA1105Q switch reset */ 462 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 463 464 /* phy3/rgmii_phy reset */ 465 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 466 /* phy3/rgmii_phy int */ 467 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 468 >; 469 }; 470 471 pinctrl_i2c1: i2c1grp { 472 fsl,pins = < 473 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 474 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 475 >; 476 }; 477 478 pinctrl_mdio: mdiogrp { 479 fsl,pins = < 480 /* phy0/usbeth_phy reset */ 481 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 482 /* phy0/usbeth_phy int */ 483 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 484 485 /* phy12/tja1102_phy0 reset */ 486 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 487 /* phy12/tja1102_phy0 int */ 488 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 489 /* phy12/tja1102_phy0 enable. Set 100K pull-up */ 490 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 491 >; 492 }; 493 494 pinctrl_uart4: uart4grp { 495 fsl,pins = < 496 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 497 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 498 >; 499 }; 500 501 pinctrl_usbotg: usbotggrp { 502 fsl,pins = < 503 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 504 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 505 >; 506 }; 507 508 pinctrl_usdhc1: usdhc1grp { 509 fsl,pins = < 510 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 511 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 512 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 513 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 514 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 515 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 516 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 517 >; 518 }; 519 520 pinctrl_usdhc2: usdhc2grp { 521 fsl,pins = < 522 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 523 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 524 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 525 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 526 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 527 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 528 >; 529 }; 530 531 pinctrl_usdhc3: usdhc3grp { 532 fsl,pins = < 533 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 534 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 535 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 536 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 537 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 538 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 539 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 540 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 541 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 542 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 543 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 544 >; 545 }; 546 547 pinctrl_wifi_npd: wifinpd { 548 fsl,pins = < 549 /* WL_REG_ON */ 550 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 551 >; 552 }; 553}; 554