1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2014 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include "imx6sx.dtsi" 10 11/ { 12 model = "Freescale i.MX6 SoloX SDB Board"; 13 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x80000000 0x40000000>; 22 }; 23 24 backlight_display: backlight-display { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm3 0 5000000>; 27 brightness-levels = <0 4 8 16 32 64 128 255>; 28 default-brightness-level = <6>; 29 }; 30 31 gpio-keys { 32 compatible = "gpio-keys"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_keys>; 35 36 volume-up { 37 label = "Volume Up"; 38 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; 39 linux,code = <KEY_VOLUMEUP>; 40 wakeup-source; 41 }; 42 43 volume-down { 44 label = "Volume Down"; 45 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 46 linux,code = <KEY_VOLUMEDOWN>; 47 wakeup-source; 48 }; 49 }; 50 51 vcc_sd3: regulator-vcc-sd3 { 52 compatible = "regulator-fixed"; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_vcc_sd3>; 55 regulator-name = "VCC_SD3"; 56 regulator-min-microvolt = <3000000>; 57 regulator-max-microvolt = <3000000>; 58 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 59 enable-active-high; 60 }; 61 62 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 63 compatible = "regulator-fixed"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_usb_otg1>; 66 regulator-name = "usb_otg1_vbus"; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 70 enable-active-high; 71 }; 72 73 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 74 compatible = "regulator-fixed"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_usb_otg2>; 77 regulator-name = "usb_otg2_vbus"; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 81 enable-active-high; 82 }; 83 84 reg_psu_5v: regulator-psu-5v { 85 compatible = "regulator-fixed"; 86 regulator-name = "PSU-5V0"; 87 regulator-min-microvolt = <5000000>; 88 regulator-max-microvolt = <5000000>; 89 }; 90 91 reg_lcd_3v3: regulator-lcd-3v3 { 92 compatible = "regulator-fixed"; 93 regulator-name = "lcd-3v3"; 94 gpio = <&gpio3 27 0>; 95 enable-active-high; 96 }; 97 98 reg_peri_3v3: regulator-peri-3v3 { 99 compatible = "regulator-fixed"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_peri_3v3>; 102 regulator-name = "peri_3v3"; 103 regulator-min-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>; 105 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 reg_enet_3v3: regulator-enet-3v3 { 111 compatible = "regulator-fixed"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_enet_3v3>; 114 regulator-name = "enet_3v3"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; 118 regulator-boot-on; 119 regulator-always-on; 120 }; 121 122 reg_pcie_gpio: regulator-pcie-gpio { 123 compatible = "regulator-fixed"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_pcie_reg>; 126 regulator-name = "MPCIE_3V3"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; 130 enable-active-high; 131 }; 132 133 reg_lcd_5v: regulator-lcd-5v { 134 compatible = "regulator-fixed"; 135 regulator-name = "lcd-5v0"; 136 regulator-min-microvolt = <5000000>; 137 regulator-max-microvolt = <5000000>; 138 }; 139 140 reg_can_en: regulator-can-en { 141 compatible = "regulator-fixed"; 142 regulator-name = "can-en"; 143 regulator-min-microvolt = <3300000>; 144 regulator-max-microvolt = <3300000>; 145 }; 146 147 reg_can_stby: regulator-can-stby { 148 compatible = "regulator-fixed"; 149 regulator-name = "can-stby"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 }; 153 154 sound { 155 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_hp>; 158 model = "wm8962-audio"; 159 ssi-controller = <&ssi2>; 160 audio-codec = <&codec>; 161 audio-routing = 162 "Headphone Jack", "HPOUTL", 163 "Headphone Jack", "HPOUTR", 164 "Ext Spk", "SPKOUTL", 165 "Ext Spk", "SPKOUTR", 166 "AMIC", "MICBIAS", 167 "IN3R", "AMIC"; 168 mux-int-port = <2>; 169 mux-ext-port = <6>; 170 hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; 171 }; 172 173 panel { 174 compatible = "sii,43wvf1g"; 175 backlight = <&backlight_display>; 176 dvdd-supply = <®_lcd_3v3>; 177 avdd-supply = <®_lcd_5v>; 178 179 port { 180 panel_in: endpoint { 181 remote-endpoint = <&display_out>; 182 }; 183 }; 184 }; 185 186 sound-spdif { 187 compatible = "fsl,imx-audio-spdif", 188 "fsl,imx6sx-sdb-spdif"; 189 model = "imx-spdif"; 190 spdif-controller = <&spdif>; 191 spdif-out; 192 }; 193 194}; 195 196&audmux { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_audmux>; 199 status = "okay"; 200}; 201 202&fec1 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_enet1>; 205 phy-supply = <®_enet_3v3>; 206 phy-mode = "rgmii-id"; 207 phy-handle = <ðphy1>; 208 phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 209 fsl,magic-packet; 210 status = "okay"; 211 212 mdio { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 ethphy1: ethernet-phy@1 { 217 reg = <1>; 218 }; 219 220 ethphy2: ethernet-phy@2 { 221 reg = <2>; 222 }; 223 }; 224}; 225 226&fec2 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_enet2>; 229 phy-mode = "rgmii-id"; 230 phy-handle = <ðphy2>; 231 fsl,magic-packet; 232 status = "okay"; 233}; 234 235&flexcan1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_flexcan1>; 238 xceiver-supply = <®_can_stby>; 239 status = "okay"; 240}; 241 242&flexcan2 { 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_flexcan2>; 245 xceiver-supply = <®_can_stby>; 246 status = "okay"; 247}; 248 249&i2c3 { 250 clock-frequency = <100000>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c3>; 253 status = "okay"; 254}; 255 256&i2c4 { 257 clock-frequency = <100000>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_i2c4>; 260 status = "okay"; 261 262 codec: wm8962@1a { 263 compatible = "wlf,wm8962"; 264 reg = <0x1a>; 265 clocks = <&clks IMX6SX_CLK_AUDIO>; 266 DCVDD-supply = <&vgen4_reg>; 267 DBVDD-supply = <&vgen4_reg>; 268 AVDD-supply = <&vgen4_reg>; 269 CPVDD-supply = <&vgen4_reg>; 270 MICVDD-supply = <&vgen3_reg>; 271 PLLVDD-supply = <&vgen4_reg>; 272 SPKVDD1-supply = <®_psu_5v>; 273 SPKVDD2-supply = <®_psu_5v>; 274 }; 275}; 276 277&pcie { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_pcie>; 280 reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; 281 vpcie-supply = <®_pcie_gpio>; 282 status = "okay"; 283}; 284 285&lcdif1 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_lcd>; 288 status = "okay"; 289 290 port { 291 display_out: endpoint { 292 remote-endpoint = <&panel_in>; 293 }; 294 }; 295}; 296 297&pwm3 { 298 #pwm-cells = <2>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_pwm3>; 301 status = "okay"; 302}; 303 304&snvs_poweroff { 305 status = "okay"; 306}; 307 308&sai1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_sai1>; 311 status = "disabled"; 312}; 313 314&spdif { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_spdif>; 317 assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; 318 assigned-clock-rates = <24576000>; 319 status = "okay"; 320}; 321 322&ssi2 { 323 status = "okay"; 324}; 325 326&uart1 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_uart1>; 329 status = "okay"; 330}; 331 332&uart5 { /* for bluetooth */ 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_uart5>; 335 uart-has-rtscts; 336 status = "okay"; 337}; 338 339&usbotg1 { 340 vbus-supply = <®_usb_otg1_vbus>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_usb_otg1_id>; 343 status = "okay"; 344}; 345 346&usbotg2 { 347 vbus-supply = <®_usb_otg2_vbus>; 348 dr_mode = "host"; 349 status = "okay"; 350}; 351 352&usbphy1 { 353 fsl,tx-d-cal = <106>; 354}; 355 356&usbphy2 { 357 fsl,tx-d-cal = <106>; 358}; 359 360&usdhc2 { 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_usdhc2>; 363 non-removable; 364 no-1-8-v; 365 keep-power-in-suspend; 366 wakeup-source; 367 status = "okay"; 368}; 369 370&usdhc3 { 371 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 372 pinctrl-0 = <&pinctrl_usdhc3>; 373 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 374 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 375 bus-width = <8>; 376 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 377 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 378 keep-power-in-suspend; 379 wakeup-source; 380 vmmc-supply = <&vcc_sd3>; 381 status = "okay"; 382}; 383 384&usdhc4 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_usdhc4>; 387 cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; 388 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; 389 status = "okay"; 390}; 391 392&wdog1 { 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_wdog>; 395 fsl,ext-reset-output; 396}; 397 398&iomuxc { 399 imx6x-sdb { 400 pinctrl_audmux: audmuxgrp { 401 fsl,pins = < 402 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 403 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 404 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 405 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 406 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 407 >; 408 }; 409 410 pinctrl_enet1: enet1grp { 411 fsl,pins = < 412 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 413 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 414 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 415 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 416 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 417 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 418 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 419 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 420 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 421 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 422 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 423 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 424 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 425 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 426 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 427 /* phy reset */ 428 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 429 >; 430 }; 431 432 pinctrl_enet_3v3: enet3v3grp { 433 fsl,pins = < 434 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 435 >; 436 }; 437 438 pinctrl_enet2: enet2grp { 439 fsl,pins = < 440 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 441 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 442 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 443 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 444 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 445 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 446 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 447 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 448 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 449 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 450 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 451 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 452 >; 453 }; 454 455 pinctrl_flexcan1: flexcan1grp { 456 fsl,pins = < 457 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 458 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 459 >; 460 }; 461 462 pinctrl_flexcan2: flexcan2grp { 463 fsl,pins = < 464 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 465 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 466 >; 467 }; 468 469 pinctrl_gpio_keys: gpio_keysgrp { 470 fsl,pins = < 471 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 472 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 473 >; 474 }; 475 476 pinctrl_hp: hpgrp { 477 fsl,pins = < 478 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 479 >; 480 }; 481 482 pinctrl_i2c1: i2c1grp { 483 fsl,pins = < 484 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 485 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 486 >; 487 }; 488 489 pinctrl_i2c3: i2c3grp { 490 fsl,pins = < 491 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 492 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 493 >; 494 }; 495 496 pinctrl_i2c4: i2c4grp { 497 fsl,pins = < 498 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 499 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 500 >; 501 }; 502 503 pinctrl_lcd: lcdgrp { 504 fsl,pins = < 505 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 506 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 507 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 508 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 509 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 510 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 511 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 512 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 513 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 514 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 515 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 516 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 517 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 518 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 519 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 520 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 521 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 522 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 523 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 524 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 525 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 526 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 527 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 528 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 529 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 530 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 531 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 532 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 533 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 534 >; 535 }; 536 537 pinctrl_mqs: mqsgrp { 538 fsl,pins = < 539 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 540 MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 541 >; 542 }; 543 544 pinctrl_pcie: pciegrp { 545 fsl,pins = < 546 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 547 >; 548 }; 549 550 pinctrl_pcie_reg: pciereggrp { 551 fsl,pins = < 552 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 553 >; 554 }; 555 556 pinctrl_peri_3v3: peri3v3grp { 557 fsl,pins = < 558 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 559 >; 560 }; 561 562 pinctrl_pwm3: pwm3grp-1 { 563 fsl,pins = < 564 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 565 >; 566 }; 567 568 pinctrl_qspi2: qspi2grp { 569 fsl,pins = < 570 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 571 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 572 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 573 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 574 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 575 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 576 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 577 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 578 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 579 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 580 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 581 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 582 >; 583 }; 584 585 pinctrl_vcc_sd3: vccsd3grp { 586 fsl,pins = < 587 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 588 >; 589 }; 590 591 pinctrl_sai1: sai1grp { 592 fsl,pins = < 593 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 594 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 595 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 596 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 597 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 598 >; 599 }; 600 601 pinctrl_spdif: spdifgrp { 602 fsl,pins = < 603 MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 604 >; 605 }; 606 607 pinctrl_uart1: uart1grp { 608 fsl,pins = < 609 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 610 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 611 >; 612 }; 613 614 pinctrl_uart5: uart5grp { 615 fsl,pins = < 616 MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 617 MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 618 MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 619 MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 620 >; 621 }; 622 623 pinctrl_usb_otg1: usbotg1grp { 624 fsl,pins = < 625 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 626 >; 627 }; 628 629 pinctrl_usb_otg1_id: usbotg1idgrp { 630 fsl,pins = < 631 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 632 >; 633 }; 634 635 pinctrl_usb_otg2: usbot2ggrp { 636 fsl,pins = < 637 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 638 >; 639 }; 640 641 pinctrl_usdhc2: usdhc2grp { 642 fsl,pins = < 643 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 644 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 645 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 646 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 647 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 648 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 649 >; 650 }; 651 652 pinctrl_usdhc3: usdhc3grp { 653 fsl,pins = < 654 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 655 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 656 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 657 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 658 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 659 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 660 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 661 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 662 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 663 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 664 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 665 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 666 >; 667 }; 668 669 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 670 fsl,pins = < 671 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 672 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 673 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 674 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 675 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 676 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 677 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 678 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 679 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 680 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 681 >; 682 }; 683 684 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 685 fsl,pins = < 686 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 687 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 688 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 689 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 690 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 691 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 692 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 693 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 694 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 695 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 696 >; 697 }; 698 699 pinctrl_usdhc4: usdhc4grp { 700 fsl,pins = < 701 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 702 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 703 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 704 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 705 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 706 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 707 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 708 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 709 >; 710 }; 711 712 pinctrl_wdog: wdoggrp { 713 fsl,pins = < 714 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 715 >; 716 }; 717 }; 718}; 719