1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5/ { 6 chosen { 7 stdout-path = &uart1; 8 }; 9 10 memory@80000000 { 11 device_type = "memory"; 12 reg = <0x80000000 0x20000000>; 13 }; 14 15 backlight_display: backlight-display { 16 compatible = "pwm-backlight"; 17 pwms = <&pwm1 0 5000000>; 18 brightness-levels = <0 4 8 16 32 64 128 255>; 19 default-brightness-level = <6>; 20 status = "okay"; 21 }; 22 23 24 reg_sd1_vmmc: regulator-sd1-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "VSD_3V3"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 reg_peri_3v3: regulator-peri-3v3 { 34 compatible = "regulator-fixed"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_peri_3v3>; 37 regulator-name = "VPERI_3V3"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 41 /* 42 * If you want to want to make this dynamic please 43 * check schematics and test all affected peripherals: 44 * 45 * - sensors 46 * - ethernet phy 47 * - can 48 * - bluetooth 49 * - wm8960 audio codec 50 * - ov5640 camera 51 */ 52 regulator-always-on; 53 }; 54 55 reg_can_3v3: regulator-can-3v3 { 56 compatible = "regulator-fixed"; 57 regulator-name = "can-3v3"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 61 }; 62 63 sound { 64 compatible = "simple-audio-card"; 65 simple-audio-card,name = "mx6ul-wm8960"; 66 simple-audio-card,format = "i2s"; 67 simple-audio-card,bitclock-master = <&dailink_master>; 68 simple-audio-card,frame-master = <&dailink_master>; 69 simple-audio-card,widgets = 70 "Microphone", "Mic Jack", 71 "Line", "Line In", 72 "Line", "Line Out", 73 "Speaker", "Speaker", 74 "Headphone", "Headphone Jack"; 75 simple-audio-card,routing = 76 "Headphone Jack", "HP_L", 77 "Headphone Jack", "HP_R", 78 "Speaker", "SPK_LP", 79 "Speaker", "SPK_LN", 80 "Speaker", "SPK_RP", 81 "Speaker", "SPK_RN", 82 "LINPUT1", "Mic Jack", 83 "LINPUT3", "Mic Jack", 84 "RINPUT1", "Mic Jack", 85 "RINPUT2", "Mic Jack"; 86 87 simple-audio-card,cpu { 88 sound-dai = <&sai2>; 89 }; 90 91 dailink_master: simple-audio-card,codec { 92 sound-dai = <&codec>; 93 clocks = <&clks IMX6UL_CLK_SAI2>; 94 }; 95 }; 96 97 spi4 { 98 compatible = "spi-gpio"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_spi4>; 101 status = "okay"; 102 gpio-sck = <&gpio5 11 0>; 103 gpio-mosi = <&gpio5 10 0>; 104 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; 105 num-chipselects = <1>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 gpio_spi: gpio@0 { 110 compatible = "fairchild,74hc595"; 111 gpio-controller; 112 #gpio-cells = <2>; 113 reg = <0>; 114 registers-number = <1>; 115 spi-max-frequency = <100000>; 116 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 117 }; 118 }; 119 120 panel { 121 compatible = "innolux,at043tn24"; 122 backlight = <&backlight_display>; 123 124 port { 125 panel_in: endpoint { 126 remote-endpoint = <&display_out>; 127 }; 128 }; 129 }; 130}; 131 132&clks { 133 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 134 assigned-clock-rates = <786432000>; 135}; 136 137&i2c2 { 138 clock-frequency = <100000>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_i2c2>; 141 status = "okay"; 142 143 codec: wm8960@1a { 144 #sound-dai-cells = <0>; 145 compatible = "wlf,wm8960"; 146 reg = <0x1a>; 147 wlf,shared-lrclk; 148 }; 149 150 camera@3c { 151 compatible = "ovti,ov5640"; 152 reg = <0x3c>; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_camera_clock>; 155 clocks = <&clks IMX6UL_CLK_CSI>; 156 clock-names = "xclk"; 157 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; 158 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; 159 160 port { 161 ov5640_to_parallel: endpoint { 162 remote-endpoint = <¶llel_from_ov5640>; 163 bus-width = <8>; 164 data-shift = <2>; /* lines 9:2 are used */ 165 hsync-active = <0>; 166 vsync-active = <0>; 167 pclk-sample = <1>; 168 }; 169 }; 170 }; 171}; 172 173&csi { 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_csi1>; 176 status = "okay"; 177 178 port { 179 parallel_from_ov5640: endpoint { 180 remote-endpoint = <&ov5640_to_parallel>; 181 bus-type = <5>; /* Parallel bus */ 182 }; 183 }; 184}; 185 186&fec1 { 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_enet1>; 189 phy-mode = "rmii"; 190 phy-handle = <ðphy0>; 191 phy-supply = <®_peri_3v3>; 192 status = "okay"; 193}; 194 195&fec2 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_enet2>; 198 phy-mode = "rmii"; 199 phy-handle = <ðphy1>; 200 phy-supply = <®_peri_3v3>; 201 status = "okay"; 202 203 mdio { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 ethphy0: ethernet-phy@2 { 208 compatible = "ethernet-phy-id0022.1560"; 209 reg = <2>; 210 micrel,led-mode = <1>; 211 clocks = <&clks IMX6UL_CLK_ENET_REF>; 212 clock-names = "rmii-ref"; 213 214 }; 215 216 ethphy1: ethernet-phy@1 { 217 compatible = "ethernet-phy-id0022.1560"; 218 reg = <1>; 219 micrel,led-mode = <1>; 220 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 221 clock-names = "rmii-ref"; 222 }; 223 }; 224}; 225 226&can1 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_flexcan1>; 229 xceiver-supply = <®_can_3v3>; 230 status = "okay"; 231}; 232 233&can2 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_flexcan2>; 236 xceiver-supply = <®_can_3v3>; 237 status = "okay"; 238}; 239 240&gpio_spi { 241 eth0-phy-hog { 242 gpio-hog; 243 gpios = <1 GPIO_ACTIVE_HIGH>; 244 output-high; 245 line-name = "eth0-phy"; 246 }; 247 248 eth1-phy-hog { 249 gpio-hog; 250 gpios = <2 GPIO_ACTIVE_HIGH>; 251 output-high; 252 line-name = "eth1-phy"; 253 }; 254}; 255 256&i2c1 { 257 clock-frequency = <100000>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_i2c1>; 260 status = "okay"; 261 262 magnetometer@e { 263 compatible = "fsl,mag3110"; 264 reg = <0x0e>; 265 vdd-supply = <®_peri_3v3>; 266 vddio-supply = <®_peri_3v3>; 267 }; 268}; 269 270&lcdif { 271 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 272 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_lcdif_dat 275 &pinctrl_lcdif_ctrl>; 276 status = "okay"; 277 278 port { 279 display_out: endpoint { 280 remote-endpoint = <&panel_in>; 281 }; 282 }; 283}; 284 285&pwm1 { 286 #pwm-cells = <2>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_pwm1>; 289 status = "okay"; 290}; 291 292&qspi { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_qspi>; 295 status = "okay"; 296 297 flash0: n25q256a@0 { 298 #address-cells = <1>; 299 #size-cells = <1>; 300 compatible = "micron,n25q256a", "jedec,spi-nor"; 301 spi-max-frequency = <29000000>; 302 spi-rx-bus-width = <4>; 303 spi-tx-bus-width = <4>; 304 reg = <0>; 305 }; 306}; 307 308&sai2 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_sai2>; 311 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 312 <&clks IMX6UL_CLK_SAI2>; 313 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 314 assigned-clock-rates = <0>, <12288000>; 315 fsl,sai-mclk-direction-output; 316 status = "okay"; 317}; 318 319&snvs_poweroff { 320 status = "okay"; 321}; 322 323&snvs_pwrkey { 324 status = "okay"; 325}; 326 327&tsc { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_tsc>; 330 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 331 measure-delay-time = <0xffff>; 332 pre-charge-time = <0xfff>; 333 status = "okay"; 334}; 335 336&uart1 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_uart1>; 339 status = "okay"; 340}; 341 342&uart2 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_uart2>; 345 uart-has-rtscts; 346 status = "okay"; 347}; 348 349&usbotg1 { 350 dr_mode = "otg"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_usb_otg1>; 353 status = "okay"; 354}; 355 356&usbotg2 { 357 dr_mode = "host"; 358 disable-over-current; 359 status = "okay"; 360}; 361 362&usbphy1 { 363 fsl,tx-d-cal = <106>; 364}; 365 366&usbphy2 { 367 fsl,tx-d-cal = <106>; 368}; 369 370&usdhc1 { 371 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 372 pinctrl-0 = <&pinctrl_usdhc1>; 373 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 374 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 375 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 376 keep-power-in-suspend; 377 wakeup-source; 378 vmmc-supply = <®_sd1_vmmc>; 379 status = "okay"; 380}; 381 382&usdhc2 { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_usdhc2>; 385 no-1-8-v; 386 broken-cd; 387 keep-power-in-suspend; 388 wakeup-source; 389 status = "okay"; 390}; 391 392&wdog1 { 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_wdog>; 395 fsl,ext-reset-output; 396}; 397 398&iomuxc { 399 pinctrl-names = "default"; 400 401 pinctrl_camera_clock: cameraclockgrp { 402 fsl,pins = < 403 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 404 >; 405 }; 406 407 pinctrl_csi1: csi1grp { 408 fsl,pins = < 409 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 410 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 411 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 412 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 413 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 414 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 415 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 416 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 417 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 418 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 419 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 420 >; 421 }; 422 423 pinctrl_enet1: enet1grp { 424 fsl,pins = < 425 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 426 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 427 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 428 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 429 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 430 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 431 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 432 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 433 >; 434 }; 435 436 pinctrl_enet2: enet2grp { 437 fsl,pins = < 438 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 439 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 440 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 441 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 442 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 443 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 444 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 445 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 446 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 447 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 448 >; 449 }; 450 451 pinctrl_flexcan1: flexcan1grp{ 452 fsl,pins = < 453 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 454 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 455 >; 456 }; 457 458 pinctrl_flexcan2: flexcan2grp{ 459 fsl,pins = < 460 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 461 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 462 >; 463 }; 464 465 pinctrl_i2c1: i2c1grp { 466 fsl,pins = < 467 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 468 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 469 >; 470 }; 471 472 pinctrl_i2c2: i2c2grp { 473 fsl,pins = < 474 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 475 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 476 >; 477 }; 478 479 pinctrl_lcdif_dat: lcdifdatgrp { 480 fsl,pins = < 481 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 482 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 483 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 484 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 485 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 486 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 487 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 488 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 489 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 490 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 491 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 492 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 493 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 494 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 495 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 496 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 497 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 498 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 499 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 500 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 501 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 502 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 503 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 504 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 505 >; 506 }; 507 508 pinctrl_lcdif_ctrl: lcdifctrlgrp { 509 fsl,pins = < 510 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 511 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 512 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 513 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 514 /* used for lcd reset */ 515 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 516 >; 517 }; 518 519 pinctrl_qspi: qspigrp { 520 fsl,pins = < 521 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 522 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 523 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 524 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 525 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 526 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 527 >; 528 }; 529 530 pinctrl_sai2: sai2grp { 531 fsl,pins = < 532 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 533 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 534 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 535 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 536 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 537 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 538 >; 539 }; 540 541 pinctrl_peri_3v3: peri3v3grp { 542 fsl,pins = < 543 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 544 >; 545 }; 546 547 pinctrl_pwm1: pwm1grp { 548 fsl,pins = < 549 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 550 >; 551 }; 552 553 pinctrl_sim2: sim2grp { 554 fsl,pins = < 555 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 556 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 557 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 558 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 559 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 560 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 561 >; 562 }; 563 564 pinctrl_spi4: spi4grp { 565 fsl,pins = < 566 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 567 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 568 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 569 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 570 >; 571 }; 572 573 pinctrl_tsc: tscgrp { 574 fsl,pins = < 575 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 576 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 577 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 578 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 579 >; 580 }; 581 582 pinctrl_uart1: uart1grp { 583 fsl,pins = < 584 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 585 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 586 >; 587 }; 588 589 pinctrl_uart2: uart2grp { 590 fsl,pins = < 591 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 592 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 593 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 594 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 595 >; 596 }; 597 598 pinctrl_usb_otg1: usbotg1grp { 599 fsl,pins = < 600 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 601 >; 602 }; 603 604 pinctrl_usdhc1: usdhc1grp { 605 fsl,pins = < 606 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 607 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 608 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 609 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 610 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 611 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 612 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 613 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 614 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 615 >; 616 }; 617 618 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 619 fsl,pins = < 620 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 621 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 622 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 623 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 624 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 625 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 626 627 >; 628 }; 629 630 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 631 fsl,pins = < 632 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 633 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 634 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 635 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 636 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 637 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 638 >; 639 }; 640 641 pinctrl_usdhc2: usdhc2grp { 642 fsl,pins = < 643 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 644 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 645 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 646 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 647 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 648 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 649 >; 650 }; 651 652 pinctrl_wdog: wdoggrp { 653 fsl,pins = < 654 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 655 >; 656 }; 657}; 658