1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (c) 2016 Protonic Holland 4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix 5 */ 6 7/dts-v1/; 8#include "imx6ul.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 model = "Protonic PRTI6G Board"; 13 compatible = "prt,prti6g", "fsl,imx6ul"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 clock_ksz8081_in: clock-ksz8081-in { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <25000000>; 23 }; 24 25 clock_ksz8081_out: clock-ksz8081-out { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <50000000>; 29 }; 30 31 leds { 32 compatible = "gpio-leds"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_leds>; 35 36 led-0 { 37 label = "debug0"; 38 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 39 linux,default-trigger = "heartbeat"; 40 }; 41 }; 42 43 reg_3v2: regulator-3v2 { 44 compatible = "regulator-fixed"; 45 regulator-name = "3v2"; 46 regulator-min-microvolt = <3200000>; 47 regulator-max-microvolt = <3200000>; 48 }; 49}; 50 51&can1 { 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_can1>; 54 status = "okay"; 55}; 56 57&can2 { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_can2>; 60 status = "okay"; 61}; 62 63&ecspi1 { 64 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_ecspi1>; 67 status = "okay"; 68 69 flash@0 { 70 compatible = "jedec,spi-nor"; 71 reg = <0>; 72 spi-max-frequency = <20000000>; 73 }; 74}; 75 76&ecspi2 { 77 cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_ecspi2>; 80 status = "okay"; 81 82 spi@0 { 83 compatible = "spidev"; 84 reg = <0>; 85 spi-max-frequency = <1000000>; 86 }; 87}; 88 89&fec1 { 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_eth1>; 92 phy-mode = "rmii"; 93 phy-handle = <&rmii_phy>; 94 clocks = <&clks IMX6UL_CLK_ENET>, 95 <&clks IMX6UL_CLK_ENET_AHB>, 96 <&clks IMX6UL_CLK_ENET_PTP>, 97 <&clock_ksz8081_out>; 98 clock-names = "ipg", "ahb", "ptp", 99 "enet_clk_ref"; 100 status = "okay"; 101 102 mdio { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 /* Microchip KSZ8081RNA PHY */ 107 rmii_phy: ethernet-phy@0 { 108 reg = <0>; 109 interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; 110 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 111 reset-assert-us = <10000>; 112 reset-deassert-us = <300>; 113 clocks = <&clock_ksz8081_in>; 114 clock-names = "rmii-ref"; 115 }; 116 }; 117}; 118 119&i2c1 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_i2c1>; 122 clock-frequency = <100000>; 123 status = "okay"; 124 125 /* additional i2c devices are added automatically by the boot loader */ 126}; 127 128&i2c2 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_i2c2>; 131 clock-frequency = <100000>; 132 status = "okay"; 133 134 adc@49 { 135 compatible = "ti,ads1015"; 136 reg = <0x49>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 channel@4 { 141 reg = <4>; 142 ti,gain = <3>; 143 ti,datarate = <3>; 144 }; 145 146 channel@5 { 147 reg = <5>; 148 ti,gain = <3>; 149 ti,datarate = <3>; 150 }; 151 152 channel@6 { 153 reg = <6>; 154 ti,gain = <3>; 155 ti,datarate = <3>; 156 }; 157 158 channel@7 { 159 reg = <7>; 160 ti,gain = <3>; 161 ti,datarate = <3>; 162 }; 163 }; 164 165 rtc@51 { 166 compatible = "nxp,pcf8563"; 167 reg = <0x51>; 168 }; 169 170 temperature-sensor@70 { 171 compatible = "ti,tmp103"; 172 reg = <0x70>; 173 }; 174}; 175 176&uart1 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_uart1>; 179 status = "okay"; 180}; 181 182&usbotg1 { 183 dr_mode = "host"; 184 status = "okay"; 185}; 186 187&usdhc1 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_usdhc1>; 190 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; 191 vmmc-supply = <®_3v2>; 192 no-1-8-v; 193 disable-wp; 194 cap-sd-highspeed; 195 no-mmc; 196 no-sdio; 197 status = "okay"; 198}; 199 200&usdhc2 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_usdhc2>; 203 bus-width = <8>; 204 no-1-8-v; 205 non-removable; 206 no-sd; 207 no-sdio; 208 status = "okay"; 209}; 210 211&iomuxc { 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_hog>; 214 215 pinctrl_can1: can1grp { 216 fsl,pins = < 217 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 218 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 219 /* SR */ 220 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 221 /* TERM */ 222 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 223 /* nSMBALERT */ 224 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 225 >; 226 }; 227 228 pinctrl_can2: can2grp { 229 fsl,pins = < 230 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 231 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 232 /* SR */ 233 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 234 >; 235 }; 236 237 pinctrl_ecspi1: ecspi1grp { 238 fsl,pins = < 239 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0 240 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1 241 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0 242 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0 243 >; 244 }; 245 246 pinctrl_ecspi2: ecspi2grp { 247 fsl,pins = < 248 MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0 249 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1 250 MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0 251 MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0 252 >; 253 }; 254 255 pinctrl_eth1: eth1grp { 256 fsl,pins = < 257 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 258 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0 259 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 260 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 261 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 262 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 263 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 264 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 265 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 266 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000 267 /* PHY ENET1_RST */ 268 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 269 /* PHY ENET1_IRQ */ 270 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880 271 >; 272 }; 273 274 pinctrl_hog: hoggrp { 275 fsl,pins = < 276 /* HW revision detect */ 277 /* REV_ID0 */ 278 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 279 /* REV_ID1 */ 280 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 281 /* REV_ID2 */ 282 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 283 /* REV_ID3 */ 284 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 285 /* BOARD_ID0 */ 286 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 287 /* BOARD_ID1 */ 288 MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 289 /* BOARD_ID2 */ 290 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 291 /* BOARD_ID3 */ 292 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 293 /* Safety controller IO */ 294 /* WAKE_SC */ 295 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 296 /* PROGRAM_SC */ 297 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 298 >; 299 }; 300 301 pinctrl_i2c1: i2c1grp { 302 fsl,pins = < 303 MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 304 MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 305 >; 306 }; 307 308 pinctrl_i2c2: i2c2grp { 309 fsl,pins = < 310 MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 311 MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 312 >; 313 }; 314 315 pinctrl_leds: ledsgrp { 316 fsl,pins = < 317 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 318 >; 319 }; 320 321 pinctrl_uart1: uart1grp { 322 fsl,pins = < 323 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 324 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 325 >; 326 }; 327 328 pinctrl_usdhc1: usdhc1grp { 329 fsl,pins = < 330 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 331 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 332 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 333 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 334 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 335 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 336 /* SD1 CD */ 337 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 338 >; 339 }; 340 341 pinctrl_usdhc2: usdhc2grp { 342 fsl,pins = < 343 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 344 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 345 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 346 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 347 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 348 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 349 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 350 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 351 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 352 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 353 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 354 >; 355 }; 356}; 357