1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 * Copyright 2018 NXP
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This file is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of
13 *     the License, or (at your option) any later version.
14 *
15 *     This file is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 *     You should have received a copy of the GNU General Public
21 *     License along with this file; if not, write to the Free
22 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 *     MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use,
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include "ls1021a.dtsi"
51
52/ {
53	model = "LS1021A QDS Board";
54	compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
55
56	aliases {
57		enet0_rgmii_phy = &rgmii_phy1;
58		enet1_rgmii_phy = &rgmii_phy2;
59		enet2_rgmii_phy = &rgmii_phy3;
60		enet0_sgmii_phy = &sgmii_phy1c;
61		enet1_sgmii_phy = &sgmii_phy1d;
62	};
63
64	sys_mclk: clock-mclk {
65		compatible = "fixed-clock";
66		#clock-cells = <0>;
67		clock-frequency = <24576000>;
68	};
69
70	regulators {
71		compatible = "simple-bus";
72		#address-cells = <1>;
73		#size-cells = <0>;
74
75		reg_3p3v: regulator@0 {
76			compatible = "regulator-fixed";
77			reg = <0>;
78			regulator-name = "3P3V";
79			regulator-min-microvolt = <3300000>;
80			regulator-max-microvolt = <3300000>;
81			regulator-always-on;
82		};
83	};
84
85	sound {
86		compatible = "simple-audio-card";
87		simple-audio-card,format = "i2s";
88		simple-audio-card,widgets =
89			"Microphone", "Microphone Jack",
90			"Headphone", "Headphone Jack",
91			"Speaker", "Speaker Ext",
92			"Line", "Line In Jack";
93		simple-audio-card,routing =
94			"MIC_IN", "Microphone Jack",
95			"Microphone Jack", "Mic Bias",
96			"LINE_IN", "Line In Jack",
97			"Headphone Jack", "HP_OUT",
98			"Speaker Ext", "LINE_OUT";
99
100		simple-audio-card,cpu {
101			sound-dai = <&sai2>;
102			frame-master;
103			bitclock-master;
104		};
105
106		simple-audio-card,codec {
107			sound-dai = <&codec>;
108			frame-master;
109			bitclock-master;
110		};
111	};
112};
113
114&dspi0 {
115	bus-num = <0>;
116	status = "okay";
117
118	dspiflash: at45db021d@0 {
119		#address-cells = <1>;
120		#size-cells = <1>;
121		compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
122		spi-max-frequency = <16000000>;
123		spi-cpol;
124		spi-cpha;
125		reg = <0>;
126	};
127};
128
129&enet0 {
130	tbi-handle = <&tbi0>;
131	phy-handle = <&sgmii_phy1c>;
132	phy-connection-type = "sgmii";
133	status = "okay";
134};
135
136&enet1 {
137	tbi-handle = <&tbi0>;
138	phy-handle = <&sgmii_phy1d>;
139	phy-connection-type = "sgmii";
140	status = "okay";
141};
142
143&enet2 {
144	phy-handle = <&rgmii_phy3>;
145	phy-connection-type = "rgmii-id";
146	status = "okay";
147};
148
149&esdhc {
150	status = "okay";
151};
152
153&i2c0 {
154	status = "okay";
155
156	pca9547: mux@77 {
157		compatible = "nxp,pca9547";
158		reg = <0x77>;
159		#address-cells = <1>;
160		#size-cells = <0>;
161
162		i2c@0 {
163			#address-cells = <1>;
164			#size-cells = <0>;
165			reg = <0x0>;
166
167			ds3232: rtc@68 {
168				compatible = "dallas,ds3232";
169				reg = <0x68>;
170				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
171			};
172		};
173
174		i2c@2 {
175			#address-cells = <1>;
176			#size-cells = <0>;
177			reg = <0x2>;
178
179			ina220@40 {
180				compatible = "ti,ina220";
181				reg = <0x40>;
182				shunt-resistor = <1000>;
183			};
184
185			ina220@41 {
186				compatible = "ti,ina220";
187				reg = <0x41>;
188				shunt-resistor = <1000>;
189			};
190		};
191
192		i2c@3 {
193			#address-cells = <1>;
194			#size-cells = <0>;
195			reg = <0x3>;
196
197			eeprom@56 {
198				compatible = "atmel,24c512";
199				reg = <0x56>;
200			};
201
202			eeprom@57 {
203				compatible = "atmel,24c512";
204				reg = <0x57>;
205			};
206
207			adt7461a@4c {
208				compatible = "adi,adt7461a";
209				reg = <0x4c>;
210			};
211		};
212
213		i2c@4 {
214			#address-cells = <1>;
215			#size-cells = <0>;
216			reg = <0x4>;
217
218			codec: sgtl5000@2a {
219				#sound-dai-cells = <0>;
220				compatible = "fsl,sgtl5000";
221				reg = <0x2a>;
222				VDDA-supply = <&reg_3p3v>;
223				VDDIO-supply = <&reg_3p3v>;
224				clocks = <&sys_mclk>;
225			};
226		};
227	};
228};
229
230&ifc {
231	#address-cells = <2>;
232	#size-cells = <1>;
233	/* NOR, NAND Flashes and FPGA on board */
234	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
235		  0x2 0x0 0x0 0x7e800000 0x00010000
236		  0x3 0x0 0x0 0x7fb00000 0x00000100>;
237	status = "okay";
238
239	nor@0,0 {
240		#address-cells = <1>;
241		#size-cells = <1>;
242		compatible = "cfi-flash";
243		reg = <0x0 0x0 0x8000000>;
244		big-endian;
245		bank-width = <2>;
246		device-width = <1>;
247	};
248
249	nand@2,0 {
250		compatible = "fsl,ifc-nand";
251		reg = <0x2 0x0 0x10000>;
252	};
253
254	fpga: board-control@3,0 {
255		#address-cells = <1>;
256		#size-cells = <1>;
257		compatible = "simple-bus";
258		reg = <0x3 0x0 0x0000100>;
259		bank-width = <1>;
260		device-width = <1>;
261		ranges = <0 3 0 0x100>;
262
263		mdio-mux-emi1 {
264			compatible = "mdio-mux-mmioreg";
265			mdio-parent-bus = <&mdio0>;
266			#address-cells = <1>;
267			#size-cells = <0>;
268			reg = <0x54 1>; /* BRDCFG4 */
269			mux-mask = <0xe0>; /* EMI1[2:0] */
270
271			/* Onboard PHYs */
272			ls1021amdio0: mdio@0 {
273				reg = <0>;
274				#address-cells = <1>;
275				#size-cells = <0>;
276				rgmii_phy1: ethernet-phy@1 {
277					reg = <0x1>;
278				};
279			};
280
281			ls1021amdio1: mdio@20 {
282				reg = <0x20>;
283				#address-cells = <1>;
284				#size-cells = <0>;
285				rgmii_phy2: ethernet-phy@2 {
286					reg = <0x2>;
287				};
288			};
289
290			ls1021amdio2: mdio@40 {
291				reg = <0x40>;
292				#address-cells = <1>;
293				#size-cells = <0>;
294				rgmii_phy3: ethernet-phy@3 {
295					reg = <0x3>;
296				};
297			};
298
299			ls1021amdio3: mdio@60 {
300				reg = <0x60>;
301				#address-cells = <1>;
302				#size-cells = <0>;
303				sgmii_phy1c: ethernet-phy@1c {
304					reg = <0x1c>;
305				};
306			};
307
308			ls1021amdio4: mdio@80 {
309				reg = <0x80>;
310				#address-cells = <1>;
311				#size-cells = <0>;
312				sgmii_phy1d: ethernet-phy@1d {
313					reg = <0x1d>;
314				};
315			};
316		};
317	};
318};
319
320&lpuart0 {
321	status = "okay";
322};
323
324&mdio0 {
325	tbi0: tbi-phy@8 {
326		reg = <0x8>;
327		device_type = "tbi-phy";
328	};
329};
330
331&sai2 {
332	status = "okay";
333};
334
335&sata {
336	status = "okay";
337};
338
339&uart0 {
340	status = "okay";
341};
342
343&uart1 {
344	status = "okay";
345};
346
347&can0 {
348	status = "okay";
349};
350
351&can1 {
352	status = "okay";
353};
354
355&can2 {
356	status = "disabled";
357};
358
359&can3 {
360	status = "disabled";
361};
362