1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2014 Carlo Caione <carlo@caione.org> 4 */ 5 6#include <dt-bindings/clock/meson8-ddr-clkc.h> 7#include <dt-bindings/clock/meson8b-clkc.h> 8#include <dt-bindings/gpio/meson8-gpio.h> 9#include <dt-bindings/power/meson8-power.h> 10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 11#include <dt-bindings/reset/amlogic,meson8b-reset.h> 12#include <dt-bindings/thermal/thermal.h> 13#include "meson.dtsi" 14 15/ { 16 model = "Amlogic Meson8 SoC"; 17 compatible = "amlogic,meson8"; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@200 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a9"; 26 next-level-cache = <&L2>; 27 reg = <0x200>; 28 enable-method = "amlogic,meson8-smp"; 29 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 30 operating-points-v2 = <&cpu_opp_table>; 31 clocks = <&clkc CLKID_CPUCLK>; 32 #cooling-cells = <2>; /* min followed by max */ 33 }; 34 35 cpu1: cpu@201 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a9"; 38 next-level-cache = <&L2>; 39 reg = <0x201>; 40 enable-method = "amlogic,meson8-smp"; 41 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 42 operating-points-v2 = <&cpu_opp_table>; 43 clocks = <&clkc CLKID_CPUCLK>; 44 #cooling-cells = <2>; /* min followed by max */ 45 }; 46 47 cpu2: cpu@202 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 next-level-cache = <&L2>; 51 reg = <0x202>; 52 enable-method = "amlogic,meson8-smp"; 53 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 54 operating-points-v2 = <&cpu_opp_table>; 55 clocks = <&clkc CLKID_CPUCLK>; 56 #cooling-cells = <2>; /* min followed by max */ 57 }; 58 59 cpu3: cpu@203 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a9"; 62 next-level-cache = <&L2>; 63 reg = <0x203>; 64 enable-method = "amlogic,meson8-smp"; 65 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 66 operating-points-v2 = <&cpu_opp_table>; 67 clocks = <&clkc CLKID_CPUCLK>; 68 #cooling-cells = <2>; /* min followed by max */ 69 }; 70 }; 71 72 cpu_opp_table: opp-table { 73 compatible = "operating-points-v2"; 74 opp-shared; 75 76 opp-96000000 { 77 opp-hz = /bits/ 64 <96000000>; 78 opp-microvolt = <825000>; 79 }; 80 opp-192000000 { 81 opp-hz = /bits/ 64 <192000000>; 82 opp-microvolt = <825000>; 83 }; 84 opp-312000000 { 85 opp-hz = /bits/ 64 <312000000>; 86 opp-microvolt = <825000>; 87 }; 88 opp-408000000 { 89 opp-hz = /bits/ 64 <408000000>; 90 opp-microvolt = <825000>; 91 }; 92 opp-504000000 { 93 opp-hz = /bits/ 64 <504000000>; 94 opp-microvolt = <825000>; 95 }; 96 opp-600000000 { 97 opp-hz = /bits/ 64 <600000000>; 98 opp-microvolt = <850000>; 99 }; 100 opp-720000000 { 101 opp-hz = /bits/ 64 <720000000>; 102 opp-microvolt = <850000>; 103 }; 104 opp-816000000 { 105 opp-hz = /bits/ 64 <816000000>; 106 opp-microvolt = <875000>; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <925000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <975000>; 115 }; 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <1025000>; 119 }; 120 opp-1608000000 { 121 opp-hz = /bits/ 64 <1608000000>; 122 opp-microvolt = <1100000>; 123 }; 124 opp-1800000000 { 125 status = "disabled"; 126 opp-hz = /bits/ 64 <1800000000>; 127 opp-microvolt = <1125000>; 128 }; 129 opp-1992000000 { 130 status = "disabled"; 131 opp-hz = /bits/ 64 <1992000000>; 132 opp-microvolt = <1150000>; 133 }; 134 }; 135 136 gpu_opp_table: gpu-opp-table { 137 compatible = "operating-points-v2"; 138 139 opp-182142857 { 140 opp-hz = /bits/ 64 <182142857>; 141 opp-microvolt = <1150000>; 142 }; 143 opp-318750000 { 144 opp-hz = /bits/ 64 <318750000>; 145 opp-microvolt = <1150000>; 146 }; 147 opp-425000000 { 148 opp-hz = /bits/ 64 <425000000>; 149 opp-microvolt = <1150000>; 150 }; 151 opp-510000000 { 152 opp-hz = /bits/ 64 <510000000>; 153 opp-microvolt = <1150000>; 154 }; 155 opp-637500000 { 156 opp-hz = /bits/ 64 <637500000>; 157 opp-microvolt = <1150000>; 158 turbo-mode; 159 }; 160 }; 161 162 pmu { 163 compatible = "arm,cortex-a9-pmu"; 164 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 169 }; 170 171 reserved-memory { 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges; 175 176 /* 2 MiB reserved for Hardware ROM Firmware? */ 177 hwrom@0 { 178 reg = <0x0 0x200000>; 179 no-map; 180 }; 181 182 /* 183 * 1 MiB reserved for the "ARM Power Firmware": this is ARM 184 * code which is responsible for system suspend. It loads a 185 * piece of ARC code ("arc_power" in the vendor u-boot tree) 186 * into SRAM, executes that and shuts down the (last) ARM core. 187 * The arc_power firmware then checks various wakeup sources 188 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or 189 * simply the power key) and re-starts the ARM core once it 190 * detects a wakeup request. 191 */ 192 power-firmware@4f00000 { 193 reg = <0x4f00000 0x100000>; 194 no-map; 195 }; 196 }; 197 198 thermal-zones { 199 soc { 200 polling-delay-passive = <250>; /* milliseconds */ 201 polling-delay = <1000>; /* milliseconds */ 202 thermal-sensors = <&thermal_sensor>; 203 204 cooling-maps { 205 map0 { 206 trip = <&soc_passive>; 207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 214 map1 { 215 trip = <&soc_hot>; 216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 217 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 218 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 219 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 220 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 221 }; 222 }; 223 224 trips { 225 soc_passive: soc-passive { 226 temperature = <80000>; /* millicelsius */ 227 hysteresis = <2000>; /* millicelsius */ 228 type = "passive"; 229 }; 230 231 soc_hot: soc-hot { 232 temperature = <90000>; /* millicelsius */ 233 hysteresis = <2000>; /* millicelsius */ 234 type = "hot"; 235 }; 236 237 soc_critical: soc-critical { 238 temperature = <110000>; /* millicelsius */ 239 hysteresis = <2000>; /* millicelsius */ 240 type = "critical"; 241 }; 242 }; 243 }; 244 }; 245 246 mmcbus: bus@c8000000 { 247 compatible = "simple-bus"; 248 reg = <0xc8000000 0x8000>; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 ranges = <0x0 0xc8000000 0x8000>; 252 253 ddr_clkc: clock-controller@400 { 254 compatible = "amlogic,meson8-ddr-clkc"; 255 reg = <0x400 0x20>; 256 clocks = <&xtal>; 257 clock-names = "xtal"; 258 #clock-cells = <1>; 259 }; 260 261 dmcbus: bus@6000 { 262 compatible = "simple-bus"; 263 reg = <0x6000 0x400>; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges = <0x0 0x6000 0x400>; 267 268 canvas: video-lut@20 { 269 compatible = "amlogic,meson8-canvas", 270 "amlogic,canvas"; 271 reg = <0x20 0x14>; 272 }; 273 }; 274 }; 275 276 apb: bus@d0000000 { 277 compatible = "simple-bus"; 278 reg = <0xd0000000 0x200000>; 279 #address-cells = <1>; 280 #size-cells = <1>; 281 ranges = <0x0 0xd0000000 0x200000>; 282 283 mali: gpu@c0000 { 284 compatible = "amlogic,meson8-mali", "arm,mali-450"; 285 reg = <0xc0000 0x40000>; 286 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-names = "gp", "gpmmu", "pp", "pmu", 303 "pp0", "ppmmu0", "pp1", "ppmmu1", 304 "pp2", "ppmmu2", "pp4", "ppmmu4", 305 "pp5", "ppmmu5", "pp6", "ppmmu6"; 306 resets = <&reset RESET_MALI>; 307 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 308 clock-names = "bus", "core"; 309 operating-points-v2 = <&gpu_opp_table>; 310 #cooling-cells = <2>; /* min followed by max */ 311 }; 312 }; 313}; /* end of / */ 314 315&aobus { 316 pmu: pmu@e0 { 317 compatible = "amlogic,meson8-pmu", "syscon"; 318 reg = <0xe0 0x18>; 319 }; 320 321 pinctrl_aobus: pinctrl@84 { 322 compatible = "amlogic,meson8-aobus-pinctrl"; 323 reg = <0x84 0xc>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges; 327 328 gpio_ao: ao-bank@14 { 329 reg = <0x14 0x4>, 330 <0x2c 0x4>, 331 <0x24 0x8>; 332 reg-names = "mux", "pull", "gpio"; 333 gpio-controller; 334 #gpio-cells = <2>; 335 gpio-ranges = <&pinctrl_aobus 0 0 16>; 336 }; 337 338 uart_ao_a_pins: uart_ao_a { 339 mux { 340 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 341 function = "uart_ao"; 342 bias-disable; 343 }; 344 }; 345 346 i2c_ao_pins: i2c_mst_ao { 347 mux { 348 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; 349 function = "i2c_mst_ao"; 350 bias-disable; 351 }; 352 }; 353 354 ir_recv_pins: remote { 355 mux { 356 groups = "remote_input"; 357 function = "remote"; 358 bias-disable; 359 }; 360 }; 361 362 pwm_f_ao_pins: pwm-f-ao { 363 mux { 364 groups = "pwm_f_ao"; 365 function = "pwm_f_ao"; 366 bias-disable; 367 }; 368 }; 369 }; 370}; 371 372&ao_arc_rproc { 373 compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; 374 amlogic,secbus2 = <&secbus2>; 375 sram = <&ao_arc_sram>; 376 resets = <&reset RESET_MEDIA_CPU>; 377 clocks = <&clkc CLKID_AO_MEDIA_CPU>; 378}; 379 380&cbus { 381 reset: reset-controller@4404 { 382 compatible = "amlogic,meson8b-reset"; 383 reg = <0x4404 0x9c>; 384 #reset-cells = <1>; 385 }; 386 387 analog_top: analog-top@81a8 { 388 compatible = "amlogic,meson8-analog-top", "syscon"; 389 reg = <0x81a8 0x14>; 390 }; 391 392 pwm_ef: pwm@86c0 { 393 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 394 reg = <0x86c0 0x10>; 395 #pwm-cells = <3>; 396 status = "disabled"; 397 }; 398 399 clock-measure@8758 { 400 compatible = "amlogic,meson8-clk-measure"; 401 reg = <0x8758 0x1c>; 402 }; 403 404 pinctrl_cbus: pinctrl@9880 { 405 compatible = "amlogic,meson8-cbus-pinctrl"; 406 reg = <0x9880 0x10>; 407 #address-cells = <1>; 408 #size-cells = <1>; 409 ranges; 410 411 gpio: banks@80b0 { 412 reg = <0x80b0 0x28>, 413 <0x80e8 0x18>, 414 <0x8120 0x18>, 415 <0x8030 0x30>; 416 reg-names = "mux", "pull", "pull-enable", "gpio"; 417 gpio-controller; 418 #gpio-cells = <2>; 419 gpio-ranges = <&pinctrl_cbus 0 0 120>; 420 }; 421 422 sd_a_pins: sd-a { 423 mux { 424 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", 425 "sd_d3_a", "sd_clk_a", "sd_cmd_a"; 426 function = "sd_a"; 427 bias-disable; 428 }; 429 }; 430 431 sd_b_pins: sd-b { 432 mux { 433 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 434 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 435 function = "sd_b"; 436 bias-disable; 437 }; 438 }; 439 440 sd_c_pins: sd-c { 441 mux { 442 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", 443 "sd_d3_c", "sd_clk_c", "sd_cmd_c"; 444 function = "sd_c"; 445 bias-disable; 446 }; 447 }; 448 449 sdxc_b_pins: sdxc-b { 450 mux { 451 groups = "sdxc_d0_b", "sdxc_d13_b", 452 "sdxc_clk_b", "sdxc_cmd_b"; 453 function = "sdxc_b"; 454 bias-pull-up; 455 }; 456 }; 457 458 spi_nor_pins: nor { 459 mux { 460 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 461 function = "nor"; 462 bias-disable; 463 }; 464 }; 465 466 eth_pins: ethernet { 467 mux { 468 groups = "eth_tx_clk_50m", "eth_tx_en", 469 "eth_txd1", "eth_txd0", 470 "eth_rx_clk_in", "eth_rx_dv", 471 "eth_rxd1", "eth_rxd0", "eth_mdio", 472 "eth_mdc"; 473 function = "ethernet"; 474 bias-disable; 475 }; 476 }; 477 478 pwm_e_pins: pwm-e { 479 mux { 480 groups = "pwm_e"; 481 function = "pwm_e"; 482 bias-disable; 483 }; 484 }; 485 486 uart_a1_pins: uart-a1 { 487 mux { 488 groups = "uart_tx_a1", 489 "uart_rx_a1"; 490 function = "uart_a"; 491 bias-disable; 492 }; 493 }; 494 495 uart_a1_cts_rts_pins: uart-a1-cts-rts { 496 mux { 497 groups = "uart_cts_a1", 498 "uart_rts_a1"; 499 function = "uart_a"; 500 bias-disable; 501 }; 502 }; 503 }; 504}; 505 506&ahb_sram { 507 ao_arc_sram: ao-arc-sram@0 { 508 compatible = "amlogic,meson8-ao-arc-sram"; 509 reg = <0x0 0x8000>; 510 pool; 511 }; 512 513 smp-sram@1ff80 { 514 compatible = "amlogic,meson8-smp-sram"; 515 reg = <0x1ff80 0x8>; 516 }; 517}; 518 519&efuse { 520 compatible = "amlogic,meson8-efuse"; 521 clocks = <&clkc CLKID_EFUSE>; 522 clock-names = "core"; 523 524 temperature_calib: calib@1f4 { 525 /* only the upper two bytes are relevant */ 526 reg = <0x1f4 0x4>; 527 }; 528}; 529 530ðmac { 531 clocks = <&clkc CLKID_ETH>; 532 clock-names = "stmmaceth"; 533 534 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; 535}; 536 537&gpio_intc { 538 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; 539 status = "okay"; 540}; 541 542&hhi { 543 clkc: clock-controller { 544 compatible = "amlogic,meson8-clkc"; 545 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; 546 clock-names = "xtal", "ddr_pll"; 547 #clock-cells = <1>; 548 #reset-cells = <1>; 549 }; 550 551 pwrc: power-controller { 552 compatible = "amlogic,meson8-pwrc"; 553 #power-domain-cells = <1>; 554 amlogic,ao-sysctrl = <&pmu>; 555 clocks = <&clkc CLKID_VPU>; 556 clock-names = "vpu"; 557 assigned-clocks = <&clkc CLKID_VPU>; 558 assigned-clock-rates = <364285714>; 559 }; 560}; 561 562&hwrng { 563 compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; 564 clocks = <&clkc CLKID_RNG0>; 565 clock-names = "core"; 566}; 567 568&i2c_AO { 569 clocks = <&clkc CLKID_CLK81>; 570}; 571 572&i2c_A { 573 clocks = <&clkc CLKID_CLK81>; 574}; 575 576&i2c_B { 577 clocks = <&clkc CLKID_CLK81>; 578}; 579 580&L2 { 581 arm,data-latency = <3 3 3>; 582 arm,tag-latency = <2 2 2>; 583 arm,filter-ranges = <0x100000 0xc0000000>; 584 prefetch-data = <1>; 585 prefetch-instr = <1>; 586 arm,shared-override; 587}; 588 589&periph { 590 scu@0 { 591 compatible = "arm,cortex-a9-scu"; 592 reg = <0x0 0x100>; 593 }; 594 595 timer@200 { 596 compatible = "arm,cortex-a9-global-timer"; 597 reg = <0x200 0x20>; 598 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 599 clocks = <&clkc CLKID_PERIPH>; 600 601 /* 602 * the arm_global_timer driver currently does not handle clock 603 * rate changes. Keep it disabled for now. 604 */ 605 status = "disabled"; 606 }; 607 608 timer@600 { 609 compatible = "arm,cortex-a9-twd-timer"; 610 reg = <0x600 0x20>; 611 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 612 clocks = <&clkc CLKID_PERIPH>; 613 }; 614}; 615 616&pwm_ab { 617 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 618}; 619 620&pwm_cd { 621 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 622}; 623 624&rtc { 625 compatible = "amlogic,meson8-rtc"; 626 resets = <&reset RESET_RTC>; 627}; 628 629&saradc { 630 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; 631 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; 632 clock-names = "clkin", "core"; 633 amlogic,hhi-sysctrl = <&hhi>; 634 nvmem-cells = <&temperature_calib>; 635 nvmem-cell-names = "temperature_calib"; 636}; 637 638&sdhc { 639 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 640 clocks = <&xtal>, 641 <&clkc CLKID_FCLK_DIV4>, 642 <&clkc CLKID_FCLK_DIV3>, 643 <&clkc CLKID_FCLK_DIV5>, 644 <&clkc CLKID_SDHC>; 645 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 646}; 647 648&secbus { 649 secbus2: system-controller@4000 { 650 compatible = "amlogic,meson8-secbus2", "syscon"; 651 reg = <0x4000 0x2000>; 652 }; 653}; 654 655&sdio { 656 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; 657 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 658 clock-names = "core", "clkin"; 659}; 660 661&spifc { 662 clocks = <&clkc CLKID_CLK81>; 663}; 664 665&timer_abcde { 666 clocks = <&xtal>, <&clkc CLKID_CLK81>; 667 clock-names = "xtal", "pclk"; 668}; 669 670&uart_AO { 671 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 672 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; 673 clock-names = "baud", "xtal", "pclk"; 674}; 675 676&uart_A { 677 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 678 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; 679 clock-names = "baud", "xtal", "pclk"; 680}; 681 682&uart_B { 683 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 684 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; 685 clock-names = "baud", "xtal", "pclk"; 686}; 687 688&uart_C { 689 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 690 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; 691 clock-names = "baud", "xtal", "pclk"; 692}; 693 694&usb0 { 695 compatible = "amlogic,meson8-usb", "snps,dwc2"; 696 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 697 clock-names = "otg"; 698}; 699 700&usb1 { 701 compatible = "amlogic,meson8-usb", "snps,dwc2"; 702 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 703 clock-names = "otg"; 704}; 705 706&usb0_phy { 707 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 708 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 709 clock-names = "usb_general", "usb"; 710 resets = <&reset RESET_USB_OTG>; 711}; 712 713&usb1_phy { 714 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 715 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 716 clock-names = "usb_general", "usb"; 717 resets = <&reset RESET_USB_OTG>; 718}; 719