1/* 2 * Device Tree Source for OMAP2 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/omap.h> 15 16/ { 17 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; 18 interrupt-parent = <&intc>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 serial0 = &uart1; 25 serial1 = &uart2; 26 serial2 = &uart3; 27 i2c0 = &i2c1; 28 i2c1 = &i2c2; 29 }; 30 31 cpus { 32 #address-cells = <0>; 33 #size-cells = <0>; 34 35 cpu { 36 compatible = "arm,arm1136jf-s"; 37 device_type = "cpu"; 38 }; 39 }; 40 41 pmu { 42 compatible = "arm,arm1136-pmu"; 43 interrupts = <3>; 44 }; 45 46 soc { 47 compatible = "ti,omap-infra"; 48 mpu { 49 compatible = "ti,omap2-mpu"; 50 ti,hwmods = "mpu"; 51 }; 52 }; 53 54 ocp { 55 compatible = "simple-bus"; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges; 59 ti,hwmods = "l3_main"; 60 61 aes: aes@480a6000 { 62 compatible = "ti,omap2-aes"; 63 ti,hwmods = "aes"; 64 reg = <0x480a6000 0x50>; 65 dmas = <&sdma 9 &sdma 10>; 66 dma-names = "tx", "rx"; 67 }; 68 69 hdq1w: 1w@480b2000 { 70 compatible = "ti,omap2420-1w"; 71 ti,hwmods = "hdq1w"; 72 reg = <0x480b2000 0x1000>; 73 interrupts = <58>; 74 }; 75 76 intc: interrupt-controller@1 { 77 compatible = "ti,omap2-intc"; 78 interrupt-controller; 79 #interrupt-cells = <1>; 80 reg = <0x480FE000 0x1000>; 81 }; 82 83 target-module@48056000 { 84 compatible = "ti,sysc-omap2", "ti,sysc"; 85 reg = <0x48056000 0x4>, 86 <0x4805602c 0x4>, 87 <0x48056028 0x4>; 88 reg-names = "rev", "sysc", "syss"; 89 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 90 SYSC_OMAP2_EMUFREE | 91 SYSC_OMAP2_SOFTRESET | 92 SYSC_OMAP2_AUTOIDLE)>; 93 ti,sysc-midle = <SYSC_IDLE_FORCE>, 94 <SYSC_IDLE_NO>, 95 <SYSC_IDLE_SMART>; 96 ti,syss-mask = <1>; 97 clocks = <&core_l3_ck>; 98 clock-names = "fck"; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x48056000 0x1000>; 102 103 sdma: dma-controller@0 { 104 compatible = "ti,omap2420-sdma", "ti,omap-sdma"; 105 reg = <0 0x1000>; 106 interrupts = <12>, 107 <13>, 108 <14>, 109 <15>; 110 #dma-cells = <1>; 111 dma-channels = <32>; 112 dma-requests = <64>; 113 }; 114 }; 115 116 i2c1: i2c@48070000 { 117 compatible = "ti,omap2-i2c"; 118 ti,hwmods = "i2c1"; 119 reg = <0x48070000 0x80>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 interrupts = <56>; 123 dmas = <&sdma 27 &sdma 28>; 124 dma-names = "tx", "rx"; 125 }; 126 127 i2c2: i2c@48072000 { 128 compatible = "ti,omap2-i2c"; 129 ti,hwmods = "i2c2"; 130 reg = <0x48072000 0x80>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 interrupts = <57>; 134 dmas = <&sdma 29 &sdma 30>; 135 dma-names = "tx", "rx"; 136 }; 137 138 mcspi1: spi@48098000 { 139 compatible = "ti,omap2-mcspi"; 140 ti,hwmods = "mcspi1"; 141 reg = <0x48098000 0x100>; 142 interrupts = <65>; 143 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 144 &sdma 39 &sdma 40 &sdma 41 &sdma 42>; 145 dma-names = "tx0", "rx0", "tx1", "rx1", 146 "tx2", "rx2", "tx3", "rx3"; 147 }; 148 149 mcspi2: spi@4809a000 { 150 compatible = "ti,omap2-mcspi"; 151 ti,hwmods = "mcspi2"; 152 reg = <0x4809a000 0x100>; 153 interrupts = <66>; 154 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; 155 dma-names = "tx0", "rx0", "tx1", "rx1"; 156 }; 157 158 rng: rng@480a0000 { 159 compatible = "ti,omap2-rng"; 160 ti,hwmods = "rng"; 161 reg = <0x480a0000 0x50>; 162 interrupts = <52>; 163 }; 164 165 sham: sham@480a4000 { 166 compatible = "ti,omap2-sham"; 167 ti,hwmods = "sham"; 168 reg = <0x480a4000 0x64>; 169 interrupts = <51>; 170 dmas = <&sdma 13>; 171 dma-names = "rx"; 172 }; 173 174 uart1: serial@4806a000 { 175 compatible = "ti,omap2-uart"; 176 ti,hwmods = "uart1"; 177 reg = <0x4806a000 0x2000>; 178 interrupts = <72>; 179 dmas = <&sdma 49 &sdma 50>; 180 dma-names = "tx", "rx"; 181 clock-frequency = <48000000>; 182 }; 183 184 uart2: serial@4806c000 { 185 compatible = "ti,omap2-uart"; 186 ti,hwmods = "uart2"; 187 reg = <0x4806c000 0x400>; 188 interrupts = <73>; 189 dmas = <&sdma 51 &sdma 52>; 190 dma-names = "tx", "rx"; 191 clock-frequency = <48000000>; 192 }; 193 194 uart3: serial@4806e000 { 195 compatible = "ti,omap2-uart"; 196 ti,hwmods = "uart3"; 197 reg = <0x4806e000 0x400>; 198 interrupts = <74>; 199 dmas = <&sdma 53 &sdma 54>; 200 dma-names = "tx", "rx"; 201 clock-frequency = <48000000>; 202 }; 203 204 timer2_target: target-module@4802a000 { 205 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 206 reg = <0x4802a000 0x4>, 207 <0x4802a010 0x4>, 208 <0x4802a014 0x4>; 209 reg-names = "rev", "sysc", "syss"; 210 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 211 SYSC_OMAP2_EMUFREE | 212 SYSC_OMAP2_ENAWAKEUP | 213 SYSC_OMAP2_SOFTRESET | 214 SYSC_OMAP2_AUTOIDLE)>; 215 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 216 <SYSC_IDLE_NO>, 217 <SYSC_IDLE_SMART>; 218 ti,syss-mask = <1>; 219 clocks = <&gpt2_fck>, <&gpt2_ick>; 220 clock-names = "fck", "ick"; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 ranges = <0x0 0x4802a000 0x1000>; 224 225 timer2: timer@0 { 226 compatible = "ti,omap2420-timer"; 227 reg = <0 0x400>; 228 interrupts = <38>; 229 }; 230 }; 231 232 timer3: timer@48078000 { 233 compatible = "ti,omap2420-timer"; 234 reg = <0x48078000 0x400>; 235 interrupts = <39>; 236 ti,hwmods = "timer3"; 237 }; 238 239 timer4: timer@4807a000 { 240 compatible = "ti,omap2420-timer"; 241 reg = <0x4807a000 0x400>; 242 interrupts = <40>; 243 ti,hwmods = "timer4"; 244 }; 245 246 timer5: timer@4807c000 { 247 compatible = "ti,omap2420-timer"; 248 reg = <0x4807c000 0x400>; 249 interrupts = <41>; 250 ti,hwmods = "timer5"; 251 ti,timer-dsp; 252 }; 253 254 timer6: timer@4807e000 { 255 compatible = "ti,omap2420-timer"; 256 reg = <0x4807e000 0x400>; 257 interrupts = <42>; 258 ti,hwmods = "timer6"; 259 ti,timer-dsp; 260 }; 261 262 timer7: timer@48080000 { 263 compatible = "ti,omap2420-timer"; 264 reg = <0x48080000 0x400>; 265 interrupts = <43>; 266 ti,hwmods = "timer7"; 267 ti,timer-dsp; 268 }; 269 270 timer8: timer@48082000 { 271 compatible = "ti,omap2420-timer"; 272 reg = <0x48082000 0x400>; 273 interrupts = <44>; 274 ti,hwmods = "timer8"; 275 ti,timer-dsp; 276 }; 277 278 timer9: timer@48084000 { 279 compatible = "ti,omap2420-timer"; 280 reg = <0x48084000 0x400>; 281 interrupts = <45>; 282 ti,hwmods = "timer9"; 283 ti,timer-pwm; 284 }; 285 286 timer10: timer@48086000 { 287 compatible = "ti,omap2420-timer"; 288 reg = <0x48086000 0x400>; 289 interrupts = <46>; 290 ti,hwmods = "timer10"; 291 ti,timer-pwm; 292 }; 293 294 timer11: timer@48088000 { 295 compatible = "ti,omap2420-timer"; 296 reg = <0x48088000 0x400>; 297 interrupts = <47>; 298 ti,hwmods = "timer11"; 299 ti,timer-pwm; 300 }; 301 302 timer12: timer@4808a000 { 303 compatible = "ti,omap2420-timer"; 304 reg = <0x4808a000 0x400>; 305 interrupts = <48>; 306 ti,hwmods = "timer12"; 307 ti,timer-pwm; 308 }; 309 310 dss: dss@48050000 { 311 compatible = "ti,omap2-dss"; 312 reg = <0x48050000 0x400>; 313 status = "disabled"; 314 ti,hwmods = "dss_core"; 315 #address-cells = <1>; 316 #size-cells = <1>; 317 ranges; 318 319 dispc@48050400 { 320 compatible = "ti,omap2-dispc"; 321 reg = <0x48050400 0x400>; 322 interrupts = <25>; 323 ti,hwmods = "dss_dispc"; 324 }; 325 326 rfbi: encoder@48050800 { 327 compatible = "ti,omap2-rfbi"; 328 reg = <0x48050800 0x400>; 329 status = "disabled"; 330 ti,hwmods = "dss_rfbi"; 331 }; 332 333 venc: encoder@48050c00 { 334 compatible = "ti,omap2-venc"; 335 reg = <0x48050c00 0x400>; 336 status = "disabled"; 337 ti,hwmods = "dss_venc"; 338 }; 339 }; 340 }; 341}; 342