1/* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/omap.h> 15 16/ { 17 compatible = "ti,omap3430", "ti,omap3"; 18 interrupt-parent = <&intc>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 mmc0 = &mmc1; 28 mmc1 = &mmc2; 29 mmc2 = &mmc3; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,cortex-a8"; 41 device_type = "cpu"; 42 reg = <0x0>; 43 44 clocks = <&dpll1_ck>; 45 clock-names = "cpu"; 46 47 clock-latency = <300000>; /* From omap-cpufreq driver */ 48 }; 49 }; 50 51 pmu@54000000 { 52 compatible = "arm,cortex-a8-pmu"; 53 reg = <0x54000000 0x800000>; 54 interrupts = <3>; 55 ti,hwmods = "debugss"; 56 }; 57 58 /* 59 * The soc node represents the soc top level view. It is used for IPs 60 * that are not memory mapped in the MPU view or for the MPU itself. 61 */ 62 soc { 63 compatible = "ti,omap-infra"; 64 mpu { 65 compatible = "ti,omap3-mpu"; 66 ti,hwmods = "mpu"; 67 }; 68 69 iva: iva { 70 compatible = "ti,iva2.2"; 71 ti,hwmods = "iva"; 72 73 dsp { 74 compatible = "ti,omap3-c64"; 75 }; 76 }; 77 }; 78 79 /* 80 * XXX: Use a flat representation of the OMAP3 interconnect. 81 * The real OMAP interconnect network is quite complex. 82 * Since it will not bring real advantage to represent that in DT for 83 * the moment, just use a fake OCP bus entry to represent the whole bus 84 * hierarchy. 85 */ 86 ocp@68000000 { 87 compatible = "ti,omap3-l3-smx", "simple-bus"; 88 reg = <0x68000000 0x10000>; 89 interrupts = <9 10>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 ti,hwmods = "l3_main"; 94 95 l4_core: l4@48000000 { 96 compatible = "ti,omap3-l4-core", "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0 0x48000000 0x1000000>; 100 101 scm: scm@2000 { 102 compatible = "ti,omap3-scm", "simple-bus"; 103 reg = <0x2000 0x2000>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0x2000 0x2000>; 107 108 omap3_pmx_core: pinmux@30 { 109 compatible = "ti,omap3-padconf", 110 "pinctrl-single"; 111 reg = <0x30 0x238>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 #pinctrl-cells = <1>; 115 #interrupt-cells = <1>; 116 interrupt-controller; 117 pinctrl-single,register-width = <16>; 118 pinctrl-single,function-mask = <0xff1f>; 119 }; 120 121 scm_conf: scm_conf@270 { 122 compatible = "syscon", "simple-bus"; 123 reg = <0x270 0x330>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0 0x270 0x330>; 127 128 pbias_regulator: pbias_regulator@2b0 { 129 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 130 reg = <0x2b0 0x4>; 131 syscon = <&scm_conf>; 132 pbias_mmc_reg: pbias_mmc_omap2430 { 133 regulator-name = "pbias_mmc_omap2430"; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <3000000>; 136 }; 137 }; 138 139 scm_clocks: clocks { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 }; 143 }; 144 145 scm_clockdomains: clockdomains { 146 }; 147 148 omap3_pmx_wkup: pinmux@a00 { 149 compatible = "ti,omap3-padconf", 150 "pinctrl-single"; 151 reg = <0xa00 0x5c>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 #pinctrl-cells = <1>; 155 #interrupt-cells = <1>; 156 interrupt-controller; 157 pinctrl-single,register-width = <16>; 158 pinctrl-single,function-mask = <0xff1f>; 159 }; 160 }; 161 }; 162 163 aes1_target: target-module@480a6000 { 164 compatible = "ti,sysc-omap2", "ti,sysc"; 165 reg = <0x480a6044 0x4>, 166 <0x480a6048 0x4>, 167 <0x480a604c 0x4>; 168 reg-names = "rev", "sysc", "syss"; 169 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 170 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 171 <SYSC_IDLE_NO>, 172 <SYSC_IDLE_SMART>; 173 ti,syss-mask = <1>; 174 clocks = <&aes1_ick>; 175 clock-names = "ick"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges = <0 0x480a6000 0x2000>; 179 180 aes1: aes1@0 { 181 compatible = "ti,omap3-aes"; 182 reg = <0 0x50>; 183 interrupts = <0>; 184 dmas = <&sdma 9 &sdma 10>; 185 dma-names = "tx", "rx"; 186 }; 187 }; 188 189 aes2_target: target-module@480c5000 { 190 compatible = "ti,sysc-omap2", "ti,sysc"; 191 reg = <0x480c5044 0x4>, 192 <0x480c5048 0x4>, 193 <0x480c504c 0x4>; 194 reg-names = "rev", "sysc", "syss"; 195 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 196 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 197 <SYSC_IDLE_NO>, 198 <SYSC_IDLE_SMART>; 199 ti,syss-mask = <1>; 200 clocks = <&aes2_ick>; 201 clock-names = "ick"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges = <0 0x480c5000 0x2000>; 205 206 aes2: aes2@0 { 207 compatible = "ti,omap3-aes"; 208 reg = <0 0x50>; 209 interrupts = <0>; 210 dmas = <&sdma 65 &sdma 66>; 211 dma-names = "tx", "rx"; 212 }; 213 }; 214 215 prm: prm@48306000 { 216 compatible = "ti,omap3-prm"; 217 reg = <0x48306000 0x4000>; 218 interrupts = <11>; 219 220 prm_clocks: clocks { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 }; 224 225 prm_clockdomains: clockdomains { 226 }; 227 }; 228 229 cm: cm@48004000 { 230 compatible = "ti,omap3-cm"; 231 reg = <0x48004000 0x4000>; 232 233 cm_clocks: clocks { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 }; 237 238 cm_clockdomains: clockdomains { 239 }; 240 }; 241 242 target-module@48320000 { 243 compatible = "ti,sysc-omap2", "ti,sysc"; 244 reg = <0x48320000 0x4>, 245 <0x48320004 0x4>; 246 reg-names = "rev", "sysc"; 247 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 248 <SYSC_IDLE_NO>; 249 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; 250 clock-names = "fck", "ick"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges = <0x0 0x48320000 0x1000>; 254 255 counter32k: counter@0 { 256 compatible = "ti,omap-counter32k"; 257 reg = <0x0 0x20>; 258 }; 259 }; 260 261 intc: interrupt-controller@48200000 { 262 compatible = "ti,omap3-intc"; 263 interrupt-controller; 264 #interrupt-cells = <1>; 265 reg = <0x48200000 0x1000>; 266 }; 267 268 target-module@48056000 { 269 compatible = "ti,sysc-omap2", "ti,sysc"; 270 reg = <0x48056000 0x4>, 271 <0x4805602c 0x4>, 272 <0x48056028 0x4>; 273 reg-names = "rev", "sysc", "syss"; 274 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 275 SYSC_OMAP2_EMUFREE | 276 SYSC_OMAP2_SOFTRESET | 277 SYSC_OMAP2_AUTOIDLE)>; 278 ti,sysc-midle = <SYSC_IDLE_FORCE>, 279 <SYSC_IDLE_NO>, 280 <SYSC_IDLE_SMART>; 281 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 282 <SYSC_IDLE_NO>, 283 <SYSC_IDLE_SMART>; 284 ti,syss-mask = <1>; 285 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ 286 clocks = <&core_l3_ick>; 287 clock-names = "ick"; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0 0x48056000 0x1000>; 291 292 sdma: dma-controller@0 { 293 compatible = "ti,omap3430-sdma", "ti,omap-sdma"; 294 reg = <0x0 0x1000>; 295 interrupts = <12>, 296 <13>, 297 <14>, 298 <15>; 299 #dma-cells = <1>; 300 dma-channels = <32>; 301 dma-requests = <96>; 302 }; 303 }; 304 305 gpio1: gpio@48310000 { 306 compatible = "ti,omap3-gpio"; 307 reg = <0x48310000 0x200>; 308 interrupts = <29>; 309 ti,hwmods = "gpio1"; 310 ti,gpio-always-on; 311 gpio-controller; 312 #gpio-cells = <2>; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 317 gpio2: gpio@49050000 { 318 compatible = "ti,omap3-gpio"; 319 reg = <0x49050000 0x200>; 320 interrupts = <30>; 321 ti,hwmods = "gpio2"; 322 gpio-controller; 323 #gpio-cells = <2>; 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 }; 327 328 gpio3: gpio@49052000 { 329 compatible = "ti,omap3-gpio"; 330 reg = <0x49052000 0x200>; 331 interrupts = <31>; 332 ti,hwmods = "gpio3"; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 }; 338 339 gpio4: gpio@49054000 { 340 compatible = "ti,omap3-gpio"; 341 reg = <0x49054000 0x200>; 342 interrupts = <32>; 343 ti,hwmods = "gpio4"; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 }; 349 350 gpio5: gpio@49056000 { 351 compatible = "ti,omap3-gpio"; 352 reg = <0x49056000 0x200>; 353 interrupts = <33>; 354 ti,hwmods = "gpio5"; 355 gpio-controller; 356 #gpio-cells = <2>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 gpio6: gpio@49058000 { 362 compatible = "ti,omap3-gpio"; 363 reg = <0x49058000 0x200>; 364 interrupts = <34>; 365 ti,hwmods = "gpio6"; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 372 uart1: serial@4806a000 { 373 compatible = "ti,omap3-uart"; 374 reg = <0x4806a000 0x2000>; 375 interrupts-extended = <&intc 72>; 376 dmas = <&sdma 49 &sdma 50>; 377 dma-names = "tx", "rx"; 378 ti,hwmods = "uart1"; 379 clock-frequency = <48000000>; 380 }; 381 382 uart2: serial@4806c000 { 383 compatible = "ti,omap3-uart"; 384 reg = <0x4806c000 0x400>; 385 interrupts-extended = <&intc 73>; 386 dmas = <&sdma 51 &sdma 52>; 387 dma-names = "tx", "rx"; 388 ti,hwmods = "uart2"; 389 clock-frequency = <48000000>; 390 }; 391 392 uart3: serial@49020000 { 393 compatible = "ti,omap3-uart"; 394 reg = <0x49020000 0x400>; 395 interrupts-extended = <&intc 74>; 396 dmas = <&sdma 53 &sdma 54>; 397 dma-names = "tx", "rx"; 398 ti,hwmods = "uart3"; 399 clock-frequency = <48000000>; 400 }; 401 402 i2c1: i2c@48070000 { 403 compatible = "ti,omap3-i2c"; 404 reg = <0x48070000 0x80>; 405 interrupts = <56>; 406 dmas = <&sdma 27 &sdma 28>; 407 dma-names = "tx", "rx"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 ti,hwmods = "i2c1"; 411 }; 412 413 i2c2: i2c@48072000 { 414 compatible = "ti,omap3-i2c"; 415 reg = <0x48072000 0x80>; 416 interrupts = <57>; 417 dmas = <&sdma 29 &sdma 30>; 418 dma-names = "tx", "rx"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 ti,hwmods = "i2c2"; 422 }; 423 424 i2c3: i2c@48060000 { 425 compatible = "ti,omap3-i2c"; 426 reg = <0x48060000 0x80>; 427 interrupts = <61>; 428 dmas = <&sdma 25 &sdma 26>; 429 dma-names = "tx", "rx"; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 ti,hwmods = "i2c3"; 433 }; 434 435 mailbox: mailbox@48094000 { 436 compatible = "ti,omap3-mailbox"; 437 ti,hwmods = "mailbox"; 438 reg = <0x48094000 0x200>; 439 interrupts = <26>; 440 #mbox-cells = <1>; 441 ti,mbox-num-users = <2>; 442 ti,mbox-num-fifos = <2>; 443 mbox_dsp: dsp { 444 ti,mbox-tx = <0 0 0>; 445 ti,mbox-rx = <1 0 0>; 446 }; 447 }; 448 449 mcspi1: spi@48098000 { 450 compatible = "ti,omap2-mcspi"; 451 reg = <0x48098000 0x100>; 452 interrupts = <65>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 ti,hwmods = "mcspi1"; 456 ti,spi-num-cs = <4>; 457 dmas = <&sdma 35>, 458 <&sdma 36>, 459 <&sdma 37>, 460 <&sdma 38>, 461 <&sdma 39>, 462 <&sdma 40>, 463 <&sdma 41>, 464 <&sdma 42>; 465 dma-names = "tx0", "rx0", "tx1", "rx1", 466 "tx2", "rx2", "tx3", "rx3"; 467 }; 468 469 mcspi2: spi@4809a000 { 470 compatible = "ti,omap2-mcspi"; 471 reg = <0x4809a000 0x100>; 472 interrupts = <66>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 ti,hwmods = "mcspi2"; 476 ti,spi-num-cs = <2>; 477 dmas = <&sdma 43>, 478 <&sdma 44>, 479 <&sdma 45>, 480 <&sdma 46>; 481 dma-names = "tx0", "rx0", "tx1", "rx1"; 482 }; 483 484 mcspi3: spi@480b8000 { 485 compatible = "ti,omap2-mcspi"; 486 reg = <0x480b8000 0x100>; 487 interrupts = <91>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 ti,hwmods = "mcspi3"; 491 ti,spi-num-cs = <2>; 492 dmas = <&sdma 15>, 493 <&sdma 16>, 494 <&sdma 23>, 495 <&sdma 24>; 496 dma-names = "tx0", "rx0", "tx1", "rx1"; 497 }; 498 499 mcspi4: spi@480ba000 { 500 compatible = "ti,omap2-mcspi"; 501 reg = <0x480ba000 0x100>; 502 interrupts = <48>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 ti,hwmods = "mcspi4"; 506 ti,spi-num-cs = <1>; 507 dmas = <&sdma 70>, <&sdma 71>; 508 dma-names = "tx0", "rx0"; 509 }; 510 511 hdqw1w: 1w@480b2000 { 512 compatible = "ti,omap3-1w"; 513 reg = <0x480b2000 0x1000>; 514 interrupts = <58>; 515 ti,hwmods = "hdq1w"; 516 }; 517 518 mmc1: mmc@4809c000 { 519 compatible = "ti,omap3-hsmmc"; 520 reg = <0x4809c000 0x200>; 521 interrupts = <83>; 522 ti,hwmods = "mmc1"; 523 ti,dual-volt; 524 dmas = <&sdma 61>, <&sdma 62>; 525 dma-names = "tx", "rx"; 526 pbias-supply = <&pbias_mmc_reg>; 527 }; 528 529 mmc2: mmc@480b4000 { 530 compatible = "ti,omap3-hsmmc"; 531 reg = <0x480b4000 0x200>; 532 interrupts = <86>; 533 ti,hwmods = "mmc2"; 534 dmas = <&sdma 47>, <&sdma 48>; 535 dma-names = "tx", "rx"; 536 }; 537 538 mmc3: mmc@480ad000 { 539 compatible = "ti,omap3-hsmmc"; 540 reg = <0x480ad000 0x200>; 541 interrupts = <94>; 542 ti,hwmods = "mmc3"; 543 dmas = <&sdma 77>, <&sdma 78>; 544 dma-names = "tx", "rx"; 545 }; 546 547 mmu_isp: mmu@480bd400 { 548 #iommu-cells = <0>; 549 compatible = "ti,omap2-iommu"; 550 reg = <0x480bd400 0x80>; 551 interrupts = <24>; 552 ti,hwmods = "mmu_isp"; 553 ti,#tlb-entries = <8>; 554 }; 555 556 mmu_iva: mmu@5d000000 { 557 #iommu-cells = <0>; 558 compatible = "ti,omap2-iommu"; 559 reg = <0x5d000000 0x80>; 560 interrupts = <28>; 561 ti,hwmods = "mmu_iva"; 562 status = "disabled"; 563 }; 564 565 wdt2: wdt@48314000 { 566 compatible = "ti,omap3-wdt"; 567 reg = <0x48314000 0x80>; 568 ti,hwmods = "wd_timer2"; 569 }; 570 571 mcbsp1: mcbsp@48074000 { 572 compatible = "ti,omap3-mcbsp"; 573 reg = <0x48074000 0xff>; 574 reg-names = "mpu"; 575 interrupts = <16>, /* OCP compliant interrupt */ 576 <59>, /* TX interrupt */ 577 <60>; /* RX interrupt */ 578 interrupt-names = "common", "tx", "rx"; 579 ti,buffer-size = <128>; 580 ti,hwmods = "mcbsp1"; 581 dmas = <&sdma 31>, 582 <&sdma 32>; 583 dma-names = "tx", "rx"; 584 clocks = <&mcbsp1_fck>; 585 clock-names = "fck"; 586 status = "disabled"; 587 }; 588 589 /* Likely needs to be tagged disabled on HS devices */ 590 rng_target: target-module@480a0000 { 591 compatible = "ti,sysc-omap2", "ti,sysc"; 592 reg = <0x480a003c 0x4>, 593 <0x480a0040 0x4>, 594 <0x480a0044 0x4>; 595 reg-names = "rev", "sysc", "syss"; 596 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 597 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 598 <SYSC_IDLE_NO>; 599 ti,syss-mask = <1>; 600 clocks = <&rng_ick>; 601 clock-names = "ick"; 602 #address-cells = <1>; 603 #size-cells = <1>; 604 ranges = <0 0x480a0000 0x2000>; 605 606 rng: rng@0 { 607 compatible = "ti,omap2-rng"; 608 reg = <0x0 0x2000>; 609 interrupts = <52>; 610 }; 611 }; 612 613 mcbsp2: mcbsp@49022000 { 614 compatible = "ti,omap3-mcbsp"; 615 reg = <0x49022000 0xff>, 616 <0x49028000 0xff>; 617 reg-names = "mpu", "sidetone"; 618 interrupts = <17>, /* OCP compliant interrupt */ 619 <62>, /* TX interrupt */ 620 <63>, /* RX interrupt */ 621 <4>; /* Sidetone */ 622 interrupt-names = "common", "tx", "rx", "sidetone"; 623 ti,buffer-size = <1280>; 624 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 625 dmas = <&sdma 33>, 626 <&sdma 34>; 627 dma-names = "tx", "rx"; 628 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; 629 clock-names = "fck", "ick"; 630 status = "disabled"; 631 }; 632 633 mcbsp3: mcbsp@49024000 { 634 compatible = "ti,omap3-mcbsp"; 635 reg = <0x49024000 0xff>, 636 <0x4902a000 0xff>; 637 reg-names = "mpu", "sidetone"; 638 interrupts = <22>, /* OCP compliant interrupt */ 639 <89>, /* TX interrupt */ 640 <90>, /* RX interrupt */ 641 <5>; /* Sidetone */ 642 interrupt-names = "common", "tx", "rx", "sidetone"; 643 ti,buffer-size = <128>; 644 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 645 dmas = <&sdma 17>, 646 <&sdma 18>; 647 dma-names = "tx", "rx"; 648 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; 649 clock-names = "fck", "ick"; 650 status = "disabled"; 651 }; 652 653 mcbsp4: mcbsp@49026000 { 654 compatible = "ti,omap3-mcbsp"; 655 reg = <0x49026000 0xff>; 656 reg-names = "mpu"; 657 interrupts = <23>, /* OCP compliant interrupt */ 658 <54>, /* TX interrupt */ 659 <55>; /* RX interrupt */ 660 interrupt-names = "common", "tx", "rx"; 661 ti,buffer-size = <128>; 662 ti,hwmods = "mcbsp4"; 663 dmas = <&sdma 19>, 664 <&sdma 20>; 665 dma-names = "tx", "rx"; 666 clocks = <&mcbsp4_fck>; 667 clock-names = "fck"; 668 #sound-dai-cells = <0>; 669 status = "disabled"; 670 }; 671 672 mcbsp5: mcbsp@48096000 { 673 compatible = "ti,omap3-mcbsp"; 674 reg = <0x48096000 0xff>; 675 reg-names = "mpu"; 676 interrupts = <27>, /* OCP compliant interrupt */ 677 <81>, /* TX interrupt */ 678 <82>; /* RX interrupt */ 679 interrupt-names = "common", "tx", "rx"; 680 ti,buffer-size = <128>; 681 ti,hwmods = "mcbsp5"; 682 dmas = <&sdma 21>, 683 <&sdma 22>; 684 dma-names = "tx", "rx"; 685 clocks = <&mcbsp5_fck>; 686 clock-names = "fck"; 687 status = "disabled"; 688 }; 689 690 sham: sham@480c3000 { 691 compatible = "ti,omap3-sham"; 692 ti,hwmods = "sham"; 693 reg = <0x480c3000 0x64>; 694 interrupts = <49>; 695 dmas = <&sdma 69>; 696 dma-names = "rx"; 697 }; 698 699 timer1_target: target-module@48318000 { 700 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 701 reg = <0x48318000 0x4>, 702 <0x48318010 0x4>, 703 <0x48318014 0x4>; 704 reg-names = "rev", "sysc", "syss"; 705 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 706 SYSC_OMAP2_EMUFREE | 707 SYSC_OMAP2_ENAWAKEUP | 708 SYSC_OMAP2_SOFTRESET | 709 SYSC_OMAP2_AUTOIDLE)>; 710 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 711 <SYSC_IDLE_NO>, 712 <SYSC_IDLE_SMART>; 713 ti,syss-mask = <1>; 714 clocks = <&gpt1_fck>, <&gpt1_ick>; 715 clock-names = "fck", "ick"; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges = <0x0 0x48318000 0x1000>; 719 720 timer1: timer@0 { 721 compatible = "ti,omap3430-timer"; 722 reg = <0x0 0x80>; 723 clocks = <&gpt1_fck>; 724 clock-names = "fck"; 725 interrupts = <37>; 726 ti,timer-alwon; 727 }; 728 }; 729 730 timer2_target: target-module@49032000 { 731 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 732 reg = <0x49032000 0x4>, 733 <0x49032010 0x4>, 734 <0x49032014 0x4>; 735 reg-names = "rev", "sysc", "syss"; 736 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 737 SYSC_OMAP2_EMUFREE | 738 SYSC_OMAP2_ENAWAKEUP | 739 SYSC_OMAP2_SOFTRESET | 740 SYSC_OMAP2_AUTOIDLE)>; 741 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 742 <SYSC_IDLE_NO>, 743 <SYSC_IDLE_SMART>; 744 ti,syss-mask = <1>; 745 clocks = <&gpt2_fck>, <&gpt2_ick>; 746 clock-names = "fck", "ick"; 747 #address-cells = <1>; 748 #size-cells = <1>; 749 ranges = <0x0 0x49032000 0x1000>; 750 751 timer2: timer@0 { 752 compatible = "ti,omap3430-timer"; 753 reg = <0 0x400>; 754 interrupts = <38>; 755 }; 756 }; 757 758 timer3: timer@49034000 { 759 compatible = "ti,omap3430-timer"; 760 reg = <0x49034000 0x400>; 761 interrupts = <39>; 762 ti,hwmods = "timer3"; 763 }; 764 765 timer4: timer@49036000 { 766 compatible = "ti,omap3430-timer"; 767 reg = <0x49036000 0x400>; 768 interrupts = <40>; 769 ti,hwmods = "timer4"; 770 }; 771 772 timer5: timer@49038000 { 773 compatible = "ti,omap3430-timer"; 774 reg = <0x49038000 0x400>; 775 interrupts = <41>; 776 ti,hwmods = "timer5"; 777 ti,timer-dsp; 778 }; 779 780 timer6: timer@4903a000 { 781 compatible = "ti,omap3430-timer"; 782 reg = <0x4903a000 0x400>; 783 interrupts = <42>; 784 ti,hwmods = "timer6"; 785 ti,timer-dsp; 786 }; 787 788 timer7: timer@4903c000 { 789 compatible = "ti,omap3430-timer"; 790 reg = <0x4903c000 0x400>; 791 interrupts = <43>; 792 ti,hwmods = "timer7"; 793 ti,timer-dsp; 794 }; 795 796 timer8: timer@4903e000 { 797 compatible = "ti,omap3430-timer"; 798 reg = <0x4903e000 0x400>; 799 interrupts = <44>; 800 ti,hwmods = "timer8"; 801 ti,timer-pwm; 802 ti,timer-dsp; 803 }; 804 805 timer9: timer@49040000 { 806 compatible = "ti,omap3430-timer"; 807 reg = <0x49040000 0x400>; 808 interrupts = <45>; 809 ti,hwmods = "timer9"; 810 ti,timer-pwm; 811 }; 812 813 timer10: timer@48086000 { 814 compatible = "ti,omap3430-timer"; 815 reg = <0x48086000 0x400>; 816 interrupts = <46>; 817 ti,hwmods = "timer10"; 818 ti,timer-pwm; 819 }; 820 821 timer11: timer@48088000 { 822 compatible = "ti,omap3430-timer"; 823 reg = <0x48088000 0x400>; 824 interrupts = <47>; 825 ti,hwmods = "timer11"; 826 ti,timer-pwm; 827 }; 828 829 timer12_target: target-module@48304000 { 830 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 831 reg = <0x48304000 0x4>, 832 <0x48304010 0x4>, 833 <0x48304014 0x4>; 834 reg-names = "rev", "sysc", "syss"; 835 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 836 SYSC_OMAP2_EMUFREE | 837 SYSC_OMAP2_ENAWAKEUP | 838 SYSC_OMAP2_SOFTRESET | 839 SYSC_OMAP2_AUTOIDLE)>; 840 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 841 <SYSC_IDLE_NO>, 842 <SYSC_IDLE_SMART>; 843 ti,syss-mask = <1>; 844 clocks = <&gpt12_fck>, <&gpt12_ick>; 845 clock-names = "fck", "ick"; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 ranges = <0x0 0x48304000 0x1000>; 849 850 timer12: timer@0 { 851 compatible = "ti,omap3430-timer"; 852 reg = <0 0x400>; 853 interrupts = <95>; 854 ti,timer-alwon; 855 ti,timer-secure; 856 }; 857 }; 858 859 usbhstll: usbhstll@48062000 { 860 compatible = "ti,usbhs-tll"; 861 reg = <0x48062000 0x1000>; 862 interrupts = <78>; 863 ti,hwmods = "usb_tll_hs"; 864 }; 865 866 usbhshost: usbhshost@48064000 { 867 compatible = "ti,usbhs-host"; 868 reg = <0x48064000 0x400>; 869 ti,hwmods = "usb_host_hs"; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 ranges; 873 874 usbhsohci: ohci@48064400 { 875 compatible = "ti,ohci-omap3"; 876 reg = <0x48064400 0x400>; 877 interrupts = <76>; 878 remote-wakeup-connected; 879 }; 880 881 usbhsehci: ehci@48064800 { 882 compatible = "ti,ehci-omap"; 883 reg = <0x48064800 0x400>; 884 interrupts = <77>; 885 }; 886 }; 887 888 gpmc: gpmc@6e000000 { 889 compatible = "ti,omap3430-gpmc"; 890 ti,hwmods = "gpmc"; 891 reg = <0x6e000000 0x02d0>; 892 interrupts = <20>; 893 dmas = <&sdma 4>; 894 dma-names = "rxtx"; 895 gpmc,num-cs = <8>; 896 gpmc,num-waitpins = <4>; 897 #address-cells = <2>; 898 #size-cells = <1>; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 gpio-controller; 902 #gpio-cells = <2>; 903 }; 904 905 usb_otg_hs: usb_otg_hs@480ab000 { 906 compatible = "ti,omap3-musb"; 907 reg = <0x480ab000 0x1000>; 908 interrupts = <92>, <93>; 909 interrupt-names = "mc", "dma"; 910 ti,hwmods = "usb_otg_hs"; 911 multipoint = <1>; 912 num-eps = <16>; 913 ram-bits = <12>; 914 }; 915 916 dss: dss@48050000 { 917 compatible = "ti,omap3-dss"; 918 reg = <0x48050000 0x200>; 919 status = "disabled"; 920 ti,hwmods = "dss_core"; 921 clocks = <&dss1_alwon_fck>; 922 clock-names = "fck"; 923 #address-cells = <1>; 924 #size-cells = <1>; 925 ranges; 926 927 dispc@48050400 { 928 compatible = "ti,omap3-dispc"; 929 reg = <0x48050400 0x400>; 930 interrupts = <25>; 931 ti,hwmods = "dss_dispc"; 932 clocks = <&dss1_alwon_fck>; 933 clock-names = "fck"; 934 }; 935 936 dsi: encoder@4804fc00 { 937 compatible = "ti,omap3-dsi"; 938 reg = <0x4804fc00 0x200>, 939 <0x4804fe00 0x40>, 940 <0x4804ff00 0x20>; 941 reg-names = "proto", "phy", "pll"; 942 interrupts = <25>; 943 status = "disabled"; 944 ti,hwmods = "dss_dsi1"; 945 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 946 clock-names = "fck", "sys_clk"; 947 948 #address-cells = <1>; 949 #size-cells = <0>; 950 }; 951 952 rfbi: encoder@48050800 { 953 compatible = "ti,omap3-rfbi"; 954 reg = <0x48050800 0x100>; 955 status = "disabled"; 956 ti,hwmods = "dss_rfbi"; 957 clocks = <&dss1_alwon_fck>, <&dss_ick>; 958 clock-names = "fck", "ick"; 959 }; 960 961 venc: encoder@48050c00 { 962 compatible = "ti,omap3-venc"; 963 reg = <0x48050c00 0x100>; 964 status = "disabled"; 965 ti,hwmods = "dss_venc"; 966 clocks = <&dss_tv_fck>; 967 clock-names = "fck"; 968 }; 969 }; 970 971 ssi: ssi-controller@48058000 { 972 compatible = "ti,omap3-ssi"; 973 ti,hwmods = "ssi"; 974 975 status = "disabled"; 976 977 reg = <0x48058000 0x1000>, 978 <0x48059000 0x1000>; 979 reg-names = "sys", 980 "gdd"; 981 982 interrupts = <71>; 983 interrupt-names = "gdd_mpu"; 984 985 #address-cells = <1>; 986 #size-cells = <1>; 987 ranges; 988 989 ssi_port1: ssi-port@4805a000 { 990 compatible = "ti,omap3-ssi-port"; 991 992 reg = <0x4805a000 0x800>, 993 <0x4805a800 0x800>; 994 reg-names = "tx", 995 "rx"; 996 997 interrupts = <67>, 998 <68>; 999 }; 1000 1001 ssi_port2: ssi-port@4805b000 { 1002 compatible = "ti,omap3-ssi-port"; 1003 1004 reg = <0x4805b000 0x800>, 1005 <0x4805b800 0x800>; 1006 reg-names = "tx", 1007 "rx"; 1008 1009 interrupts = <69>, 1010 <70>; 1011 }; 1012 }; 1013 }; 1014}; 1015 1016#include "omap3xxx-clocks.dtsi" 1017 1018/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ 1019&timer1_target { 1020 ti,no-reset-on-init; 1021 ti,no-idle; 1022 timer@0 { 1023 assigned-clocks = <&gpt1_fck>; 1024 assigned-clock-parents = <&omap_32k_fck>; 1025 }; 1026}; 1027