1/*
2 * Device Tree Source for OMAP4460 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#include "omap4.dtsi"
11
12/ {
13	cpus {
14		/* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
15		cpu0: cpu@0 {
16			operating-points = <
17				/* kHz    uV */
18				350000  1025000
19				700000  1200000
20				920000  1313000
21			>;
22			clock-latency = <300000>; /* From legacy driver */
23
24			/* cooling options */
25			#cooling-cells = <2>; /* min followed by max */
26		};
27	};
28
29	thermal-zones {
30		#include "omap4-cpu-thermal.dtsi"
31	};
32
33	ocp {
34		bandgap: bandgap@4a002260 {
35			reg = <0x4a002260 0x4
36			       0x4a00232C 0x4
37			       0x4a002378 0x18>;
38			compatible = "ti,omap4460-bandgap";
39			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
40			gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
41
42			#thermal-sensor-cells = <0>;
43		};
44
45		abb_mpu: regulator-abb-mpu {
46			status = "okay";
47
48			reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
49			      <0x4A002268 0x4>;
50			reg-names = "base-address", "int-address",
51				    "efuse-address";
52
53			ti,abb_info = <
54			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
55			1025000		0	0	0	0	0
56			1200000		0	0	0	0	0
57			1313000		0	0	0x100000 0x40000 0
58			1375000		1	0	0	0	0
59			1389000		1	0	0	0	0
60			>;
61		};
62
63		abb_iva: regulator-abb-iva {
64			status = "okay";
65
66			reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
67			      <0x4A002268 0x4>;
68			reg-names = "base-address", "int-address",
69				    "efuse-address";
70
71			ti,abb_info = <
72			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
73			950000		0	0	0	0	0
74			1140000		0	0	0	0	0
75			1291000		0	0	0x200000 0	0
76			1375000		1	0	0	0	0
77			1376000		1	0	0	0	0
78			>;
79		};
80	};
81
82};
83
84&cpu_thermal {
85	coefficients = <348 (-9301)>;
86};
87
88/* Only some L4 CFG interconnect ranges are different on 4460 */
89&l4_cfg_segment_300000 {
90	ranges = <0x00000000 0x00300000 0x020000>,	/* ap 67 */
91		 <0x00040000 0x00340000 0x001000>,	/* ap 68 */
92		 <0x00020000 0x00320000 0x004000>,	/* ap 71 */
93		 <0x00024000 0x00324000 0x002000>,	/* ap 72 */
94		 <0x00026000 0x00326000 0x001000>,	/* ap 73 */
95		 <0x00027000 0x00327000 0x001000>,	/* ap 74 */
96		 <0x00028000 0x00328000 0x001000>,	/* ap 75 */
97		 <0x00029000 0x00329000 0x001000>,	/* ap 76 */
98		 <0x00030000 0x00330000 0x010000>,	/* ap 77 */
99		 <0x0002a000 0x0032a000 0x002000>,	/* ap 90 */
100		 <0x0002c000 0x0032c000 0x004000>,	/* ap 91 */
101		 <0x00010000 0x00310000 0x008000>,	/* ap 92 */
102		 <0x00018000 0x00318000 0x004000>,	/* ap 93 */
103		 <0x0001c000 0x0031c000 0x002000>,	/* ap 94 */
104		 <0x0001e000 0x0031e000 0x002000>;	/* ap 95 */
105};
106
107&l4_cfg_target_0 {
108	ranges = <0x00000000 0x00000000 0x00010000>,
109		 <0x00010000 0x00010000 0x00008000>,
110		 <0x00018000 0x00018000 0x00004000>,
111		 <0x0001c000 0x0001c000 0x00002000>,
112		 <0x0001e000 0x0001e000 0x00002000>,
113		 <0x00020000 0x00020000 0x00004000>,
114		 <0x00024000 0x00024000 0x00002000>,
115		 <0x00026000 0x00026000 0x00001000>,
116		 <0x00027000 0x00027000 0x00001000>,
117		 <0x00028000 0x00028000 0x00001000>,
118		 <0x00029000 0x00029000 0x00001000>,
119		 <0x0002a000 0x0002a000 0x00002000>,
120		 <0x0002c000 0x0002c000 0x00004000>,
121		 <0x00030000 0x00030000 0x00010000>;
122};
123
124&pmu {
125	compatible = "arm,cortex-a9-pmu";
126	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
127		     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
128};
129
130/include/ "omap446x-clocks.dtsi"
131