1&l4_cfg { /* 0x4a000000 */ 2 compatible = "ti,omap5-l4-cfg", "simple-pm-bus"; 3 power-domains = <&prm_core>; 4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; 5 clock-names = "fck"; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 9 reg-names = "ap", "la", "ia0"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */ 17 <0x00280000 0x4a280000 0x080000>, /* segment 5 */ 18 <0x00300000 0x4a300000 0x080000>; /* segment 6 */ 19 20 segment@0 { /* 0x4a000000 */ 21 compatible = "simple-pm-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 25 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 26 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 27 <0x00002000 0x00002000 0x001000>, /* ap 3 */ 28 <0x00003000 0x00003000 0x001000>, /* ap 4 */ 29 <0x00004000 0x00004000 0x001000>, /* ap 5 */ 30 <0x00005000 0x00005000 0x001000>, /* ap 6 */ 31 <0x00056000 0x00056000 0x001000>, /* ap 7 */ 32 <0x00057000 0x00057000 0x001000>, /* ap 8 */ 33 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ 34 <0x00058000 0x00058000 0x001000>, /* ap 10 */ 35 <0x00062000 0x00062000 0x001000>, /* ap 11 */ 36 <0x00063000 0x00063000 0x001000>, /* ap 12 */ 37 <0x00008000 0x00008000 0x002000>, /* ap 21 */ 38 <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ 39 <0x00066000 0x00066000 0x001000>, /* ap 23 */ 40 <0x00067000 0x00067000 0x001000>, /* ap 24 */ 41 <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ 42 <0x00060000 0x00060000 0x001000>, /* ap 70 */ 43 <0x00064000 0x00064000 0x001000>, /* ap 71 */ 44 <0x00065000 0x00065000 0x001000>, /* ap 72 */ 45 <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ 46 <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ 47 <0x00070000 0x00070000 0x004000>, /* ap 79 */ 48 <0x00074000 0x00074000 0x001000>, /* ap 80 */ 49 <0x00075000 0x00075000 0x001000>, /* ap 81 */ 50 <0x00076000 0x00076000 0x001000>, /* ap 82 */ 51 <0x00020000 0x00020000 0x020000>, /* ap 109 */ 52 <0x00040000 0x00040000 0x001000>, /* ap 110 */ 53 <0x00059000 0x00059000 0x001000>; /* ap 111 */ 54 55 target-module@2000 { /* 0x4a002000, ap 3 44.0 */ 56 compatible = "ti,sysc-omap4", "ti,sysc"; 57 reg = <0x2000 0x4>; 58 reg-names = "rev"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges = <0x0 0x2000 0x1000>; 62 63 scm_core: scm@0 { 64 compatible = "ti,omap5-scm-core", "simple-bus"; 65 reg = <0x0 0x1000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges = <0 0 0x800>; 69 70 scm_conf: scm_conf@0 { 71 compatible = "syscon"; 72 reg = <0x0 0x800>; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 }; 76 }; 77 78 scm_padconf_core: scm@800 { 79 compatible = "ti,omap5-scm-padconf-core", 80 "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0 0x800 0x800>; 84 85 omap5_pmx_core: pinmux@40 { 86 compatible = "ti,omap5-padconf", 87 "pinctrl-single"; 88 reg = <0x40 0x01b6>; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 #pinctrl-cells = <1>; 92 #interrupt-cells = <1>; 93 interrupt-controller; 94 pinctrl-single,register-width = <16>; 95 pinctrl-single,function-mask = <0x7fff>; 96 }; 97 98 omap5_padconf_global: omap5_padconf_global@5a0 { 99 compatible = "syscon", 100 "simple-bus"; 101 reg = <0x5a0 0xec>; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 0x5a0 0xec>; 105 106 pbias_regulator: pbias_regulator@60 { 107 compatible = "ti,pbias-omap5", "ti,pbias-omap"; 108 reg = <0x60 0x4>; 109 syscon = <&omap5_padconf_global>; 110 pbias_mmc_reg: pbias_mmc_omap5 { 111 regulator-name = "pbias_mmc_omap5"; 112 regulator-min-microvolt = <1800000>; 113 regulator-max-microvolt = <3300000>; 114 }; 115 }; 116 }; 117 }; 118 }; 119 120 target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ 121 compatible = "ti,sysc-omap4", "ti,sysc"; 122 reg = <0x4000 0x4>; 123 reg-names = "rev"; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x0 0x4000 0x1000>; 127 128 cm_core_aon: cm_core_aon@0 { 129 compatible = "ti,omap5-cm-core-aon", 130 "simple-bus"; 131 reg = <0x0 0x2000>; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges = <0 0 0x1000>; 135 136 cm_core_aon_clocks: clocks { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 }; 140 141 cm_core_aon_clockdomains: clockdomains { 142 }; 143 }; 144 }; 145 146 target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ 147 compatible = "ti,sysc-omap4", "ti,sysc"; 148 reg = <0x8000 0x4>; 149 reg-names = "rev"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0x0 0x8000 0x2000>; 153 154 cm_core: cm_core@0 { 155 compatible = "ti,omap5-cm-core", "simple-bus"; 156 reg = <0x0 0x2000>; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 ranges = <0 0 0x2000>; 160 161 cm_core_clocks: clocks { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 cm_core_clockdomains: clockdomains { 167 }; 168 }; 169 }; 170 171 target-module@20000 { /* 0x4a020000, ap 109 08.0 */ 172 compatible = "ti,sysc-omap4", "ti,sysc"; 173 reg = <0x20000 0x4>, 174 <0x20010 0x4>; 175 reg-names = "rev", "sysc"; 176 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 177 ti,sysc-midle = <SYSC_IDLE_FORCE>, 178 <SYSC_IDLE_NO>, 179 <SYSC_IDLE_SMART>, 180 <SYSC_IDLE_SMART_WKUP>; 181 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 182 <SYSC_IDLE_NO>, 183 <SYSC_IDLE_SMART>, 184 <SYSC_IDLE_SMART_WKUP>; 185 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 186 clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; 187 clock-names = "fck"; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges = <0x0 0x20000 0x20000>; 191 192 usb3: omap_dwc3@0 { 193 compatible = "ti,dwc3"; 194 reg = <0x0 0x10000>; 195 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 utmi-mode = <2>; 199 ranges = <0 0 0x20000>; 200 dwc3: usb@10000 { 201 compatible = "snps,dwc3"; 202 reg = <0x10000 0x10000>; 203 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 206 interrupt-names = "peripheral", 207 "host", 208 "otg"; 209 phys = <&usb2_phy>, <&usb3_phy>; 210 phy-names = "usb2-phy", "usb3-phy"; 211 dr_mode = "peripheral"; 212 }; 213 }; 214 }; 215 216 target-module@56000 { /* 0x4a056000, ap 7 02.0 */ 217 compatible = "ti,sysc-omap2", "ti,sysc"; 218 reg = <0x56000 0x4>, 219 <0x5602c 0x4>, 220 <0x56028 0x4>; 221 reg-names = "rev", "sysc", "syss"; 222 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 223 SYSC_OMAP2_EMUFREE | 224 SYSC_OMAP2_SOFTRESET | 225 SYSC_OMAP2_AUTOIDLE)>; 226 ti,sysc-midle = <SYSC_IDLE_FORCE>, 227 <SYSC_IDLE_NO>, 228 <SYSC_IDLE_SMART>; 229 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 230 <SYSC_IDLE_NO>, 231 <SYSC_IDLE_SMART>; 232 ti,syss-mask = <1>; 233 /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ 234 clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; 235 clock-names = "fck"; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges = <0x0 0x56000 0x1000>; 239 240 sdma: dma-controller@0 { 241 compatible = "ti,omap4430-sdma", "ti,omap-sdma"; 242 reg = <0x0 0x1000>; 243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 247 #dma-cells = <1>; 248 dma-channels = <32>; 249 dma-requests = <127>; 250 }; 251 }; 252 253 target-module@58000 { /* 0x4a058000, ap 10 06.0 */ 254 compatible = "ti,sysc"; 255 status = "disabled"; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 ranges = <0x00000000 0x00058000 0x00001000>, 259 <0x00001000 0x00059000 0x00001000>, 260 <0x00002000 0x0005a000 0x00001000>, 261 <0x00003000 0x0005b000 0x00001000>; 262 }; 263 264 target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ 265 compatible = "ti,sysc"; 266 status = "disabled"; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges = <0x0 0x5e000 0x2000>; 270 }; 271 272 target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ 273 compatible = "ti,sysc-omap2", "ti,sysc"; 274 reg = <0x62000 0x4>, 275 <0x62010 0x4>, 276 <0x62014 0x4>; 277 reg-names = "rev", "sysc", "syss"; 278 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 279 SYSC_OMAP2_ENAWAKEUP | 280 SYSC_OMAP2_SOFTRESET | 281 SYSC_OMAP2_AUTOIDLE)>; 282 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 283 <SYSC_IDLE_NO>, 284 <SYSC_IDLE_SMART>; 285 ti,syss-mask = <1>; 286 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 287 clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; 288 clock-names = "fck"; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges = <0x0 0x62000 0x1000>; 292 293 usbhstll: usbhstll@0 { 294 compatible = "ti,usbhs-tll"; 295 reg = <0x0 0x1000>; 296 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 297 }; 298 }; 299 300 target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ 301 compatible = "ti,sysc-omap4", "ti,sysc"; 302 reg = <0x64000 0x4>, 303 <0x64010 0x4>; 304 reg-names = "rev", "sysc"; 305 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 306 ti,sysc-midle = <SYSC_IDLE_FORCE>, 307 <SYSC_IDLE_NO>, 308 <SYSC_IDLE_SMART>, 309 <SYSC_IDLE_SMART_WKUP>; 310 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 311 <SYSC_IDLE_NO>, 312 <SYSC_IDLE_SMART>, 313 <SYSC_IDLE_SMART_WKUP>; 314 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 315 clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; 316 clock-names = "fck"; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges = <0x0 0x64000 0x1000>; 320 321 usbhshost: usbhshost@0 { 322 compatible = "ti,usbhs-host"; 323 reg = <0x0 0x800>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges = <0 0 0x1000>; 327 clocks = <&l3init_60m_fclk>, 328 <&xclk60mhsp1_ck>, 329 <&xclk60mhsp2_ck>; 330 clock-names = "refclk_60m_int", 331 "refclk_60m_ext_p1", 332 "refclk_60m_ext_p2"; 333 334 usbhsohci: ohci@800 { 335 compatible = "ti,ohci-omap3"; 336 reg = <0x800 0x400>; 337 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 338 remote-wakeup-connected; 339 }; 340 341 usbhsehci: ehci@c00 { 342 compatible = "ti,ehci-omap"; 343 reg = <0xc00 0x400>; 344 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 345 }; 346 }; 347 }; 348 349 target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ 350 compatible = "ti,sysc-omap2", "ti,sysc"; 351 reg = <0x66000 0x4>, 352 <0x66010 0x4>, 353 <0x66014 0x4>; 354 reg-names = "rev", "sysc", "syss"; 355 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 356 SYSC_OMAP2_SOFTRESET | 357 SYSC_OMAP2_AUTOIDLE)>; 358 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 359 <SYSC_IDLE_NO>, 360 <SYSC_IDLE_SMART>; 361 ti,syss-mask = <1>; 362 /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ 363 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; 364 clock-names = "fck"; 365 resets = <&prm_dsp 1>; 366 reset-names = "rstctrl"; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges = <0x0 0x66000 0x1000>; 370 371 mmu_dsp: mmu@0 { 372 compatible = "ti,omap4-iommu"; 373 reg = <0x0 0x100>; 374 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 375 #iommu-cells = <0>; 376 }; 377 }; 378 379 target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ 380 compatible = "ti,sysc"; 381 status = "disabled"; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 ranges = <0x0 0x70000 0x4000>; 385 }; 386 387 target-module@75000 { /* 0x4a075000, ap 81 32.0 */ 388 compatible = "ti,sysc"; 389 status = "disabled"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 ranges = <0x0 0x75000 0x1000>; 393 }; 394 }; 395 396 segment@80000 { /* 0x4a080000 */ 397 compatible = "simple-pm-bus"; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ 401 <0x0005a000 0x000da000 0x001000>, /* ap 14 */ 402 <0x0005b000 0x000db000 0x001000>, /* ap 15 */ 403 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ 404 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ 405 <0x0005e000 0x000de000 0x001000>, /* ap 18 */ 406 <0x00060000 0x000e0000 0x001000>, /* ap 19 */ 407 <0x00061000 0x000e1000 0x001000>, /* ap 20 */ 408 <0x00074000 0x000f4000 0x001000>, /* ap 25 */ 409 <0x00075000 0x000f5000 0x001000>, /* ap 26 */ 410 <0x00076000 0x000f6000 0x001000>, /* ap 27 */ 411 <0x00077000 0x000f7000 0x001000>, /* ap 28 */ 412 <0x00036000 0x000b6000 0x001000>, /* ap 65 */ 413 <0x00037000 0x000b7000 0x001000>, /* ap 66 */ 414 <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ 415 <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ 416 <0x00000000 0x00080000 0x004000>, /* ap 83 */ 417 <0x00004000 0x00084000 0x001000>, /* ap 84 */ 418 <0x00005000 0x00085000 0x001000>, /* ap 85 */ 419 <0x00006000 0x00086000 0x001000>, /* ap 86 */ 420 <0x00007000 0x00087000 0x001000>, /* ap 87 */ 421 <0x00008000 0x00088000 0x001000>, /* ap 88 */ 422 <0x00010000 0x00090000 0x004000>, /* ap 89 */ 423 <0x00014000 0x00094000 0x001000>, /* ap 90 */ 424 <0x00015000 0x00095000 0x001000>, /* ap 91 */ 425 <0x00016000 0x00096000 0x001000>, /* ap 92 */ 426 <0x00017000 0x00097000 0x001000>, /* ap 93 */ 427 <0x00018000 0x00098000 0x001000>, /* ap 94 */ 428 <0x00020000 0x000a0000 0x004000>, /* ap 95 */ 429 <0x00024000 0x000a4000 0x001000>, /* ap 96 */ 430 <0x00025000 0x000a5000 0x001000>, /* ap 97 */ 431 <0x00026000 0x000a6000 0x001000>, /* ap 98 */ 432 <0x00027000 0x000a7000 0x001000>, /* ap 99 */ 433 <0x00028000 0x000a8000 0x001000>; /* ap 100 */ 434 435 target-module@0 { /* 0x4a080000, ap 83 28.0 */ 436 compatible = "ti,sysc-omap2", "ti,sysc"; 437 reg = <0x0 0x4>, 438 <0x10 0x4>, 439 <0x14 0x4>; 440 reg-names = "rev", "sysc", "syss"; 441 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 442 SYSC_OMAP2_AUTOIDLE)>; 443 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 444 <SYSC_IDLE_NO>, 445 <SYSC_IDLE_SMART>; 446 ti,syss-mask = <1>; 447 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 448 clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; 449 clock-names = "fck"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0x00000000 0x00000000 0x00004000>, 453 <0x00004000 0x00004000 0x00001000>, 454 <0x00005000 0x00005000 0x00001000>, 455 <0x00006000 0x00006000 0x00001000>, 456 <0x00007000 0x00007000 0x00001000>; 457 458 ocp2scp@0 { 459 compatible = "ti,omap-ocp2scp"; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 reg = <0 0x20>; 463 }; 464 465 usb2_phy: usb2phy@4000 { 466 compatible = "ti,omap-usb2"; 467 reg = <0x4000 0x7c>; 468 syscon-phy-power = <&scm_conf 0x300>; 469 clocks = <&usb_phy_cm_clk32k>, 470 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; 471 clock-names = "wkupclk", "refclk"; 472 #phy-cells = <0>; 473 }; 474 475 usb3_phy: usb3phy@4400 { 476 compatible = "ti,omap-usb3"; 477 reg = <0x4400 0x80>, 478 <0x4800 0x64>, 479 <0x4c00 0x40>; 480 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 481 syscon-phy-power = <&scm_conf 0x370>; 482 clocks = <&usb_phy_cm_clk32k>, 483 <&sys_clkin>, 484 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; 485 clock-names = "wkupclk", 486 "sysclk", 487 "refclk"; 488 #phy-cells = <0>; 489 }; 490 }; 491 492 target-module@10000 { /* 0x4a090000, ap 89 36.0 */ 493 compatible = "ti,sysc-omap2", "ti,sysc"; 494 reg = <0x10000 0x4>, 495 <0x10010 0x4>, 496 <0x10014 0x4>; 497 reg-names = "rev", "sysc", "syss"; 498 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 499 SYSC_OMAP2_AUTOIDLE)>; 500 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 501 <SYSC_IDLE_NO>, 502 <SYSC_IDLE_SMART>; 503 ti,syss-mask = <1>; 504 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 505 clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; 506 clock-names = "fck"; 507 #address-cells = <1>; 508 #size-cells = <1>; 509 ranges = <0x00000000 0x00010000 0x00004000>, 510 <0x00004000 0x00014000 0x00001000>, 511 <0x00005000 0x00015000 0x00001000>, 512 <0x00006000 0x00016000 0x00001000>, 513 <0x00007000 0x00017000 0x00001000>; 514 515 ocp2scp@0 { 516 compatible = "ti,omap-ocp2scp"; 517 #address-cells = <1>; 518 #size-cells = <1>; 519 reg = <0x0 0x20>; 520 }; 521 522 sata_phy: phy@6000 { 523 compatible = "ti,phy-pipe3-sata"; 524 reg = <0x6000 0x80>, /* phy_rx */ 525 <0x6400 0x64>, /* phy_tx */ 526 <0x6800 0x40>; /* pll_ctrl */ 527 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 528 syscon-phy-power = <&scm_conf 0x374>; 529 clocks = <&sys_clkin>, 530 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; 531 clock-names = "sysclk", "refclk"; 532 #phy-cells = <0>; 533 }; 534 }; 535 536 target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ 537 compatible = "ti,sysc"; 538 status = "disabled"; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 ranges = <0x00000000 0x00020000 0x00004000>, 542 <0x00004000 0x00024000 0x00001000>, 543 <0x00005000 0x00025000 0x00001000>, 544 <0x00006000 0x00026000 0x00001000>, 545 <0x00007000 0x00027000 0x00001000>; 546 }; 547 548 target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ 549 compatible = "ti,sysc"; 550 status = "disabled"; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 ranges = <0x0 0x36000 0x1000>; 554 }; 555 556 target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ 557 compatible = "ti,sysc"; 558 status = "disabled"; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges = <0x0 0x4d000 0x1000>; 562 }; 563 564 target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ 565 compatible = "ti,sysc"; 566 status = "disabled"; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges = <0x0 0x59000 0x1000>; 570 }; 571 572 target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ 573 compatible = "ti,sysc"; 574 status = "disabled"; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 ranges = <0x0 0x5b000 0x1000>; 578 }; 579 580 target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ 581 compatible = "ti,sysc"; 582 status = "disabled"; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges = <0x0 0x5d000 0x1000>; 586 }; 587 588 target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ 589 compatible = "ti,sysc"; 590 status = "disabled"; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0x0 0x60000 0x1000>; 594 }; 595 596 target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ 597 compatible = "ti,sysc-omap4", "ti,sysc"; 598 reg = <0x74000 0x4>, 599 <0x74010 0x4>; 600 reg-names = "rev", "sysc"; 601 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 602 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 603 <SYSC_IDLE_NO>, 604 <SYSC_IDLE_SMART>; 605 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ 606 clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; 607 clock-names = "fck"; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0x0 0x74000 0x1000>; 611 612 mailbox: mailbox@0 { 613 compatible = "ti,omap4-mailbox"; 614 reg = <0x0 0x200>; 615 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 616 #mbox-cells = <1>; 617 ti,mbox-num-users = <3>; 618 ti,mbox-num-fifos = <8>; 619 mbox_ipu: mbox_ipu { 620 ti,mbox-tx = <0 0 0>; 621 ti,mbox-rx = <1 0 0>; 622 }; 623 mbox_dsp: mbox_dsp { 624 ti,mbox-tx = <3 0 0>; 625 ti,mbox-rx = <2 0 0>; 626 }; 627 }; 628 }; 629 630 target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ 631 compatible = "ti,sysc-omap2", "ti,sysc"; 632 reg = <0x76000 0x4>, 633 <0x76010 0x4>, 634 <0x76014 0x4>; 635 reg-names = "rev", "sysc", "syss"; 636 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 637 SYSC_OMAP2_ENAWAKEUP | 638 SYSC_OMAP2_SOFTRESET | 639 SYSC_OMAP2_AUTOIDLE)>; 640 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 641 <SYSC_IDLE_NO>, 642 <SYSC_IDLE_SMART>; 643 ti,syss-mask = <1>; 644 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ 645 clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; 646 clock-names = "fck"; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 ranges = <0x0 0x76000 0x1000>; 650 651 hwspinlock: spinlock@0 { 652 compatible = "ti,omap4-hwspinlock"; 653 reg = <0x0 0x1000>; 654 #hwlock-cells = <1>; 655 }; 656 }; 657 }; 658 659 segment@100000 { /* 0x4a100000 */ 660 compatible = "simple-pm-bus"; 661 #address-cells = <1>; 662 #size-cells = <1>; 663 ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ 664 <0x00003000 0x00103000 0x001000>, /* ap 60 */ 665 <0x00008000 0x00108000 0x001000>, /* ap 61 */ 666 <0x00009000 0x00109000 0x001000>, /* ap 62 */ 667 <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ 668 <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ 669 <0x00040000 0x00140000 0x010000>, /* ap 101 */ 670 <0x00050000 0x00150000 0x001000>; /* ap 102 */ 671 672 target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ 673 compatible = "ti,sysc"; 674 status = "disabled"; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges = <0x0 0x2000 0x1000>; 678 }; 679 680 target-module@8000 { /* 0x4a108000, ap 61 26.0 */ 681 compatible = "ti,sysc"; 682 status = "disabled"; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 ranges = <0x0 0x8000 0x1000>; 686 }; 687 688 target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ 689 compatible = "ti,sysc"; 690 status = "disabled"; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 ranges = <0x0 0xa000 0x1000>; 694 }; 695 696 target-module@40000 { /* 0x4a140000, ap 101 16.0 */ 697 compatible = "ti,sysc-omap4", "ti,sysc"; 698 reg = <0x400fc 4>, 699 <0x41100 4>; 700 reg-names = "rev", "sysc"; 701 ti,sysc-midle = <SYSC_IDLE_FORCE>, 702 <SYSC_IDLE_NO>, 703 <SYSC_IDLE_SMART>; 704 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 705 <SYSC_IDLE_NO>, 706 <SYSC_IDLE_SMART>, 707 <SYSC_IDLE_SMART_WKUP>; 708 power-domains = <&prm_l3init>; 709 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>; 710 clock-names = "fck"; 711 #size-cells = <1>; 712 #address-cells = <1>; 713 ranges = <0x0 0x40000 0x10000>; 714 715 sata: sata@0 { 716 compatible = "snps,dwc-ahci"; 717 reg = <0 0x1100>, <0x1100 0x8>; 718 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 719 phys = <&sata_phy>; 720 phy-names = "sata-phy"; 721 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; 722 ports-implemented = <0x1>; 723 }; 724 }; 725 }; 726 727 segment@180000 { /* 0x4a180000 */ 728 compatible = "simple-pm-bus"; 729 #address-cells = <1>; 730 #size-cells = <1>; 731 }; 732 733 segment@200000 { /* 0x4a200000 */ 734 compatible = "simple-pm-bus"; 735 #address-cells = <1>; 736 #size-cells = <1>; 737 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ 738 <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ 739 <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ 740 <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ 741 <0x00006000 0x00206000 0x001000>, /* ap 33 */ 742 <0x00007000 0x00207000 0x001000>, /* ap 34 */ 743 <0x00004000 0x00204000 0x001000>, /* ap 35 */ 744 <0x00005000 0x00205000 0x001000>, /* ap 36 */ 745 <0x00012000 0x00212000 0x001000>, /* ap 37 */ 746 <0x00013000 0x00213000 0x001000>, /* ap 38 */ 747 <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ 748 <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ 749 <0x00010000 0x00210000 0x001000>, /* ap 41 */ 750 <0x00011000 0x00211000 0x001000>, /* ap 42 */ 751 <0x00016000 0x00216000 0x001000>, /* ap 43 */ 752 <0x00017000 0x00217000 0x001000>, /* ap 44 */ 753 <0x00014000 0x00214000 0x001000>, /* ap 45 */ 754 <0x00015000 0x00215000 0x001000>, /* ap 46 */ 755 <0x00018000 0x00218000 0x001000>, /* ap 47 */ 756 <0x00019000 0x00219000 0x001000>, /* ap 48 */ 757 <0x00020000 0x00220000 0x001000>, /* ap 49 */ 758 <0x00021000 0x00221000 0x001000>, /* ap 50 */ 759 <0x00026000 0x00226000 0x001000>, /* ap 51 */ 760 <0x00027000 0x00227000 0x001000>, /* ap 52 */ 761 <0x00028000 0x00228000 0x001000>, /* ap 53 */ 762 <0x00029000 0x00229000 0x001000>, /* ap 54 */ 763 <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ 764 <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ 765 <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ 766 <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ 767 <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ 768 <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ 769 <0x00024000 0x00224000 0x001000>, /* ap 75 */ 770 <0x00025000 0x00225000 0x001000>, /* ap 76 */ 771 <0x00002000 0x00202000 0x001000>, /* ap 103 */ 772 <0x00003000 0x00203000 0x001000>, /* ap 104 */ 773 <0x00008000 0x00208000 0x001000>, /* ap 105 */ 774 <0x00009000 0x00209000 0x001000>, /* ap 106 */ 775 <0x00022000 0x00222000 0x001000>, /* ap 107 */ 776 <0x00023000 0x00223000 0x001000>; /* ap 108 */ 777 778 target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ 779 compatible = "ti,sysc"; 780 status = "disabled"; 781 #address-cells = <1>; 782 #size-cells = <1>; 783 ranges = <0x0 0x2000 0x1000>; 784 }; 785 786 target-module@4000 { /* 0x4a204000, ap 35 46.0 */ 787 compatible = "ti,sysc"; 788 status = "disabled"; 789 #address-cells = <1>; 790 #size-cells = <1>; 791 ranges = <0x0 0x4000 0x1000>; 792 }; 793 794 target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ 795 compatible = "ti,sysc"; 796 status = "disabled"; 797 #address-cells = <1>; 798 #size-cells = <1>; 799 ranges = <0x0 0x6000 0x1000>; 800 }; 801 802 target-module@8000 { /* 0x4a208000, ap 105 34.0 */ 803 compatible = "ti,sysc"; 804 status = "disabled"; 805 #address-cells = <1>; 806 #size-cells = <1>; 807 ranges = <0x0 0x8000 0x1000>; 808 }; 809 810 target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ 811 compatible = "ti,sysc"; 812 status = "disabled"; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 ranges = <0x0 0xa000 0x1000>; 816 }; 817 818 target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ 819 compatible = "ti,sysc"; 820 status = "disabled"; 821 #address-cells = <1>; 822 #size-cells = <1>; 823 ranges = <0x0 0xc000 0x1000>; 824 }; 825 826 target-module@10000 { /* 0x4a210000, ap 41 56.0 */ 827 compatible = "ti,sysc"; 828 status = "disabled"; 829 #address-cells = <1>; 830 #size-cells = <1>; 831 ranges = <0x0 0x10000 0x1000>; 832 }; 833 834 target-module@12000 { /* 0x4a212000, ap 37 52.0 */ 835 compatible = "ti,sysc"; 836 status = "disabled"; 837 #address-cells = <1>; 838 #size-cells = <1>; 839 ranges = <0x0 0x12000 0x1000>; 840 }; 841 842 target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ 843 compatible = "ti,sysc"; 844 status = "disabled"; 845 #address-cells = <1>; 846 #size-cells = <1>; 847 ranges = <0x0 0x14000 0x1000>; 848 }; 849 850 target-module@16000 { /* 0x4a216000, ap 43 42.0 */ 851 compatible = "ti,sysc"; 852 status = "disabled"; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 ranges = <0x0 0x16000 0x1000>; 856 }; 857 858 target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ 859 compatible = "ti,sysc"; 860 status = "disabled"; 861 #address-cells = <1>; 862 #size-cells = <1>; 863 ranges = <0x0 0x18000 0x1000>; 864 }; 865 866 target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ 867 compatible = "ti,sysc"; 868 status = "disabled"; 869 #address-cells = <1>; 870 #size-cells = <1>; 871 ranges = <0x0 0x1a000 0x1000>; 872 }; 873 874 target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ 875 compatible = "ti,sysc"; 876 status = "disabled"; 877 #address-cells = <1>; 878 #size-cells = <1>; 879 ranges = <0x0 0x1c000 0x1000>; 880 }; 881 882 target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ 883 compatible = "ti,sysc"; 884 status = "disabled"; 885 #address-cells = <1>; 886 #size-cells = <1>; 887 ranges = <0x0 0x1e000 0x1000>; 888 }; 889 890 target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ 891 compatible = "ti,sysc"; 892 status = "disabled"; 893 #address-cells = <1>; 894 #size-cells = <1>; 895 ranges = <0x0 0x20000 0x1000>; 896 }; 897 898 target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ 899 compatible = "ti,sysc"; 900 status = "disabled"; 901 #address-cells = <1>; 902 #size-cells = <1>; 903 ranges = <0x0 0x22000 0x1000>; 904 }; 905 906 target-module@24000 { /* 0x4a224000, ap 75 48.0 */ 907 compatible = "ti,sysc"; 908 status = "disabled"; 909 #address-cells = <1>; 910 #size-cells = <1>; 911 ranges = <0x0 0x24000 0x1000>; 912 }; 913 914 target-module@26000 { /* 0x4a226000, ap 51 24.0 */ 915 compatible = "ti,sysc"; 916 status = "disabled"; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges = <0x0 0x26000 0x1000>; 920 }; 921 922 target-module@28000 { /* 0x4a228000, ap 53 38.0 */ 923 compatible = "ti,sysc"; 924 status = "disabled"; 925 #address-cells = <1>; 926 #size-cells = <1>; 927 ranges = <0x0 0x28000 0x1000>; 928 }; 929 930 target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ 931 compatible = "ti,sysc"; 932 status = "disabled"; 933 #address-cells = <1>; 934 #size-cells = <1>; 935 ranges = <0x0 0x2a000 0x1000>; 936 }; 937 }; 938 939 segment@280000 { /* 0x4a280000 */ 940 compatible = "simple-pm-bus"; 941 #address-cells = <1>; 942 #size-cells = <1>; 943 }; 944 945 segment@300000 { /* 0x4a300000 */ 946 compatible = "simple-pm-bus"; 947 #address-cells = <1>; 948 #size-cells = <1>; 949 }; 950}; 951 952&l4_per { /* 0x48000000 */ 953 compatible = "ti,omap5-l4-per", "simple-pm-bus"; 954 power-domains = <&prm_core>; 955 clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>; 956 clock-names = "fck"; 957 reg = <0x48000000 0x800>, 958 <0x48000800 0x800>, 959 <0x48001000 0x400>, 960 <0x48001400 0x400>, 961 <0x48001800 0x400>, 962 <0x48001c00 0x400>; 963 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 964 #address-cells = <1>; 965 #size-cells = <1>; 966 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ 967 <0x00200000 0x48200000 0x200000>; /* segment 1 */ 968 969 segment@0 { /* 0x48000000 */ 970 compatible = "simple-pm-bus"; 971 #address-cells = <1>; 972 #size-cells = <1>; 973 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 974 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 975 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 976 <0x00020000 0x00020000 0x001000>, /* ap 3 */ 977 <0x00021000 0x00021000 0x001000>, /* ap 4 */ 978 <0x00032000 0x00032000 0x001000>, /* ap 5 */ 979 <0x00033000 0x00033000 0x001000>, /* ap 6 */ 980 <0x00034000 0x00034000 0x001000>, /* ap 7 */ 981 <0x00035000 0x00035000 0x001000>, /* ap 8 */ 982 <0x00036000 0x00036000 0x001000>, /* ap 9 */ 983 <0x00037000 0x00037000 0x001000>, /* ap 10 */ 984 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ 985 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ 986 <0x00055000 0x00055000 0x001000>, /* ap 13 */ 987 <0x00056000 0x00056000 0x001000>, /* ap 14 */ 988 <0x00057000 0x00057000 0x001000>, /* ap 15 */ 989 <0x00058000 0x00058000 0x001000>, /* ap 16 */ 990 <0x00059000 0x00059000 0x001000>, /* ap 17 */ 991 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ 992 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ 993 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ 994 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ 995 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ 996 <0x00060000 0x00060000 0x001000>, /* ap 23 */ 997 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ 998 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ 999 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ 1000 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ 1001 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ 1002 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ 1003 <0x00070000 0x00070000 0x001000>, /* ap 30 */ 1004 <0x00071000 0x00071000 0x001000>, /* ap 31 */ 1005 <0x00072000 0x00072000 0x001000>, /* ap 32 */ 1006 <0x00073000 0x00073000 0x001000>, /* ap 33 */ 1007 <0x00061000 0x00061000 0x001000>, /* ap 34 */ 1008 <0x00053000 0x00053000 0x001000>, /* ap 35 */ 1009 <0x00054000 0x00054000 0x001000>, /* ap 36 */ 1010 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ 1011 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ 1012 <0x00078000 0x00078000 0x001000>, /* ap 39 */ 1013 <0x00079000 0x00079000 0x001000>, /* ap 40 */ 1014 <0x00086000 0x00086000 0x001000>, /* ap 41 */ 1015 <0x00087000 0x00087000 0x001000>, /* ap 42 */ 1016 <0x00088000 0x00088000 0x001000>, /* ap 43 */ 1017 <0x00089000 0x00089000 0x001000>, /* ap 44 */ 1018 <0x00051000 0x00051000 0x001000>, /* ap 45 */ 1019 <0x00052000 0x00052000 0x001000>, /* ap 46 */ 1020 <0x00098000 0x00098000 0x001000>, /* ap 47 */ 1021 <0x00099000 0x00099000 0x001000>, /* ap 48 */ 1022 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ 1023 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ 1024 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ 1025 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ 1026 <0x00068000 0x00068000 0x001000>, /* ap 53 */ 1027 <0x00069000 0x00069000 0x001000>, /* ap 54 */ 1028 <0x00090000 0x00090000 0x002000>, /* ap 55 */ 1029 <0x00092000 0x00092000 0x001000>, /* ap 56 */ 1030 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ 1031 <0x000a5000 0x000a5000 0x001000>, 1032 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ 1033 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ 1034 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ 1035 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ 1036 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ 1037 <0x00066000 0x00066000 0x001000>, /* ap 63 */ 1038 <0x00067000 0x00067000 0x001000>, /* ap 64 */ 1039 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ 1040 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ 1041 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ 1042 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ 1043 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ 1044 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ 1045 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ 1046 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ 1047 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ 1048 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ 1049 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ 1050 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ 1051 <0x00001400 0x00001400 0x000400>, /* ap 77 */ 1052 <0x00001800 0x00001800 0x000400>, /* ap 78 */ 1053 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ 1054 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ 1055 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ 1056 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ 1057 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ 1058 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ 1059 1060 target-module@20000 { /* 0x48020000, ap 3 04.0 */ 1061 compatible = "ti,sysc-omap2", "ti,sysc"; 1062 reg = <0x20050 0x4>, 1063 <0x20054 0x4>, 1064 <0x20058 0x4>; 1065 reg-names = "rev", "sysc", "syss"; 1066 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1067 SYSC_OMAP2_SOFTRESET | 1068 SYSC_OMAP2_AUTOIDLE)>; 1069 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1070 <SYSC_IDLE_NO>, 1071 <SYSC_IDLE_SMART>, 1072 <SYSC_IDLE_SMART_WKUP>; 1073 ti,syss-mask = <1>; 1074 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1075 clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; 1076 clock-names = "fck"; 1077 #address-cells = <1>; 1078 #size-cells = <1>; 1079 ranges = <0x0 0x20000 0x1000>; 1080 1081 uart3: serial@0 { 1082 compatible = "ti,omap4-uart"; 1083 reg = <0x0 0x100>; 1084 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1085 clock-frequency = <48000000>; 1086 }; 1087 }; 1088 1089 target-module@32000 { /* 0x48032000, ap 5 3e.0 */ 1090 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1091 reg = <0x32000 0x4>, 1092 <0x32010 0x4>; 1093 reg-names = "rev", "sysc"; 1094 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1095 SYSC_OMAP4_SOFTRESET)>; 1096 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1097 <SYSC_IDLE_NO>, 1098 <SYSC_IDLE_SMART>, 1099 <SYSC_IDLE_SMART_WKUP>; 1100 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1101 clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; 1102 clock-names = "fck"; 1103 #address-cells = <1>; 1104 #size-cells = <1>; 1105 ranges = <0x0 0x32000 0x1000>; 1106 1107 timer2: timer@0 { 1108 compatible = "ti,omap5430-timer"; 1109 reg = <0x0 0x80>; 1110 clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>, 1111 <&sys_clkin>; 1112 clock-names = "fck", "timer_sys_ck"; 1113 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1114 }; 1115 }; 1116 1117 target-module@34000 { /* 0x48034000, ap 7 46.0 */ 1118 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1119 reg = <0x34000 0x4>, 1120 <0x34010 0x4>; 1121 reg-names = "rev", "sysc"; 1122 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1123 SYSC_OMAP4_SOFTRESET)>; 1124 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1125 <SYSC_IDLE_NO>, 1126 <SYSC_IDLE_SMART>, 1127 <SYSC_IDLE_SMART_WKUP>; 1128 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1129 clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; 1130 clock-names = "fck"; 1131 #address-cells = <1>; 1132 #size-cells = <1>; 1133 ranges = <0x0 0x34000 0x1000>; 1134 1135 timer3: timer@0 { 1136 compatible = "ti,omap5430-timer"; 1137 reg = <0x0 0x80>; 1138 clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>, 1139 <&sys_clkin>; 1140 clock-names = "fck", "timer_sys_ck"; 1141 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1142 }; 1143 }; 1144 1145 target-module@36000 { /* 0x48036000, ap 9 4e.0 */ 1146 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1147 reg = <0x36000 0x4>, 1148 <0x36010 0x4>; 1149 reg-names = "rev", "sysc"; 1150 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1151 SYSC_OMAP4_SOFTRESET)>; 1152 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1153 <SYSC_IDLE_NO>, 1154 <SYSC_IDLE_SMART>, 1155 <SYSC_IDLE_SMART_WKUP>; 1156 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1157 clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; 1158 clock-names = "fck"; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges = <0x0 0x36000 0x1000>; 1162 1163 timer4: timer@0 { 1164 compatible = "ti,omap5430-timer"; 1165 reg = <0x0 0x80>; 1166 clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>, 1167 <&sys_clkin>; 1168 clock-names = "fck", "timer_sys_ck"; 1169 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1170 }; 1171 }; 1172 1173 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ 1174 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1175 reg = <0x3e000 0x4>, 1176 <0x3e010 0x4>; 1177 reg-names = "rev", "sysc"; 1178 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1179 SYSC_OMAP4_SOFTRESET)>; 1180 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1181 <SYSC_IDLE_NO>, 1182 <SYSC_IDLE_SMART>, 1183 <SYSC_IDLE_SMART_WKUP>; 1184 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1185 clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; 1186 clock-names = "fck"; 1187 #address-cells = <1>; 1188 #size-cells = <1>; 1189 ranges = <0x0 0x3e000 0x1000>; 1190 1191 timer9: timer@0 { 1192 compatible = "ti,omap5430-timer"; 1193 reg = <0x0 0x80>; 1194 clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>, 1195 <&sys_clkin>; 1196 clock-names = "fck", "timer_sys_ck"; 1197 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1198 ti,timer-pwm; 1199 }; 1200 }; 1201 1202 target-module@51000 { /* 0x48051000, ap 45 2e.0 */ 1203 compatible = "ti,sysc-omap2", "ti,sysc"; 1204 reg = <0x51000 0x4>, 1205 <0x51010 0x4>, 1206 <0x51114 0x4>; 1207 reg-names = "rev", "sysc", "syss"; 1208 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1209 SYSC_OMAP2_SOFTRESET | 1210 SYSC_OMAP2_AUTOIDLE)>; 1211 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1212 <SYSC_IDLE_NO>, 1213 <SYSC_IDLE_SMART>, 1214 <SYSC_IDLE_SMART_WKUP>; 1215 ti,syss-mask = <1>; 1216 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1217 clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, 1218 <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; 1219 clock-names = "fck", "dbclk"; 1220 #address-cells = <1>; 1221 #size-cells = <1>; 1222 ranges = <0x0 0x51000 0x1000>; 1223 1224 gpio7: gpio@0 { 1225 compatible = "ti,omap4-gpio"; 1226 reg = <0x0 0x200>; 1227 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1228 gpio-controller; 1229 #gpio-cells = <2>; 1230 interrupt-controller; 1231 #interrupt-cells = <2>; 1232 }; 1233 }; 1234 1235 target-module@53000 { /* 0x48053000, ap 35 36.0 */ 1236 compatible = "ti,sysc-omap2", "ti,sysc"; 1237 reg = <0x53000 0x4>, 1238 <0x53010 0x4>, 1239 <0x53114 0x4>; 1240 reg-names = "rev", "sysc", "syss"; 1241 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1242 SYSC_OMAP2_SOFTRESET | 1243 SYSC_OMAP2_AUTOIDLE)>; 1244 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1245 <SYSC_IDLE_NO>, 1246 <SYSC_IDLE_SMART>, 1247 <SYSC_IDLE_SMART_WKUP>; 1248 ti,syss-mask = <1>; 1249 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1250 clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, 1251 <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; 1252 clock-names = "fck", "dbclk"; 1253 #address-cells = <1>; 1254 #size-cells = <1>; 1255 ranges = <0x0 0x53000 0x1000>; 1256 1257 gpio8: gpio@0 { 1258 compatible = "ti,omap4-gpio"; 1259 reg = <0x0 0x200>; 1260 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1261 gpio-controller; 1262 #gpio-cells = <2>; 1263 interrupt-controller; 1264 #interrupt-cells = <2>; 1265 }; 1266 }; 1267 1268 target-module@55000 { /* 0x48055000, ap 13 0e.0 */ 1269 compatible = "ti,sysc-omap2", "ti,sysc"; 1270 reg = <0x55000 0x4>, 1271 <0x55010 0x4>, 1272 <0x55114 0x4>; 1273 reg-names = "rev", "sysc", "syss"; 1274 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1275 SYSC_OMAP2_SOFTRESET | 1276 SYSC_OMAP2_AUTOIDLE)>; 1277 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1278 <SYSC_IDLE_NO>, 1279 <SYSC_IDLE_SMART>, 1280 <SYSC_IDLE_SMART_WKUP>; 1281 ti,syss-mask = <1>; 1282 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1283 clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, 1284 <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; 1285 clock-names = "fck", "dbclk"; 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 ranges = <0x0 0x55000 0x1000>; 1289 1290 gpio2: gpio@0 { 1291 compatible = "ti,omap4-gpio"; 1292 reg = <0x0 0x200>; 1293 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1294 gpio-controller; 1295 #gpio-cells = <2>; 1296 interrupt-controller; 1297 #interrupt-cells = <2>; 1298 }; 1299 }; 1300 1301 target-module@57000 { /* 0x48057000, ap 15 06.0 */ 1302 compatible = "ti,sysc-omap2", "ti,sysc"; 1303 reg = <0x57000 0x4>, 1304 <0x57010 0x4>, 1305 <0x57114 0x4>; 1306 reg-names = "rev", "sysc", "syss"; 1307 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1308 SYSC_OMAP2_SOFTRESET | 1309 SYSC_OMAP2_AUTOIDLE)>; 1310 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1311 <SYSC_IDLE_NO>, 1312 <SYSC_IDLE_SMART>, 1313 <SYSC_IDLE_SMART_WKUP>; 1314 ti,syss-mask = <1>; 1315 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1316 clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, 1317 <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; 1318 clock-names = "fck", "dbclk"; 1319 #address-cells = <1>; 1320 #size-cells = <1>; 1321 ranges = <0x0 0x57000 0x1000>; 1322 1323 gpio3: gpio@0 { 1324 compatible = "ti,omap4-gpio"; 1325 reg = <0x0 0x200>; 1326 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1327 gpio-controller; 1328 #gpio-cells = <2>; 1329 interrupt-controller; 1330 #interrupt-cells = <2>; 1331 }; 1332 }; 1333 1334 target-module@59000 { /* 0x48059000, ap 17 16.0 */ 1335 compatible = "ti,sysc-omap2", "ti,sysc"; 1336 reg = <0x59000 0x4>, 1337 <0x59010 0x4>, 1338 <0x59114 0x4>; 1339 reg-names = "rev", "sysc", "syss"; 1340 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1341 SYSC_OMAP2_SOFTRESET | 1342 SYSC_OMAP2_AUTOIDLE)>; 1343 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1344 <SYSC_IDLE_NO>, 1345 <SYSC_IDLE_SMART>, 1346 <SYSC_IDLE_SMART_WKUP>; 1347 ti,syss-mask = <1>; 1348 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1349 clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, 1350 <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; 1351 clock-names = "fck", "dbclk"; 1352 #address-cells = <1>; 1353 #size-cells = <1>; 1354 ranges = <0x0 0x59000 0x1000>; 1355 1356 gpio4: gpio@0 { 1357 compatible = "ti,omap4-gpio"; 1358 reg = <0x0 0x200>; 1359 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1360 gpio-controller; 1361 #gpio-cells = <2>; 1362 interrupt-controller; 1363 #interrupt-cells = <2>; 1364 }; 1365 }; 1366 1367 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ 1368 compatible = "ti,sysc-omap2", "ti,sysc"; 1369 reg = <0x5b000 0x4>, 1370 <0x5b010 0x4>, 1371 <0x5b114 0x4>; 1372 reg-names = "rev", "sysc", "syss"; 1373 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1374 SYSC_OMAP2_SOFTRESET | 1375 SYSC_OMAP2_AUTOIDLE)>; 1376 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1377 <SYSC_IDLE_NO>, 1378 <SYSC_IDLE_SMART>, 1379 <SYSC_IDLE_SMART_WKUP>; 1380 ti,syss-mask = <1>; 1381 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1382 clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, 1383 <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; 1384 clock-names = "fck", "dbclk"; 1385 #address-cells = <1>; 1386 #size-cells = <1>; 1387 ranges = <0x0 0x5b000 0x1000>; 1388 1389 gpio5: gpio@0 { 1390 compatible = "ti,omap4-gpio"; 1391 reg = <0x0 0x200>; 1392 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1393 gpio-controller; 1394 #gpio-cells = <2>; 1395 interrupt-controller; 1396 #interrupt-cells = <2>; 1397 }; 1398 }; 1399 1400 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ 1401 compatible = "ti,sysc-omap2", "ti,sysc"; 1402 reg = <0x5d000 0x4>, 1403 <0x5d010 0x4>, 1404 <0x5d114 0x4>; 1405 reg-names = "rev", "sysc", "syss"; 1406 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1407 SYSC_OMAP2_SOFTRESET | 1408 SYSC_OMAP2_AUTOIDLE)>; 1409 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1410 <SYSC_IDLE_NO>, 1411 <SYSC_IDLE_SMART>, 1412 <SYSC_IDLE_SMART_WKUP>; 1413 ti,syss-mask = <1>; 1414 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1415 clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, 1416 <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; 1417 clock-names = "fck", "dbclk"; 1418 #address-cells = <1>; 1419 #size-cells = <1>; 1420 ranges = <0x0 0x5d000 0x1000>; 1421 1422 gpio6: gpio@0 { 1423 compatible = "ti,omap4-gpio"; 1424 reg = <0x0 0x200>; 1425 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1426 gpio-controller; 1427 #gpio-cells = <2>; 1428 interrupt-controller; 1429 #interrupt-cells = <2>; 1430 }; 1431 }; 1432 1433 target-module@60000 { /* 0x48060000, ap 23 24.0 */ 1434 compatible = "ti,sysc-omap2", "ti,sysc"; 1435 reg = <0x60000 0x8>, 1436 <0x60010 0x8>, 1437 <0x60090 0x8>; 1438 reg-names = "rev", "sysc", "syss"; 1439 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1440 SYSC_OMAP2_ENAWAKEUP | 1441 SYSC_OMAP2_SOFTRESET | 1442 SYSC_OMAP2_AUTOIDLE)>; 1443 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1444 <SYSC_IDLE_NO>, 1445 <SYSC_IDLE_SMART>, 1446 <SYSC_IDLE_SMART_WKUP>; 1447 ti,syss-mask = <1>; 1448 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1449 clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; 1450 clock-names = "fck"; 1451 #address-cells = <1>; 1452 #size-cells = <1>; 1453 ranges = <0x0 0x60000 0x1000>; 1454 1455 i2c3: i2c@0 { 1456 compatible = "ti,omap4-i2c"; 1457 reg = <0x0 0x100>; 1458 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 }; 1462 }; 1463 1464 target-module@66000 { /* 0x48066000, ap 63 4c.0 */ 1465 compatible = "ti,sysc-omap2", "ti,sysc"; 1466 reg = <0x66050 0x4>, 1467 <0x66054 0x4>, 1468 <0x66058 0x4>; 1469 reg-names = "rev", "sysc", "syss"; 1470 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1471 SYSC_OMAP2_SOFTRESET | 1472 SYSC_OMAP2_AUTOIDLE)>; 1473 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1474 <SYSC_IDLE_NO>, 1475 <SYSC_IDLE_SMART>, 1476 <SYSC_IDLE_SMART_WKUP>; 1477 ti,syss-mask = <1>; 1478 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1479 clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; 1480 clock-names = "fck"; 1481 #address-cells = <1>; 1482 #size-cells = <1>; 1483 ranges = <0x0 0x66000 0x1000>; 1484 1485 uart5: serial@0 { 1486 compatible = "ti,omap4-uart"; 1487 reg = <0x0 0x100>; 1488 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1489 clock-frequency = <48000000>; 1490 }; 1491 }; 1492 1493 target-module@68000 { /* 0x48068000, ap 53 54.0 */ 1494 compatible = "ti,sysc-omap2", "ti,sysc"; 1495 reg = <0x68050 0x4>, 1496 <0x68054 0x4>, 1497 <0x68058 0x4>; 1498 reg-names = "rev", "sysc", "syss"; 1499 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1500 SYSC_OMAP2_SOFTRESET | 1501 SYSC_OMAP2_AUTOIDLE)>; 1502 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1503 <SYSC_IDLE_NO>, 1504 <SYSC_IDLE_SMART>, 1505 <SYSC_IDLE_SMART_WKUP>; 1506 ti,syss-mask = <1>; 1507 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1508 clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; 1509 clock-names = "fck"; 1510 #address-cells = <1>; 1511 #size-cells = <1>; 1512 ranges = <0x0 0x68000 0x1000>; 1513 1514 uart6: serial@0 { 1515 compatible = "ti,omap4-uart"; 1516 reg = <0x0 0x100>; 1517 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1518 clock-frequency = <48000000>; 1519 }; 1520 }; 1521 1522 target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ 1523 compatible = "ti,sysc-omap2", "ti,sysc"; 1524 reg = <0x6a050 0x4>, 1525 <0x6a054 0x4>, 1526 <0x6a058 0x4>; 1527 reg-names = "rev", "sysc", "syss"; 1528 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1529 SYSC_OMAP2_SOFTRESET | 1530 SYSC_OMAP2_AUTOIDLE)>; 1531 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1532 <SYSC_IDLE_NO>, 1533 <SYSC_IDLE_SMART>, 1534 <SYSC_IDLE_SMART_WKUP>; 1535 ti,syss-mask = <1>; 1536 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1537 clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; 1538 clock-names = "fck"; 1539 #address-cells = <1>; 1540 #size-cells = <1>; 1541 ranges = <0x0 0x6a000 0x1000>; 1542 1543 uart1: serial@0 { 1544 compatible = "ti,omap4-uart"; 1545 reg = <0x0 0x100>; 1546 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1547 clock-frequency = <48000000>; 1548 }; 1549 }; 1550 1551 target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ 1552 compatible = "ti,sysc-omap2", "ti,sysc"; 1553 reg = <0x6c050 0x4>, 1554 <0x6c054 0x4>, 1555 <0x6c058 0x4>; 1556 reg-names = "rev", "sysc", "syss"; 1557 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1558 SYSC_OMAP2_SOFTRESET | 1559 SYSC_OMAP2_AUTOIDLE)>; 1560 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1561 <SYSC_IDLE_NO>, 1562 <SYSC_IDLE_SMART>, 1563 <SYSC_IDLE_SMART_WKUP>; 1564 ti,syss-mask = <1>; 1565 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1566 clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; 1567 clock-names = "fck"; 1568 #address-cells = <1>; 1569 #size-cells = <1>; 1570 ranges = <0x0 0x6c000 0x1000>; 1571 1572 uart2: serial@0 { 1573 compatible = "ti,omap4-uart"; 1574 reg = <0x0 0x100>; 1575 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1576 clock-frequency = <48000000>; 1577 }; 1578 }; 1579 1580 target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ 1581 compatible = "ti,sysc-omap2", "ti,sysc"; 1582 reg = <0x6e050 0x4>, 1583 <0x6e054 0x4>, 1584 <0x6e058 0x4>; 1585 reg-names = "rev", "sysc", "syss"; 1586 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1587 SYSC_OMAP2_SOFTRESET | 1588 SYSC_OMAP2_AUTOIDLE)>; 1589 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1590 <SYSC_IDLE_NO>, 1591 <SYSC_IDLE_SMART>, 1592 <SYSC_IDLE_SMART_WKUP>; 1593 ti,syss-mask = <1>; 1594 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1595 clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; 1596 clock-names = "fck"; 1597 #address-cells = <1>; 1598 #size-cells = <1>; 1599 ranges = <0x0 0x6e000 0x1000>; 1600 1601 uart4: serial@0 { 1602 compatible = "ti,omap4-uart"; 1603 reg = <0x0 0x100>; 1604 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1605 clock-frequency = <48000000>; 1606 }; 1607 }; 1608 1609 target-module@70000 { /* 0x48070000, ap 30 14.0 */ 1610 compatible = "ti,sysc-omap2", "ti,sysc"; 1611 reg = <0x70000 0x8>, 1612 <0x70010 0x8>, 1613 <0x70090 0x8>; 1614 reg-names = "rev", "sysc", "syss"; 1615 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1616 SYSC_OMAP2_ENAWAKEUP | 1617 SYSC_OMAP2_SOFTRESET | 1618 SYSC_OMAP2_AUTOIDLE)>; 1619 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1620 <SYSC_IDLE_NO>, 1621 <SYSC_IDLE_SMART>, 1622 <SYSC_IDLE_SMART_WKUP>; 1623 ti,syss-mask = <1>; 1624 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1625 clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; 1626 clock-names = "fck"; 1627 #address-cells = <1>; 1628 #size-cells = <1>; 1629 ranges = <0x0 0x70000 0x1000>; 1630 1631 i2c1: i2c@0 { 1632 compatible = "ti,omap4-i2c"; 1633 reg = <0x0 0x100>; 1634 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 }; 1638 }; 1639 1640 target-module@72000 { /* 0x48072000, ap 32 1c.0 */ 1641 compatible = "ti,sysc-omap2", "ti,sysc"; 1642 reg = <0x72000 0x8>, 1643 <0x72010 0x8>, 1644 <0x72090 0x8>; 1645 reg-names = "rev", "sysc", "syss"; 1646 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1647 SYSC_OMAP2_ENAWAKEUP | 1648 SYSC_OMAP2_SOFTRESET | 1649 SYSC_OMAP2_AUTOIDLE)>; 1650 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1651 <SYSC_IDLE_NO>, 1652 <SYSC_IDLE_SMART>, 1653 <SYSC_IDLE_SMART_WKUP>; 1654 ti,syss-mask = <1>; 1655 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1656 clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; 1657 clock-names = "fck"; 1658 #address-cells = <1>; 1659 #size-cells = <1>; 1660 ranges = <0x0 0x72000 0x1000>; 1661 1662 i2c2: i2c@0 { 1663 compatible = "ti,omap4-i2c"; 1664 reg = <0x0 0x100>; 1665 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 }; 1669 }; 1670 1671 target-module@78000 { /* 0x48078000, ap 39 12.0 */ 1672 compatible = "ti,sysc"; 1673 status = "disabled"; 1674 #address-cells = <1>; 1675 #size-cells = <1>; 1676 ranges = <0x0 0x78000 0x1000>; 1677 }; 1678 1679 target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ 1680 compatible = "ti,sysc-omap2", "ti,sysc"; 1681 reg = <0x7a000 0x8>, 1682 <0x7a010 0x8>, 1683 <0x7a090 0x8>; 1684 reg-names = "rev", "sysc", "syss"; 1685 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1686 SYSC_OMAP2_ENAWAKEUP | 1687 SYSC_OMAP2_SOFTRESET | 1688 SYSC_OMAP2_AUTOIDLE)>; 1689 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1690 <SYSC_IDLE_NO>, 1691 <SYSC_IDLE_SMART>, 1692 <SYSC_IDLE_SMART_WKUP>; 1693 ti,syss-mask = <1>; 1694 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1695 clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; 1696 clock-names = "fck"; 1697 #address-cells = <1>; 1698 #size-cells = <1>; 1699 ranges = <0x0 0x7a000 0x1000>; 1700 1701 i2c4: i2c@0 { 1702 compatible = "ti,omap4-i2c"; 1703 reg = <0x0 0x100>; 1704 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 }; 1708 }; 1709 1710 target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ 1711 compatible = "ti,sysc-omap2", "ti,sysc"; 1712 reg = <0x7c000 0x8>, 1713 <0x7c010 0x8>, 1714 <0x7c090 0x8>; 1715 reg-names = "rev", "sysc", "syss"; 1716 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1717 SYSC_OMAP2_ENAWAKEUP | 1718 SYSC_OMAP2_SOFTRESET | 1719 SYSC_OMAP2_AUTOIDLE)>; 1720 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1721 <SYSC_IDLE_NO>, 1722 <SYSC_IDLE_SMART>, 1723 <SYSC_IDLE_SMART_WKUP>; 1724 ti,syss-mask = <1>; 1725 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1726 clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; 1727 clock-names = "fck"; 1728 #address-cells = <1>; 1729 #size-cells = <1>; 1730 ranges = <0x0 0x7c000 0x1000>; 1731 1732 i2c5: i2c@0 { 1733 compatible = "ti,omap4-i2c"; 1734 reg = <0x0 0x100>; 1735 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 }; 1739 }; 1740 1741 target-module@86000 { /* 0x48086000, ap 41 5e.0 */ 1742 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1743 reg = <0x86000 0x4>, 1744 <0x86010 0x4>; 1745 reg-names = "rev", "sysc"; 1746 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1747 SYSC_OMAP4_SOFTRESET)>; 1748 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1749 <SYSC_IDLE_NO>, 1750 <SYSC_IDLE_SMART>, 1751 <SYSC_IDLE_SMART_WKUP>; 1752 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1753 clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; 1754 clock-names = "fck"; 1755 #address-cells = <1>; 1756 #size-cells = <1>; 1757 ranges = <0x0 0x86000 0x1000>; 1758 1759 timer10: timer@0 { 1760 compatible = "ti,omap5430-timer"; 1761 reg = <0x0 0x80>; 1762 clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>, 1763 <&sys_clkin>; 1764 clock-names = "fck", "timer_sys_ck"; 1765 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1766 ti,timer-pwm; 1767 }; 1768 }; 1769 1770 target-module@88000 { /* 0x48088000, ap 43 66.0 */ 1771 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1772 reg = <0x88000 0x4>, 1773 <0x88010 0x4>; 1774 reg-names = "rev", "sysc"; 1775 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1776 SYSC_OMAP4_SOFTRESET)>; 1777 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1778 <SYSC_IDLE_NO>, 1779 <SYSC_IDLE_SMART>, 1780 <SYSC_IDLE_SMART_WKUP>; 1781 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1782 clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; 1783 clock-names = "fck"; 1784 #address-cells = <1>; 1785 #size-cells = <1>; 1786 ranges = <0x0 0x88000 0x1000>; 1787 1788 timer11: timer@0 { 1789 compatible = "ti,omap5430-timer"; 1790 reg = <0x0 0x80>; 1791 clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>, 1792 <&sys_clkin>; 1793 clock-names = "fck", "timer_sys_ck"; 1794 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1795 ti,timer-pwm; 1796 }; 1797 }; 1798 1799 rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ 1800 compatible = "ti,sysc-omap2", "ti,sysc"; 1801 reg = <0x91fe0 0x4>, 1802 <0x91fe4 0x4>; 1803 reg-names = "rev", "sysc"; 1804 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 1805 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1806 <SYSC_IDLE_NO>; 1807 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1808 clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; 1809 clock-names = "fck"; 1810 #address-cells = <1>; 1811 #size-cells = <1>; 1812 ranges = <0x0 0x90000 0x2000>; 1813 1814 rng: rng@0 { 1815 compatible = "ti,omap4-rng"; 1816 reg = <0x0 0x2000>; 1817 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1818 }; 1819 }; 1820 1821 target-module@98000 { /* 0x48098000, ap 47 08.0 */ 1822 compatible = "ti,sysc-omap4", "ti,sysc"; 1823 reg = <0x98000 0x4>, 1824 <0x98010 0x4>; 1825 reg-names = "rev", "sysc"; 1826 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1827 SYSC_OMAP4_SOFTRESET)>; 1828 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1829 <SYSC_IDLE_NO>, 1830 <SYSC_IDLE_SMART>, 1831 <SYSC_IDLE_SMART_WKUP>; 1832 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1833 clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; 1834 clock-names = "fck"; 1835 #address-cells = <1>; 1836 #size-cells = <1>; 1837 ranges = <0x0 0x98000 0x1000>; 1838 1839 mcspi1: spi@0 { 1840 compatible = "ti,omap4-mcspi"; 1841 reg = <0x0 0x200>; 1842 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 ti,spi-num-cs = <4>; 1846 dmas = <&sdma 35>, 1847 <&sdma 36>, 1848 <&sdma 37>, 1849 <&sdma 38>, 1850 <&sdma 39>, 1851 <&sdma 40>, 1852 <&sdma 41>, 1853 <&sdma 42>; 1854 dma-names = "tx0", "rx0", "tx1", "rx1", 1855 "tx2", "rx2", "tx3", "rx3"; 1856 }; 1857 }; 1858 1859 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ 1860 compatible = "ti,sysc-omap4", "ti,sysc"; 1861 reg = <0x9a000 0x4>, 1862 <0x9a010 0x4>; 1863 reg-names = "rev", "sysc"; 1864 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1865 SYSC_OMAP4_SOFTRESET)>; 1866 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1867 <SYSC_IDLE_NO>, 1868 <SYSC_IDLE_SMART>, 1869 <SYSC_IDLE_SMART_WKUP>; 1870 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1871 clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; 1872 clock-names = "fck"; 1873 #address-cells = <1>; 1874 #size-cells = <1>; 1875 ranges = <0x0 0x9a000 0x1000>; 1876 1877 mcspi2: spi@0 { 1878 compatible = "ti,omap4-mcspi"; 1879 reg = <0x0 0x200>; 1880 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1881 #address-cells = <1>; 1882 #size-cells = <0>; 1883 ti,spi-num-cs = <2>; 1884 dmas = <&sdma 43>, 1885 <&sdma 44>, 1886 <&sdma 45>, 1887 <&sdma 46>; 1888 dma-names = "tx0", "rx0", "tx1", "rx1"; 1889 }; 1890 }; 1891 1892 target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ 1893 compatible = "ti,sysc-omap4", "ti,sysc"; 1894 reg = <0x9c000 0x4>, 1895 <0x9c010 0x4>; 1896 reg-names = "rev", "sysc"; 1897 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1898 SYSC_OMAP4_SOFTRESET)>; 1899 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1900 <SYSC_IDLE_NO>, 1901 <SYSC_IDLE_SMART>, 1902 <SYSC_IDLE_SMART_WKUP>; 1903 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1904 <SYSC_IDLE_NO>, 1905 <SYSC_IDLE_SMART>, 1906 <SYSC_IDLE_SMART_WKUP>; 1907 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 1908 clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; 1909 clock-names = "fck"; 1910 #address-cells = <1>; 1911 #size-cells = <1>; 1912 ranges = <0x0 0x9c000 0x1000>; 1913 1914 mmc1: mmc@0 { 1915 compatible = "ti,omap4-hsmmc"; 1916 reg = <0x0 0x400>; 1917 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1918 ti,dual-volt; 1919 ti,needs-special-reset; 1920 dmas = <&sdma 61>, <&sdma 62>; 1921 dma-names = "tx", "rx"; 1922 pbias-supply = <&pbias_mmc_reg>; 1923 }; 1924 }; 1925 1926 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ 1927 compatible = "ti,sysc"; 1928 status = "disabled"; 1929 #address-cells = <1>; 1930 #size-cells = <1>; 1931 ranges = <0x0 0xa2000 0x1000>; 1932 }; 1933 1934 target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ 1935 compatible = "ti,sysc"; 1936 status = "disabled"; 1937 #address-cells = <1>; 1938 #size-cells = <1>; 1939 ranges = <0x00000000 0x000a4000 0x00001000>, 1940 <0x00001000 0x000a5000 0x00001000>; 1941 }; 1942 1943 des_target: target-module@a5000 { /* 0x480a5000 */ 1944 compatible = "ti,sysc-omap2", "ti,sysc"; 1945 reg = <0xa5030 0x4>, 1946 <0xa5034 0x4>, 1947 <0xa5038 0x4>; 1948 reg-names = "rev", "sysc", "syss"; 1949 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1950 SYSC_OMAP2_AUTOIDLE)>; 1951 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1952 <SYSC_IDLE_NO>, 1953 <SYSC_IDLE_SMART>, 1954 <SYSC_IDLE_SMART_WKUP>; 1955 ti,syss-mask = <1>; 1956 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1957 clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; 1958 clock-names = "fck"; 1959 #address-cells = <1>; 1960 #size-cells = <1>; 1961 ranges = <0 0xa5000 0x00001000>; 1962 status = "disabled"; 1963 1964 des: des@0 { 1965 compatible = "ti,omap4-des"; 1966 reg = <0 0xa0>; 1967 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1968 dmas = <&sdma 117>, <&sdma 116>; 1969 dma-names = "tx", "rx"; 1970 }; 1971 }; 1972 1973 target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ 1974 compatible = "ti,sysc"; 1975 status = "disabled"; 1976 #address-cells = <1>; 1977 #size-cells = <1>; 1978 ranges = <0x0 0xa8000 0x4000>; 1979 }; 1980 1981 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ 1982 compatible = "ti,sysc-omap4", "ti,sysc"; 1983 reg = <0xad000 0x4>, 1984 <0xad010 0x4>; 1985 reg-names = "rev", "sysc"; 1986 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1987 SYSC_OMAP4_SOFTRESET)>; 1988 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1989 <SYSC_IDLE_NO>, 1990 <SYSC_IDLE_SMART>, 1991 <SYSC_IDLE_SMART_WKUP>; 1992 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1993 <SYSC_IDLE_NO>, 1994 <SYSC_IDLE_SMART>, 1995 <SYSC_IDLE_SMART_WKUP>; 1996 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 1997 clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; 1998 clock-names = "fck"; 1999 #address-cells = <1>; 2000 #size-cells = <1>; 2001 ranges = <0x0 0xad000 0x1000>; 2002 2003 mmc3: mmc@0 { 2004 compatible = "ti,omap4-hsmmc"; 2005 reg = <0x0 0x400>; 2006 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2007 ti,needs-special-reset; 2008 dmas = <&sdma 77>, <&sdma 78>; 2009 dma-names = "tx", "rx"; 2010 }; 2011 }; 2012 2013 target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ 2014 compatible = "ti,sysc"; 2015 status = "disabled"; 2016 #address-cells = <1>; 2017 #size-cells = <1>; 2018 ranges = <0x0 0xb2000 0x1000>; 2019 }; 2020 2021 target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ 2022 compatible = "ti,sysc-omap4", "ti,sysc"; 2023 reg = <0xb4000 0x4>, 2024 <0xb4010 0x4>; 2025 reg-names = "rev", "sysc"; 2026 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2027 SYSC_OMAP4_SOFTRESET)>; 2028 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2029 <SYSC_IDLE_NO>, 2030 <SYSC_IDLE_SMART>, 2031 <SYSC_IDLE_SMART_WKUP>; 2032 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2033 <SYSC_IDLE_NO>, 2034 <SYSC_IDLE_SMART>, 2035 <SYSC_IDLE_SMART_WKUP>; 2036 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 2037 clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; 2038 clock-names = "fck"; 2039 #address-cells = <1>; 2040 #size-cells = <1>; 2041 ranges = <0x0 0xb4000 0x1000>; 2042 2043 mmc2: mmc@0 { 2044 compatible = "ti,omap4-hsmmc"; 2045 reg = <0x0 0x400>; 2046 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2047 ti,needs-special-reset; 2048 dmas = <&sdma 47>, <&sdma 48>; 2049 dma-names = "tx", "rx"; 2050 }; 2051 }; 2052 2053 target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ 2054 compatible = "ti,sysc-omap4", "ti,sysc"; 2055 reg = <0xb8000 0x4>, 2056 <0xb8010 0x4>; 2057 reg-names = "rev", "sysc"; 2058 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2059 SYSC_OMAP4_SOFTRESET)>; 2060 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2061 <SYSC_IDLE_NO>, 2062 <SYSC_IDLE_SMART>, 2063 <SYSC_IDLE_SMART_WKUP>; 2064 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 2065 clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; 2066 clock-names = "fck"; 2067 #address-cells = <1>; 2068 #size-cells = <1>; 2069 ranges = <0x0 0xb8000 0x1000>; 2070 2071 mcspi3: spi@0 { 2072 compatible = "ti,omap4-mcspi"; 2073 reg = <0x0 0x200>; 2074 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2075 #address-cells = <1>; 2076 #size-cells = <0>; 2077 ti,spi-num-cs = <2>; 2078 dmas = <&sdma 15>, <&sdma 16>; 2079 dma-names = "tx0", "rx0"; 2080 }; 2081 }; 2082 2083 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ 2084 compatible = "ti,sysc-omap4", "ti,sysc"; 2085 reg = <0xba000 0x4>, 2086 <0xba010 0x4>; 2087 reg-names = "rev", "sysc"; 2088 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2089 SYSC_OMAP4_SOFTRESET)>; 2090 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2091 <SYSC_IDLE_NO>, 2092 <SYSC_IDLE_SMART>, 2093 <SYSC_IDLE_SMART_WKUP>; 2094 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 2095 clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; 2096 clock-names = "fck"; 2097 #address-cells = <1>; 2098 #size-cells = <1>; 2099 ranges = <0x0 0xba000 0x1000>; 2100 2101 mcspi4: spi@0 { 2102 compatible = "ti,omap4-mcspi"; 2103 reg = <0x0 0x200>; 2104 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 ti,spi-num-cs = <1>; 2108 dmas = <&sdma 70>, <&sdma 71>; 2109 dma-names = "tx0", "rx0"; 2110 }; 2111 }; 2112 2113 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ 2114 compatible = "ti,sysc-omap4", "ti,sysc"; 2115 reg = <0xd1000 0x4>, 2116 <0xd1010 0x4>; 2117 reg-names = "rev", "sysc"; 2118 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2119 SYSC_OMAP4_SOFTRESET)>; 2120 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2121 <SYSC_IDLE_NO>, 2122 <SYSC_IDLE_SMART>, 2123 <SYSC_IDLE_SMART_WKUP>; 2124 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2125 <SYSC_IDLE_NO>, 2126 <SYSC_IDLE_SMART>, 2127 <SYSC_IDLE_SMART_WKUP>; 2128 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 2129 clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; 2130 clock-names = "fck"; 2131 #address-cells = <1>; 2132 #size-cells = <1>; 2133 ranges = <0x0 0xd1000 0x1000>; 2134 2135 mmc4: mmc@0 { 2136 compatible = "ti,omap4-hsmmc"; 2137 reg = <0x0 0x400>; 2138 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2139 ti,needs-special-reset; 2140 dmas = <&sdma 57>, <&sdma 58>; 2141 dma-names = "tx", "rx"; 2142 }; 2143 }; 2144 2145 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ 2146 compatible = "ti,sysc-omap4", "ti,sysc"; 2147 reg = <0xd5000 0x4>, 2148 <0xd5010 0x4>; 2149 reg-names = "rev", "sysc"; 2150 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2151 SYSC_OMAP4_SOFTRESET)>; 2152 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2153 <SYSC_IDLE_NO>, 2154 <SYSC_IDLE_SMART>, 2155 <SYSC_IDLE_SMART_WKUP>; 2156 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2157 <SYSC_IDLE_NO>, 2158 <SYSC_IDLE_SMART>, 2159 <SYSC_IDLE_SMART_WKUP>; 2160 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ 2161 clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; 2162 clock-names = "fck"; 2163 #address-cells = <1>; 2164 #size-cells = <1>; 2165 ranges = <0x0 0xd5000 0x1000>; 2166 2167 mmc5: mmc@0 { 2168 compatible = "ti,omap4-hsmmc"; 2169 reg = <0x0 0x400>; 2170 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2171 ti,needs-special-reset; 2172 dmas = <&sdma 59>, <&sdma 60>; 2173 dma-names = "tx", "rx"; 2174 }; 2175 }; 2176 }; 2177 2178 segment@200000 { /* 0x48200000 */ 2179 compatible = "simple-pm-bus"; 2180 #address-cells = <1>; 2181 #size-cells = <1>; 2182 }; 2183}; 2184 2185&l4_wkup { /* 0x4ae00000 */ 2186 compatible = "ti,omap5-l4-wkup", "simple-pm-bus"; 2187 power-domains = <&prm_wkupaon>; 2188 clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>; 2189 clock-names = "fck"; 2190 reg = <0x4ae00000 0x800>, 2191 <0x4ae00800 0x800>, 2192 <0x4ae01000 0x1000>; 2193 reg-names = "ap", "la", "ia0"; 2194 #address-cells = <1>; 2195 #size-cells = <1>; 2196 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ 2197 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ 2198 <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ 2199 2200 segment@0 { /* 0x4ae00000 */ 2201 compatible = "simple-pm-bus"; 2202 #address-cells = <1>; 2203 #size-cells = <1>; 2204 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 2205 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 2206 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 2207 <0x00006000 0x00006000 0x002000>, /* ap 3 */ 2208 <0x00008000 0x00008000 0x001000>, /* ap 4 */ 2209 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ 2210 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ 2211 <0x00004000 0x00004000 0x001000>, /* ap 17 */ 2212 <0x00005000 0x00005000 0x001000>, /* ap 18 */ 2213 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ 2214 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ 2215 2216 target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ 2217 compatible = "ti,sysc-omap2", "ti,sysc"; 2218 reg = <0x4000 0x4>, 2219 <0x4010 0x4>; 2220 reg-names = "rev", "sysc"; 2221 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2222 <SYSC_IDLE_NO>; 2223 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ 2224 clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; 2225 clock-names = "fck"; 2226 #address-cells = <1>; 2227 #size-cells = <1>; 2228 ranges = <0x0 0x4000 0x1000>; 2229 2230 counter32k: counter@0 { 2231 compatible = "ti,omap-counter32k"; 2232 reg = <0x0 0x40>; 2233 }; 2234 }; 2235 2236 target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ 2237 compatible = "ti,sysc-omap4", "ti,sysc"; 2238 reg = <0x6000 0x4>; 2239 reg-names = "rev"; 2240 #address-cells = <1>; 2241 #size-cells = <1>; 2242 ranges = <0x0 0x6000 0x2000>; 2243 2244 prm: prm@0 { 2245 compatible = "ti,omap5-prm", "simple-bus"; 2246 reg = <0x0 0x2000>; 2247 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2248 #address-cells = <1>; 2249 #size-cells = <1>; 2250 ranges = <0 0 0x2000>; 2251 2252 prm_clocks: clocks { 2253 #address-cells = <1>; 2254 #size-cells = <0>; 2255 }; 2256 2257 prm_clockdomains: clockdomains { 2258 }; 2259 }; 2260 }; 2261 2262 target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ 2263 compatible = "ti,sysc-omap4", "ti,sysc"; 2264 reg = <0xa000 0x4>; 2265 reg-names = "rev"; 2266 #address-cells = <1>; 2267 #size-cells = <1>; 2268 ranges = <0x0 0xa000 0x1000>; 2269 2270 scrm: scrm@0 { 2271 compatible = "ti,omap5-scrm"; 2272 reg = <0x0 0x1000>; 2273 2274 scrm_clocks: clocks { 2275 #address-cells = <1>; 2276 #size-cells = <0>; 2277 }; 2278 2279 scrm_clockdomains: clockdomains { 2280 }; 2281 }; 2282 }; 2283 2284 target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ 2285 compatible = "ti,sysc-omap4", "ti,sysc"; 2286 reg = <0xc000 0x4>; 2287 reg-names = "rev"; 2288 #address-cells = <1>; 2289 #size-cells = <1>; 2290 ranges = <0x0 0xc000 0x1000>; 2291 2292 omap5_pmx_wkup: pinmux@840 { 2293 compatible = "ti,omap5-padconf", 2294 "pinctrl-single"; 2295 reg = <0x840 0x003c>; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 #pinctrl-cells = <1>; 2299 #interrupt-cells = <1>; 2300 interrupt-controller; 2301 pinctrl-single,register-width = <16>; 2302 pinctrl-single,function-mask = <0x7fff>; 2303 }; 2304 2305 omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { 2306 compatible = "ti,omap5-scm-wkup-pad-conf", 2307 "simple-bus"; 2308 reg = <0xda0 0x60>; 2309 #address-cells = <1>; 2310 #size-cells = <1>; 2311 ranges = <0 0 0x60>; 2312 2313 scm_wkup_pad_conf: scm_conf@0 { 2314 compatible = "syscon", "simple-bus"; 2315 reg = <0x0 0x60>; 2316 #address-cells = <1>; 2317 #size-cells = <1>; 2318 ranges = <0 0x0 0x60>; 2319 2320 scm_wkup_pad_conf_clocks: clocks@0 { 2321 #address-cells = <1>; 2322 #size-cells = <0>; 2323 }; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 segment@10000 { /* 0x4ae10000 */ 2330 compatible = "simple-pm-bus"; 2331 #address-cells = <1>; 2332 #size-cells = <1>; 2333 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ 2334 <0x00001000 0x00011000 0x001000>, /* ap 6 */ 2335 <0x00004000 0x00014000 0x001000>, /* ap 7 */ 2336 <0x00005000 0x00015000 0x001000>, /* ap 8 */ 2337 <0x00008000 0x00018000 0x001000>, /* ap 9 */ 2338 <0x00009000 0x00019000 0x001000>, /* ap 10 */ 2339 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ 2340 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ 2341 2342 target-module@0 { /* 0x4ae10000, ap 5 10.0 */ 2343 compatible = "ti,sysc-omap2", "ti,sysc"; 2344 reg = <0x0 0x4>, 2345 <0x10 0x4>, 2346 <0x114 0x4>; 2347 reg-names = "rev", "sysc", "syss"; 2348 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2349 SYSC_OMAP2_SOFTRESET | 2350 SYSC_OMAP2_AUTOIDLE)>; 2351 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2352 <SYSC_IDLE_NO>, 2353 <SYSC_IDLE_SMART>, 2354 <SYSC_IDLE_SMART_WKUP>; 2355 ti,syss-mask = <1>; 2356 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ 2357 clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, 2358 <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; 2359 clock-names = "fck", "dbclk"; 2360 #address-cells = <1>; 2361 #size-cells = <1>; 2362 ranges = <0x0 0x0 0x1000>; 2363 2364 gpio1: gpio@0 { 2365 compatible = "ti,omap4-gpio"; 2366 reg = <0x0 0x200>; 2367 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 2368 ti,gpio-always-on; 2369 gpio-controller; 2370 #gpio-cells = <2>; 2371 interrupt-controller; 2372 #interrupt-cells = <2>; 2373 }; 2374 }; 2375 2376 target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ 2377 compatible = "ti,sysc-omap2", "ti,sysc"; 2378 reg = <0x4000 0x4>, 2379 <0x4010 0x4>, 2380 <0x4014 0x4>; 2381 reg-names = "rev", "sysc", "syss"; 2382 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 2383 SYSC_OMAP2_SOFTRESET)>; 2384 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2385 <SYSC_IDLE_NO>, 2386 <SYSC_IDLE_SMART>, 2387 <SYSC_IDLE_SMART_WKUP>; 2388 ti,syss-mask = <1>; 2389 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ 2390 clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; 2391 clock-names = "fck"; 2392 #address-cells = <1>; 2393 #size-cells = <1>; 2394 ranges = <0x0 0x4000 0x1000>; 2395 2396 wdt2: wdt@0 { 2397 compatible = "ti,omap5-wdt", "ti,omap3-wdt"; 2398 reg = <0x0 0x80>; 2399 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2400 }; 2401 }; 2402 2403 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ 2404 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 2405 reg = <0x8000 0x4>, 2406 <0x8010 0x4>; 2407 reg-names = "rev", "sysc"; 2408 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2409 SYSC_OMAP4_SOFTRESET)>; 2410 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2411 <SYSC_IDLE_NO>, 2412 <SYSC_IDLE_SMART>, 2413 <SYSC_IDLE_SMART_WKUP>; 2414 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ 2415 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; 2416 clock-names = "fck"; 2417 #address-cells = <1>; 2418 #size-cells = <1>; 2419 ranges = <0x0 0x8000 0x1000>; 2420 2421 timer1: timer@0 { 2422 compatible = "ti,omap5430-timer"; 2423 reg = <0x0 0x80>; 2424 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>, 2425 <&sys_clkin>; 2426 clock-names = "fck", "timer_sys_ck"; 2427 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2428 ti,timer-alwon; 2429 }; 2430 }; 2431 2432 target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ 2433 compatible = "ti,sysc-omap2", "ti,sysc"; 2434 reg = <0xc000 0x4>, 2435 <0xc010 0x4>; 2436 reg-names = "rev", "sysc"; 2437 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 2438 SYSC_OMAP2_SOFTRESET)>; 2439 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2440 <SYSC_IDLE_NO>, 2441 <SYSC_IDLE_SMART>; 2442 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ 2443 clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; 2444 clock-names = "fck"; 2445 #address-cells = <1>; 2446 #size-cells = <1>; 2447 ranges = <0x0 0xc000 0x1000>; 2448 2449 keypad: keypad@0 { 2450 compatible = "ti,omap4-keypad"; 2451 reg = <0x0 0x400>; 2452 }; 2453 }; 2454 }; 2455 2456 segment@20000 { /* 0x4ae20000 */ 2457 compatible = "simple-pm-bus"; 2458 #address-cells = <1>; 2459 #size-cells = <1>; 2460 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ 2461 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ 2462 <0x00000000 0x00020000 0x001000>, /* ap 21 */ 2463 <0x00001000 0x00021000 0x001000>, /* ap 22 */ 2464 <0x00002000 0x00022000 0x001000>, /* ap 23 */ 2465 <0x00003000 0x00023000 0x001000>, /* ap 24 */ 2466 <0x00007000 0x00027000 0x000400>, /* ap 25 */ 2467 <0x00008000 0x00028000 0x000800>, /* ap 26 */ 2468 <0x00009000 0x00029000 0x000100>, /* ap 27 */ 2469 <0x00008800 0x00028800 0x000200>, /* ap 28 */ 2470 <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ 2471 2472 target-module@0 { /* 0x4ae20000, ap 21 04.0 */ 2473 compatible = "ti,sysc"; 2474 status = "disabled"; 2475 #address-cells = <1>; 2476 #size-cells = <1>; 2477 ranges = <0x0 0x0 0x1000>; 2478 }; 2479 2480 target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ 2481 compatible = "ti,sysc"; 2482 status = "disabled"; 2483 #address-cells = <1>; 2484 #size-cells = <1>; 2485 ranges = <0x0 0x2000 0x1000>; 2486 }; 2487 2488 target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ 2489 compatible = "ti,sysc"; 2490 status = "disabled"; 2491 #address-cells = <1>; 2492 #size-cells = <1>; 2493 ranges = <0x00000000 0x00006000 0x00001000>, 2494 <0x00001000 0x00007000 0x00000400>, 2495 <0x00002000 0x00008000 0x00000800>, 2496 <0x00002800 0x00008800 0x00000200>, 2497 <0x00002a00 0x00008a00 0x00000100>, 2498 <0x00003000 0x00009000 0x00000100>; 2499 }; 2500 }; 2501}; 2502 2503