1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 6#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm IPQ8064"; 16 compatible = "qcom,ipq8064"; 17 interrupt-parent = <&intc>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "qcom,krait"; 25 enable-method = "qcom,kpss-acc-v1"; 26 device_type = "cpu"; 27 reg = <0>; 28 next-level-cache = <&L2>; 29 qcom,acc = <&acc0>; 30 qcom,saw = <&saw0>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "qcom,krait"; 35 enable-method = "qcom,kpss-acc-v1"; 36 device_type = "cpu"; 37 reg = <1>; 38 next-level-cache = <&L2>; 39 qcom,acc = <&acc1>; 40 qcom,saw = <&saw1>; 41 }; 42 43 L2: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x0 0x0>; 52 }; 53 54 cpu-pmu { 55 compatible = "qcom,krait-pmu"; 56 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 57 IRQ_TYPE_LEVEL_HIGH)>; 58 }; 59 60 reserved-memory { 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 65 nss@40000000 { 66 reg = <0x40000000 0x1000000>; 67 no-map; 68 }; 69 70 smem: smem@41000000 { 71 reg = <0x41000000 0x200000>; 72 no-map; 73 }; 74 }; 75 76 clocks { 77 cxo_board { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <25000000>; 81 }; 82 83 pxo_board { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <25000000>; 87 }; 88 89 sleep_clk: sleep_clk { 90 compatible = "fixed-clock"; 91 clock-frequency = <32768>; 92 #clock-cells = <0>; 93 }; 94 }; 95 96 firmware { 97 scm { 98 compatible = "qcom,scm-ipq806x", "qcom,scm"; 99 }; 100 }; 101 102 soc: soc { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 ranges; 106 compatible = "simple-bus"; 107 108 lpass@28100000 { 109 compatible = "qcom,lpass-cpu"; 110 status = "disabled"; 111 clocks = <&lcc AHBIX_CLK>, 112 <&lcc MI2S_OSR_CLK>, 113 <&lcc MI2S_BIT_CLK>; 114 clock-names = "ahbix-clk", 115 "mi2s-osr-clk", 116 "mi2s-bit-clk"; 117 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 118 interrupt-names = "lpass-irq-lpaif"; 119 reg = <0x28100000 0x10000>; 120 reg-names = "lpass-lpaif"; 121 }; 122 123 qcom_pinmux: pinmux@800000 { 124 compatible = "qcom,ipq8064-pinctrl"; 125 reg = <0x800000 0x4000>; 126 127 gpio-controller; 128 gpio-ranges = <&qcom_pinmux 0 0 69>; 129 #gpio-cells = <2>; 130 interrupt-controller; 131 #interrupt-cells = <2>; 132 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 133 134 pcie0_pins: pcie0_pinmux { 135 mux { 136 pins = "gpio3"; 137 function = "pcie1_rst"; 138 drive-strength = <12>; 139 bias-disable; 140 }; 141 }; 142 143 pcie1_pins: pcie1_pinmux { 144 mux { 145 pins = "gpio48"; 146 function = "pcie2_rst"; 147 drive-strength = <12>; 148 bias-disable; 149 }; 150 }; 151 152 pcie2_pins: pcie2_pinmux { 153 mux { 154 pins = "gpio63"; 155 function = "pcie3_rst"; 156 drive-strength = <12>; 157 bias-disable; 158 }; 159 }; 160 161 spi_pins: spi_pins { 162 mux { 163 pins = "gpio18", "gpio19", "gpio21"; 164 function = "gsbi5"; 165 drive-strength = <10>; 166 bias-none; 167 }; 168 }; 169 170 leds_pins: leds_pins { 171 mux { 172 pins = "gpio7", "gpio8", "gpio9", 173 "gpio26", "gpio53"; 174 function = "gpio"; 175 drive-strength = <2>; 176 bias-pull-down; 177 output-low; 178 }; 179 }; 180 181 buttons_pins: buttons_pins { 182 mux { 183 pins = "gpio54"; 184 drive-strength = <2>; 185 bias-pull-up; 186 }; 187 }; 188 }; 189 190 intc: interrupt-controller@2000000 { 191 compatible = "qcom,msm-qgic2"; 192 interrupt-controller; 193 #interrupt-cells = <3>; 194 reg = <0x02000000 0x1000>, 195 <0x02002000 0x1000>; 196 }; 197 198 timer@200a000 { 199 compatible = "qcom,kpss-timer", 200 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; 201 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 202 IRQ_TYPE_EDGE_RISING)>, 203 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 204 IRQ_TYPE_EDGE_RISING)>, 205 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 206 IRQ_TYPE_EDGE_RISING)>, 207 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 208 IRQ_TYPE_EDGE_RISING)>, 209 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 210 IRQ_TYPE_EDGE_RISING)>; 211 reg = <0x0200a000 0x100>; 212 clock-frequency = <25000000>, 213 <32768>; 214 clocks = <&sleep_clk>; 215 clock-names = "sleep"; 216 cpu-offset = <0x80000>; 217 }; 218 219 acc0: clock-controller@2088000 { 220 compatible = "qcom,kpss-acc-v1"; 221 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 222 }; 223 224 acc1: clock-controller@2098000 { 225 compatible = "qcom,kpss-acc-v1"; 226 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 227 }; 228 229 saw0: regulator@2089000 { 230 compatible = "qcom,saw2"; 231 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 232 regulator; 233 }; 234 235 saw1: regulator@2099000 { 236 compatible = "qcom,saw2"; 237 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 238 regulator; 239 }; 240 241 gsbi2: gsbi@12480000 { 242 compatible = "qcom,gsbi-v1.0.0"; 243 cell-index = <2>; 244 reg = <0x12480000 0x100>; 245 clocks = <&gcc GSBI2_H_CLK>; 246 clock-names = "iface"; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 ranges; 250 status = "disabled"; 251 252 syscon-tcsr = <&tcsr>; 253 254 gsbi2_serial: serial@12490000 { 255 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 256 reg = <0x12490000 0x1000>, 257 <0x12480000 0x1000>; 258 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 260 clock-names = "core", "iface"; 261 status = "disabled"; 262 }; 263 264 i2c@124a0000 { 265 compatible = "qcom,i2c-qup-v1.1.1"; 266 reg = <0x124a0000 0x1000>; 267 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 268 269 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 270 clock-names = "core", "iface"; 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 }; 277 278 gsbi4: gsbi@16300000 { 279 compatible = "qcom,gsbi-v1.0.0"; 280 cell-index = <4>; 281 reg = <0x16300000 0x100>; 282 clocks = <&gcc GSBI4_H_CLK>; 283 clock-names = "iface"; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 ranges; 287 status = "disabled"; 288 289 syscon-tcsr = <&tcsr>; 290 291 gsbi4_serial: serial@16340000 { 292 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 293 reg = <0x16340000 0x1000>, 294 <0x16300000 0x1000>; 295 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 297 clock-names = "core", "iface"; 298 status = "disabled"; 299 }; 300 301 i2c@16380000 { 302 compatible = "qcom,i2c-qup-v1.1.1"; 303 reg = <0x16380000 0x1000>; 304 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 305 306 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 307 clock-names = "core", "iface"; 308 status = "disabled"; 309 310 #address-cells = <1>; 311 #size-cells = <0>; 312 }; 313 }; 314 315 gsbi5: gsbi@1a200000 { 316 compatible = "qcom,gsbi-v1.0.0"; 317 cell-index = <5>; 318 reg = <0x1a200000 0x100>; 319 clocks = <&gcc GSBI5_H_CLK>; 320 clock-names = "iface"; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges; 324 status = "disabled"; 325 326 syscon-tcsr = <&tcsr>; 327 328 gsbi5_serial: serial@1a240000 { 329 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 330 reg = <0x1a240000 0x1000>, 331 <0x1a200000 0x1000>; 332 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 334 clock-names = "core", "iface"; 335 status = "disabled"; 336 }; 337 338 i2c@1a280000 { 339 compatible = "qcom,i2c-qup-v1.1.1"; 340 reg = <0x1a280000 0x1000>; 341 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 342 343 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 344 clock-names = "core", "iface"; 345 status = "disabled"; 346 347 #address-cells = <1>; 348 #size-cells = <0>; 349 }; 350 351 spi@1a280000 { 352 compatible = "qcom,spi-qup-v1.1.1"; 353 reg = <0x1a280000 0x1000>; 354 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 355 356 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 357 clock-names = "core", "iface"; 358 status = "disabled"; 359 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 }; 364 365 gsbi7: gsbi@16600000 { 366 status = "disabled"; 367 compatible = "qcom,gsbi-v1.0.0"; 368 cell-index = <7>; 369 reg = <0x16600000 0x100>; 370 clocks = <&gcc GSBI7_H_CLK>; 371 clock-names = "iface"; 372 #address-cells = <1>; 373 #size-cells = <1>; 374 ranges; 375 syscon-tcsr = <&tcsr>; 376 377 gsbi7_serial: serial@16640000 { 378 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 379 reg = <0x16640000 0x1000>, 380 <0x16600000 0x1000>; 381 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 383 clock-names = "core", "iface"; 384 status = "disabled"; 385 }; 386 }; 387 388 rng@1a500000 { 389 compatible = "qcom,prng"; 390 reg = <0x1a500000 0x200>; 391 clocks = <&gcc PRNG_CLK>; 392 clock-names = "core"; 393 }; 394 395 sata_phy: sata-phy@1b400000 { 396 compatible = "qcom,ipq806x-sata-phy"; 397 reg = <0x1b400000 0x200>; 398 399 clocks = <&gcc SATA_PHY_CFG_CLK>; 400 clock-names = "cfg"; 401 402 #phy-cells = <0>; 403 status = "disabled"; 404 }; 405 406 sata: sata@29000000 { 407 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 408 reg = <0x29000000 0x180>; 409 410 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 411 412 clocks = <&gcc SFAB_SATA_S_H_CLK>, 413 <&gcc SATA_H_CLK>, 414 <&gcc SATA_A_CLK>, 415 <&gcc SATA_RXOOB_CLK>, 416 <&gcc SATA_PMALIVE_CLK>; 417 clock-names = "slave_face", "iface", "core", 418 "rxoob", "pmalive"; 419 420 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 421 assigned-clock-rates = <100000000>, <100000000>; 422 423 phys = <&sata_phy>; 424 phy-names = "sata-phy"; 425 status = "disabled"; 426 }; 427 428 qcom,ssbi@500000 { 429 compatible = "qcom,ssbi"; 430 reg = <0x00500000 0x1000>; 431 qcom,controller-type = "pmic-arbiter"; 432 }; 433 434 qfprom: qfprom@700000 { 435 compatible = "qcom,qfprom"; 436 reg = <0x00700000 0x1000>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 }; 440 441 gcc: clock-controller@900000 { 442 compatible = "qcom,gcc-ipq8064"; 443 reg = <0x00900000 0x4000>; 444 #clock-cells = <1>; 445 #reset-cells = <1>; 446 }; 447 448 tcsr: syscon@1a400000 { 449 compatible = "qcom,tcsr-ipq8064", "syscon"; 450 reg = <0x1a400000 0x100>; 451 }; 452 453 lcc: clock-controller@28000000 { 454 compatible = "qcom,lcc-ipq8064"; 455 reg = <0x28000000 0x1000>; 456 #clock-cells = <1>; 457 #reset-cells = <1>; 458 }; 459 460 pcie0: pci@1b500000 { 461 compatible = "qcom,pcie-ipq8064"; 462 reg = <0x1b500000 0x1000 463 0x1b502000 0x80 464 0x1b600000 0x100 465 0x0ff00000 0x100000>; 466 reg-names = "dbi", "elbi", "parf", "config"; 467 device_type = "pci"; 468 linux,pci-domain = <0>; 469 bus-range = <0x00 0xff>; 470 num-lanes = <1>; 471 #address-cells = <3>; 472 #size-cells = <2>; 473 474 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ 475 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ 476 477 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 478 interrupt-names = "msi"; 479 #interrupt-cells = <1>; 480 interrupt-map-mask = <0 0 0 0x7>; 481 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 482 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 483 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 484 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 485 486 clocks = <&gcc PCIE_A_CLK>, 487 <&gcc PCIE_H_CLK>, 488 <&gcc PCIE_PHY_CLK>, 489 <&gcc PCIE_AUX_CLK>, 490 <&gcc PCIE_ALT_REF_CLK>; 491 clock-names = "core", "iface", "phy", "aux", "ref"; 492 493 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 494 assigned-clock-rates = <100000000>; 495 496 resets = <&gcc PCIE_ACLK_RESET>, 497 <&gcc PCIE_HCLK_RESET>, 498 <&gcc PCIE_POR_RESET>, 499 <&gcc PCIE_PCI_RESET>, 500 <&gcc PCIE_PHY_RESET>, 501 <&gcc PCIE_EXT_RESET>; 502 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 503 504 pinctrl-0 = <&pcie0_pins>; 505 pinctrl-names = "default"; 506 507 status = "disabled"; 508 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 509 }; 510 511 pcie1: pci@1b700000 { 512 compatible = "qcom,pcie-ipq8064"; 513 reg = <0x1b700000 0x1000 514 0x1b702000 0x80 515 0x1b800000 0x100 516 0x31f00000 0x100000>; 517 reg-names = "dbi", "elbi", "parf", "config"; 518 device_type = "pci"; 519 linux,pci-domain = <1>; 520 bus-range = <0x00 0xff>; 521 num-lanes = <1>; 522 #address-cells = <3>; 523 #size-cells = <2>; 524 525 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ 526 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ 527 528 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "msi"; 530 #interrupt-cells = <1>; 531 interrupt-map-mask = <0 0 0 0x7>; 532 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 533 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 534 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 535 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 536 537 clocks = <&gcc PCIE_1_A_CLK>, 538 <&gcc PCIE_1_H_CLK>, 539 <&gcc PCIE_1_PHY_CLK>, 540 <&gcc PCIE_1_AUX_CLK>, 541 <&gcc PCIE_1_ALT_REF_CLK>; 542 clock-names = "core", "iface", "phy", "aux", "ref"; 543 544 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 545 assigned-clock-rates = <100000000>; 546 547 resets = <&gcc PCIE_1_ACLK_RESET>, 548 <&gcc PCIE_1_HCLK_RESET>, 549 <&gcc PCIE_1_POR_RESET>, 550 <&gcc PCIE_1_PCI_RESET>, 551 <&gcc PCIE_1_PHY_RESET>, 552 <&gcc PCIE_1_EXT_RESET>; 553 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 554 555 pinctrl-0 = <&pcie1_pins>; 556 pinctrl-names = "default"; 557 558 status = "disabled"; 559 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 560 }; 561 562 pcie2: pci@1b900000 { 563 compatible = "qcom,pcie-ipq8064"; 564 reg = <0x1b900000 0x1000 565 0x1b902000 0x80 566 0x1ba00000 0x100 567 0x35f00000 0x100000>; 568 reg-names = "dbi", "elbi", "parf", "config"; 569 device_type = "pci"; 570 linux,pci-domain = <2>; 571 bus-range = <0x00 0xff>; 572 num-lanes = <1>; 573 #address-cells = <3>; 574 #size-cells = <2>; 575 576 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ 577 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ 578 579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "msi"; 581 #interrupt-cells = <1>; 582 interrupt-map-mask = <0 0 0 0x7>; 583 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 584 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 585 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 586 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 587 588 clocks = <&gcc PCIE_2_A_CLK>, 589 <&gcc PCIE_2_H_CLK>, 590 <&gcc PCIE_2_PHY_CLK>, 591 <&gcc PCIE_2_AUX_CLK>, 592 <&gcc PCIE_2_ALT_REF_CLK>; 593 clock-names = "core", "iface", "phy", "aux", "ref"; 594 595 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 596 assigned-clock-rates = <100000000>; 597 598 resets = <&gcc PCIE_2_ACLK_RESET>, 599 <&gcc PCIE_2_HCLK_RESET>, 600 <&gcc PCIE_2_POR_RESET>, 601 <&gcc PCIE_2_PCI_RESET>, 602 <&gcc PCIE_2_PHY_RESET>, 603 <&gcc PCIE_2_EXT_RESET>; 604 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 605 606 pinctrl-0 = <&pcie2_pins>; 607 pinctrl-names = "default"; 608 609 status = "disabled"; 610 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 611 }; 612 613 nss_common: syscon@03000000 { 614 compatible = "syscon"; 615 reg = <0x03000000 0x0000FFFF>; 616 }; 617 618 qsgmii_csr: syscon@1bb00000 { 619 compatible = "syscon"; 620 reg = <0x1bb00000 0x000001FF>; 621 }; 622 623 stmmac_axi_setup: stmmac-axi-config { 624 snps,wr_osr_lmt = <7>; 625 snps,rd_osr_lmt = <7>; 626 snps,blen = <16 0 0 0 0 0 0>; 627 }; 628 629 gmac0: ethernet@37000000 { 630 device_type = "network"; 631 compatible = "qcom,ipq806x-gmac"; 632 reg = <0x37000000 0x200000>; 633 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 634 interrupt-names = "macirq"; 635 636 snps,axi-config = <&stmmac_axi_setup>; 637 snps,pbl = <32>; 638 snps,aal = <1>; 639 640 qcom,nss-common = <&nss_common>; 641 qcom,qsgmii-csr = <&qsgmii_csr>; 642 643 clocks = <&gcc GMAC_CORE1_CLK>; 644 clock-names = "stmmaceth"; 645 646 resets = <&gcc GMAC_CORE1_RESET>; 647 reset-names = "stmmaceth"; 648 649 status = "disabled"; 650 }; 651 652 gmac1: ethernet@37200000 { 653 device_type = "network"; 654 compatible = "qcom,ipq806x-gmac"; 655 reg = <0x37200000 0x200000>; 656 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "macirq"; 658 659 snps,axi-config = <&stmmac_axi_setup>; 660 snps,pbl = <32>; 661 snps,aal = <1>; 662 663 qcom,nss-common = <&nss_common>; 664 qcom,qsgmii-csr = <&qsgmii_csr>; 665 666 clocks = <&gcc GMAC_CORE2_CLK>; 667 clock-names = "stmmaceth"; 668 669 resets = <&gcc GMAC_CORE2_RESET>; 670 reset-names = "stmmaceth"; 671 672 status = "disabled"; 673 }; 674 675 gmac2: ethernet@37400000 { 676 device_type = "network"; 677 compatible = "qcom,ipq806x-gmac"; 678 reg = <0x37400000 0x200000>; 679 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "macirq"; 681 682 snps,axi-config = <&stmmac_axi_setup>; 683 snps,pbl = <32>; 684 snps,aal = <1>; 685 686 qcom,nss-common = <&nss_common>; 687 qcom,qsgmii-csr = <&qsgmii_csr>; 688 689 clocks = <&gcc GMAC_CORE3_CLK>; 690 clock-names = "stmmaceth"; 691 692 resets = <&gcc GMAC_CORE3_RESET>; 693 reset-names = "stmmaceth"; 694 695 status = "disabled"; 696 }; 697 698 gmac3: ethernet@37600000 { 699 device_type = "network"; 700 compatible = "qcom,ipq806x-gmac"; 701 reg = <0x37600000 0x200000>; 702 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "macirq"; 704 705 snps,axi-config = <&stmmac_axi_setup>; 706 snps,pbl = <32>; 707 snps,aal = <1>; 708 709 qcom,nss-common = <&nss_common>; 710 qcom,qsgmii-csr = <&qsgmii_csr>; 711 712 clocks = <&gcc GMAC_CORE4_CLK>; 713 clock-names = "stmmaceth"; 714 715 resets = <&gcc GMAC_CORE4_RESET>; 716 reset-names = "stmmaceth"; 717 718 status = "disabled"; 719 }; 720 721 vsdcc_fixed: vsdcc-regulator { 722 compatible = "regulator-fixed"; 723 regulator-name = "SDCC Power"; 724 regulator-min-microvolt = <3300000>; 725 regulator-max-microvolt = <3300000>; 726 regulator-always-on; 727 }; 728 729 sdcc1bam: dma@12402000 { 730 compatible = "qcom,bam-v1.3.0"; 731 reg = <0x12402000 0x8000>; 732 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&gcc SDC1_H_CLK>; 734 clock-names = "bam_clk"; 735 #dma-cells = <1>; 736 qcom,ee = <0>; 737 }; 738 739 sdcc3bam: dma@12182000 { 740 compatible = "qcom,bam-v1.3.0"; 741 reg = <0x12182000 0x8000>; 742 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&gcc SDC3_H_CLK>; 744 clock-names = "bam_clk"; 745 #dma-cells = <1>; 746 qcom,ee = <0>; 747 }; 748 749 amba: amba { 750 compatible = "simple-bus"; 751 #address-cells = <1>; 752 #size-cells = <1>; 753 ranges; 754 755 sdcc1: sdcc@12400000 { 756 status = "disabled"; 757 compatible = "arm,pl18x", "arm,primecell"; 758 arm,primecell-periphid = <0x00051180>; 759 reg = <0x12400000 0x2000>; 760 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "cmd_irq"; 762 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 763 clock-names = "mclk", "apb_pclk"; 764 bus-width = <8>; 765 max-frequency = <96000000>; 766 non-removable; 767 cap-sd-highspeed; 768 cap-mmc-highspeed; 769 mmc-ddr-1_8v; 770 vmmc-supply = <&vsdcc_fixed>; 771 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 772 dma-names = "tx", "rx"; 773 }; 774 775 sdcc3: sdcc@12180000 { 776 compatible = "arm,pl18x", "arm,primecell"; 777 arm,primecell-periphid = <0x00051180>; 778 status = "disabled"; 779 reg = <0x12180000 0x2000>; 780 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "cmd_irq"; 782 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 783 clock-names = "mclk", "apb_pclk"; 784 bus-width = <8>; 785 cap-sd-highspeed; 786 cap-mmc-highspeed; 787 max-frequency = <192000000>; 788 sd-uhs-sdr104; 789 sd-uhs-ddr50; 790 vqmmc-supply = <&vsdcc_fixed>; 791 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 792 dma-names = "tx", "rx"; 793 }; 794 }; 795 }; 796}; 797