1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V2H (R8A77920) SoC 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7792-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7792"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &iic3; 26 spi0 = &qspi; 27 spi1 = &msiof0; 28 spi2 = &msiof1; 29 vin0 = &vin0; 30 vin1 = &vin1; 31 vin2 = &vin2; 32 vin3 = &vin3; 33 vin4 = &vin4; 34 vin5 = &vin5; 35 }; 36 37 /* External CAN clock */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "renesas,apmu"; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a15"; 53 reg = <0>; 54 clock-frequency = <1000000000>; 55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 56 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 57 next-level-cache = <&L2_CA15>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a15"; 63 reg = <1>; 64 clock-frequency = <1000000000>; 65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 67 next-level-cache = <&L2_CA15>; 68 }; 69 70 L2_CA15: cache-controller-0 { 71 compatible = "cache"; 72 cache-unified; 73 cache-level = <2>; 74 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 75 }; 76 }; 77 78 /* External root clock */ 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board. */ 83 clock-frequency = <0>; 84 }; 85 86 pmu { 87 compatible = "arm,cortex-a15-pmu"; 88 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 89 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 90 interrupt-affinity = <&cpu0>, <&cpu1>; 91 }; 92 93 /* External SCIF clock */ 94 scif_clk: scif { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board. */ 98 clock-frequency = <0>; 99 }; 100 101 soc { 102 compatible = "simple-bus"; 103 interrupt-parent = <&gic>; 104 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 rwdt: watchdog@e6020000 { 110 compatible = "renesas,r8a7792-wdt", 111 "renesas,rcar-gen2-wdt"; 112 reg = <0 0xe6020000 0 0x0c>; 113 clocks = <&cpg CPG_MOD 402>; 114 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 115 resets = <&cpg 402>; 116 status = "disabled"; 117 }; 118 119 gpio0: gpio@e6050000 { 120 compatible = "renesas,gpio-r8a7792", 121 "renesas,rcar-gen2-gpio"; 122 reg = <0 0xe6050000 0 0x50>; 123 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 124 #gpio-cells = <2>; 125 gpio-controller; 126 gpio-ranges = <&pfc 0 0 29>; 127 #interrupt-cells = <2>; 128 interrupt-controller; 129 clocks = <&cpg CPG_MOD 912>; 130 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 131 resets = <&cpg 912>; 132 }; 133 134 gpio1: gpio@e6051000 { 135 compatible = "renesas,gpio-r8a7792", 136 "renesas,rcar-gen2-gpio"; 137 reg = <0 0xe6051000 0 0x50>; 138 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 139 #gpio-cells = <2>; 140 gpio-controller; 141 gpio-ranges = <&pfc 0 32 23>; 142 #interrupt-cells = <2>; 143 interrupt-controller; 144 clocks = <&cpg CPG_MOD 911>; 145 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 146 resets = <&cpg 911>; 147 }; 148 149 gpio2: gpio@e6052000 { 150 compatible = "renesas,gpio-r8a7792", 151 "renesas,rcar-gen2-gpio"; 152 reg = <0 0xe6052000 0 0x50>; 153 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 154 #gpio-cells = <2>; 155 gpio-controller; 156 gpio-ranges = <&pfc 0 64 32>; 157 #interrupt-cells = <2>; 158 interrupt-controller; 159 clocks = <&cpg CPG_MOD 910>; 160 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 161 resets = <&cpg 910>; 162 }; 163 164 gpio3: gpio@e6053000 { 165 compatible = "renesas,gpio-r8a7792", 166 "renesas,rcar-gen2-gpio"; 167 reg = <0 0xe6053000 0 0x50>; 168 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 169 #gpio-cells = <2>; 170 gpio-controller; 171 gpio-ranges = <&pfc 0 96 28>; 172 #interrupt-cells = <2>; 173 interrupt-controller; 174 clocks = <&cpg CPG_MOD 909>; 175 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 176 resets = <&cpg 909>; 177 }; 178 179 gpio4: gpio@e6054000 { 180 compatible = "renesas,gpio-r8a7792", 181 "renesas,rcar-gen2-gpio"; 182 reg = <0 0xe6054000 0 0x50>; 183 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 184 #gpio-cells = <2>; 185 gpio-controller; 186 gpio-ranges = <&pfc 0 128 17>; 187 #interrupt-cells = <2>; 188 interrupt-controller; 189 clocks = <&cpg CPG_MOD 908>; 190 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 191 resets = <&cpg 908>; 192 }; 193 194 gpio5: gpio@e6055000 { 195 compatible = "renesas,gpio-r8a7792", 196 "renesas,rcar-gen2-gpio"; 197 reg = <0 0xe6055000 0 0x50>; 198 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 199 #gpio-cells = <2>; 200 gpio-controller; 201 gpio-ranges = <&pfc 0 160 17>; 202 #interrupt-cells = <2>; 203 interrupt-controller; 204 clocks = <&cpg CPG_MOD 907>; 205 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 206 resets = <&cpg 907>; 207 }; 208 209 gpio6: gpio@e6055100 { 210 compatible = "renesas,gpio-r8a7792", 211 "renesas,rcar-gen2-gpio"; 212 reg = <0 0xe6055100 0 0x50>; 213 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 214 #gpio-cells = <2>; 215 gpio-controller; 216 gpio-ranges = <&pfc 0 192 17>; 217 #interrupt-cells = <2>; 218 interrupt-controller; 219 clocks = <&cpg CPG_MOD 905>; 220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 221 resets = <&cpg 905>; 222 }; 223 224 gpio7: gpio@e6055200 { 225 compatible = "renesas,gpio-r8a7792", 226 "renesas,rcar-gen2-gpio"; 227 reg = <0 0xe6055200 0 0x50>; 228 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 229 #gpio-cells = <2>; 230 gpio-controller; 231 gpio-ranges = <&pfc 0 224 17>; 232 #interrupt-cells = <2>; 233 interrupt-controller; 234 clocks = <&cpg CPG_MOD 904>; 235 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 236 resets = <&cpg 904>; 237 }; 238 239 gpio8: gpio@e6055300 { 240 compatible = "renesas,gpio-r8a7792", 241 "renesas,rcar-gen2-gpio"; 242 reg = <0 0xe6055300 0 0x50>; 243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 244 #gpio-cells = <2>; 245 gpio-controller; 246 gpio-ranges = <&pfc 0 256 17>; 247 #interrupt-cells = <2>; 248 interrupt-controller; 249 clocks = <&cpg CPG_MOD 921>; 250 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 251 resets = <&cpg 921>; 252 }; 253 254 gpio9: gpio@e6055400 { 255 compatible = "renesas,gpio-r8a7792", 256 "renesas,rcar-gen2-gpio"; 257 reg = <0 0xe6055400 0 0x50>; 258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 259 #gpio-cells = <2>; 260 gpio-controller; 261 gpio-ranges = <&pfc 0 288 17>; 262 #interrupt-cells = <2>; 263 interrupt-controller; 264 clocks = <&cpg CPG_MOD 919>; 265 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 266 resets = <&cpg 919>; 267 }; 268 269 gpio10: gpio@e6055500 { 270 compatible = "renesas,gpio-r8a7792", 271 "renesas,rcar-gen2-gpio"; 272 reg = <0 0xe6055500 0 0x50>; 273 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 274 #gpio-cells = <2>; 275 gpio-controller; 276 gpio-ranges = <&pfc 0 320 32>; 277 #interrupt-cells = <2>; 278 interrupt-controller; 279 clocks = <&cpg CPG_MOD 914>; 280 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 281 resets = <&cpg 914>; 282 }; 283 284 gpio11: gpio@e6055600 { 285 compatible = "renesas,gpio-r8a7792", 286 "renesas,rcar-gen2-gpio"; 287 reg = <0 0xe6055600 0 0x50>; 288 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 289 #gpio-cells = <2>; 290 gpio-controller; 291 gpio-ranges = <&pfc 0 352 30>; 292 #interrupt-cells = <2>; 293 interrupt-controller; 294 clocks = <&cpg CPG_MOD 913>; 295 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 296 resets = <&cpg 913>; 297 }; 298 299 pfc: pinctrl@e6060000 { 300 compatible = "renesas,pfc-r8a7792"; 301 reg = <0 0xe6060000 0 0x144>; 302 }; 303 304 cpg: clock-controller@e6150000 { 305 compatible = "renesas,r8a7792-cpg-mssr"; 306 reg = <0 0xe6150000 0 0x1000>; 307 clocks = <&extal_clk>; 308 clock-names = "extal"; 309 #clock-cells = <2>; 310 #power-domain-cells = <0>; 311 #reset-cells = <1>; 312 }; 313 314 apmu@e6152000 { 315 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 316 reg = <0 0xe6152000 0 0x188>; 317 cpus = <&cpu0>, <&cpu1>; 318 }; 319 320 rst: reset-controller@e6160000 { 321 compatible = "renesas,r8a7792-rst"; 322 reg = <0 0xe6160000 0 0x0100>; 323 }; 324 325 sysc: system-controller@e6180000 { 326 compatible = "renesas,r8a7792-sysc"; 327 reg = <0 0xe6180000 0 0x0200>; 328 #power-domain-cells = <1>; 329 }; 330 331 irqc: interrupt-controller@e61c0000 { 332 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 333 #interrupt-cells = <2>; 334 interrupt-controller; 335 reg = <0 0xe61c0000 0 0x200>; 336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 407>; 341 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 342 resets = <&cpg 407>; 343 }; 344 345 icram0: sram@e63a0000 { 346 compatible = "mmio-sram"; 347 reg = <0 0xe63a0000 0 0x12000>; 348 #address-cells = <1>; 349 #size-cells = <1>; 350 ranges = <0 0 0xe63a0000 0x12000>; 351 }; 352 353 icram1: sram@e63c0000 { 354 compatible = "mmio-sram"; 355 reg = <0 0xe63c0000 0 0x1000>; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0 0 0xe63c0000 0x1000>; 359 360 smp-sram@0 { 361 compatible = "renesas,smp-sram"; 362 reg = <0 0x100>; 363 }; 364 }; 365 366 /* I2C doesn't need pinmux */ 367 i2c0: i2c@e6508000 { 368 compatible = "renesas,i2c-r8a7792", 369 "renesas,rcar-gen2-i2c"; 370 reg = <0 0xe6508000 0 0x40>; 371 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cpg CPG_MOD 931>; 373 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 374 resets = <&cpg 931>; 375 i2c-scl-internal-delay-ns = <6>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 status = "disabled"; 379 }; 380 381 i2c1: i2c@e6518000 { 382 compatible = "renesas,i2c-r8a7792", 383 "renesas,rcar-gen2-i2c"; 384 reg = <0 0xe6518000 0 0x40>; 385 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cpg CPG_MOD 930>; 387 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 388 resets = <&cpg 930>; 389 i2c-scl-internal-delay-ns = <6>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 }; 394 395 i2c2: i2c@e6530000 { 396 compatible = "renesas,i2c-r8a7792", 397 "renesas,rcar-gen2-i2c"; 398 reg = <0 0xe6530000 0 0x40>; 399 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&cpg CPG_MOD 929>; 401 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 402 resets = <&cpg 929>; 403 i2c-scl-internal-delay-ns = <6>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 status = "disabled"; 407 }; 408 409 i2c3: i2c@e6540000 { 410 compatible = "renesas,i2c-r8a7792", 411 "renesas,rcar-gen2-i2c"; 412 reg = <0 0xe6540000 0 0x40>; 413 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&cpg CPG_MOD 928>; 415 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 416 resets = <&cpg 928>; 417 i2c-scl-internal-delay-ns = <6>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 i2c4: i2c@e6520000 { 424 compatible = "renesas,i2c-r8a7792", 425 "renesas,rcar-gen2-i2c"; 426 reg = <0 0xe6520000 0 0x40>; 427 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cpg CPG_MOD 927>; 429 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 430 resets = <&cpg 927>; 431 i2c-scl-internal-delay-ns = <6>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 }; 436 437 i2c5: i2c@e6528000 { 438 compatible = "renesas,i2c-r8a7792", 439 "renesas,rcar-gen2-i2c"; 440 reg = <0 0xe6528000 0 0x40>; 441 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cpg CPG_MOD 925>; 443 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 444 resets = <&cpg 925>; 445 i2c-scl-internal-delay-ns = <110>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 status = "disabled"; 449 }; 450 451 iic3: i2c@e60b0000 { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 compatible = "renesas,iic-r8a7792", 455 "renesas,rcar-gen2-iic", 456 "renesas,rmobile-iic"; 457 reg = <0 0xe60b0000 0 0x425>; 458 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&cpg CPG_MOD 926>; 460 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 461 <&dmac1 0x77>, <&dmac1 0x78>; 462 dma-names = "tx", "rx", "tx", "rx"; 463 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 464 resets = <&cpg 926>; 465 status = "disabled"; 466 }; 467 468 dmac0: dma-controller@e6700000 { 469 compatible = "renesas,dmac-r8a7792", 470 "renesas,rcar-dmac"; 471 reg = <0 0xe6700000 0 0x20000>; 472 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 488 interrupt-names = "error", 489 "ch0", "ch1", "ch2", "ch3", 490 "ch4", "ch5", "ch6", "ch7", 491 "ch8", "ch9", "ch10", "ch11", 492 "ch12", "ch13", "ch14"; 493 clocks = <&cpg CPG_MOD 219>; 494 clock-names = "fck"; 495 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 496 resets = <&cpg 219>; 497 #dma-cells = <1>; 498 dma-channels = <15>; 499 }; 500 501 dmac1: dma-controller@e6720000 { 502 compatible = "renesas,dmac-r8a7792", 503 "renesas,rcar-dmac"; 504 reg = <0 0xe6720000 0 0x20000>; 505 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-names = "error", 522 "ch0", "ch1", "ch2", "ch3", 523 "ch4", "ch5", "ch6", "ch7", 524 "ch8", "ch9", "ch10", "ch11", 525 "ch12", "ch13", "ch14"; 526 clocks = <&cpg CPG_MOD 218>; 527 clock-names = "fck"; 528 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 529 resets = <&cpg 218>; 530 #dma-cells = <1>; 531 dma-channels = <15>; 532 }; 533 534 avb: ethernet@e6800000 { 535 compatible = "renesas,etheravb-r8a7792", 536 "renesas,etheravb-rcar-gen2"; 537 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 538 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 812>; 540 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 541 resets = <&cpg 812>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 status = "disabled"; 545 }; 546 547 qspi: spi@e6b10000 { 548 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 549 reg = <0 0xe6b10000 0 0x2c>; 550 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 917>; 552 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 553 <&dmac1 0x17>, <&dmac1 0x18>; 554 dma-names = "tx", "rx", "tx", "rx"; 555 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 556 resets = <&cpg 917>; 557 num-cs = <1>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 scif0: serial@e6e60000 { 564 compatible = "renesas,scif-r8a7792", 565 "renesas,rcar-gen2-scif", "renesas,scif"; 566 reg = <0 0xe6e60000 0 64>; 567 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cpg CPG_MOD 721>, 569 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 570 clock-names = "fck", "brg_int", "scif_clk"; 571 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 572 <&dmac1 0x29>, <&dmac1 0x2a>; 573 dma-names = "tx", "rx", "tx", "rx"; 574 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 575 resets = <&cpg 721>; 576 status = "disabled"; 577 }; 578 579 scif1: serial@e6e68000 { 580 compatible = "renesas,scif-r8a7792", 581 "renesas,rcar-gen2-scif", "renesas,scif"; 582 reg = <0 0xe6e68000 0 64>; 583 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cpg CPG_MOD 720>, 585 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 586 clock-names = "fck", "brg_int", "scif_clk"; 587 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 588 <&dmac1 0x2d>, <&dmac1 0x2e>; 589 dma-names = "tx", "rx", "tx", "rx"; 590 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 591 resets = <&cpg 720>; 592 status = "disabled"; 593 }; 594 595 scif2: serial@e6e58000 { 596 compatible = "renesas,scif-r8a7792", 597 "renesas,rcar-gen2-scif", "renesas,scif"; 598 reg = <0 0xe6e58000 0 64>; 599 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 719>, 601 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 602 clock-names = "fck", "brg_int", "scif_clk"; 603 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 604 <&dmac1 0x2b>, <&dmac1 0x2c>; 605 dma-names = "tx", "rx", "tx", "rx"; 606 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 607 resets = <&cpg 719>; 608 status = "disabled"; 609 }; 610 611 scif3: serial@e6ea8000 { 612 compatible = "renesas,scif-r8a7792", 613 "renesas,rcar-gen2-scif", "renesas,scif"; 614 reg = <0 0xe6ea8000 0 64>; 615 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&cpg CPG_MOD 718>, 617 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 618 clock-names = "fck", "brg_int", "scif_clk"; 619 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 620 <&dmac1 0x2f>, <&dmac1 0x30>; 621 dma-names = "tx", "rx", "tx", "rx"; 622 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 623 resets = <&cpg 718>; 624 status = "disabled"; 625 }; 626 627 hscif0: serial@e62c0000 { 628 compatible = "renesas,hscif-r8a7792", 629 "renesas,rcar-gen2-hscif", "renesas,hscif"; 630 reg = <0 0xe62c0000 0 96>; 631 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 717>, 633 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 634 clock-names = "fck", "brg_int", "scif_clk"; 635 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 636 <&dmac1 0x39>, <&dmac1 0x3a>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 639 resets = <&cpg 717>; 640 status = "disabled"; 641 }; 642 643 hscif1: serial@e62c8000 { 644 compatible = "renesas,hscif-r8a7792", 645 "renesas,rcar-gen2-hscif", "renesas,hscif"; 646 reg = <0 0xe62c8000 0 96>; 647 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&cpg CPG_MOD 716>, 649 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 650 clock-names = "fck", "brg_int", "scif_clk"; 651 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 652 <&dmac1 0x4d>, <&dmac1 0x4e>; 653 dma-names = "tx", "rx", "tx", "rx"; 654 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 655 resets = <&cpg 716>; 656 status = "disabled"; 657 }; 658 659 msiof0: spi@e6e20000 { 660 compatible = "renesas,msiof-r8a7792", 661 "renesas,rcar-gen2-msiof"; 662 reg = <0 0xe6e20000 0 0x0064>; 663 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&cpg CPG_MOD 000>; 665 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 666 <&dmac1 0x51>, <&dmac1 0x52>; 667 dma-names = "tx", "rx", "tx", "rx"; 668 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 669 resets = <&cpg 000>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 msiof1: spi@e6e10000 { 676 compatible = "renesas,msiof-r8a7792", 677 "renesas,rcar-gen2-msiof"; 678 reg = <0 0xe6e10000 0 0x0064>; 679 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cpg CPG_MOD 208>; 681 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 682 <&dmac1 0x55>, <&dmac1 0x56>; 683 dma-names = "tx", "rx", "tx", "rx"; 684 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 685 resets = <&cpg 208>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 }; 690 691 can0: can@e6e80000 { 692 compatible = "renesas,can-r8a7792", 693 "renesas,rcar-gen2-can"; 694 reg = <0 0xe6e80000 0 0x1000>; 695 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cpg CPG_MOD 916>, 697 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 698 clock-names = "clkp1", "clkp2", "can_clk"; 699 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 700 resets = <&cpg 916>; 701 status = "disabled"; 702 }; 703 704 can1: can@e6e88000 { 705 compatible = "renesas,can-r8a7792", 706 "renesas,rcar-gen2-can"; 707 reg = <0 0xe6e88000 0 0x1000>; 708 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD 915>, 710 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 711 clock-names = "clkp1", "clkp2", "can_clk"; 712 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 713 resets = <&cpg 915>; 714 status = "disabled"; 715 }; 716 717 vin0: video@e6ef0000 { 718 compatible = "renesas,vin-r8a7792", 719 "renesas,rcar-gen2-vin"; 720 reg = <0 0xe6ef0000 0 0x1000>; 721 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 811>; 723 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 724 resets = <&cpg 811>; 725 status = "disabled"; 726 }; 727 728 vin1: video@e6ef1000 { 729 compatible = "renesas,vin-r8a7792", 730 "renesas,rcar-gen2-vin"; 731 reg = <0 0xe6ef1000 0 0x1000>; 732 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cpg CPG_MOD 810>; 734 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 735 resets = <&cpg 810>; 736 status = "disabled"; 737 }; 738 739 vin2: video@e6ef2000 { 740 compatible = "renesas,vin-r8a7792", 741 "renesas,rcar-gen2-vin"; 742 reg = <0 0xe6ef2000 0 0x1000>; 743 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cpg CPG_MOD 809>; 745 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 746 resets = <&cpg 809>; 747 status = "disabled"; 748 }; 749 750 vin3: video@e6ef3000 { 751 compatible = "renesas,vin-r8a7792", 752 "renesas,rcar-gen2-vin"; 753 reg = <0 0xe6ef3000 0 0x1000>; 754 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&cpg CPG_MOD 808>; 756 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 757 resets = <&cpg 808>; 758 status = "disabled"; 759 }; 760 761 vin4: video@e6ef4000 { 762 compatible = "renesas,vin-r8a7792", 763 "renesas,rcar-gen2-vin"; 764 reg = <0 0xe6ef4000 0 0x1000>; 765 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cpg CPG_MOD 805>; 767 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 768 resets = <&cpg 805>; 769 status = "disabled"; 770 }; 771 772 vin5: video@e6ef5000 { 773 compatible = "renesas,vin-r8a7792", 774 "renesas,rcar-gen2-vin"; 775 reg = <0 0xe6ef5000 0 0x1000>; 776 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cpg CPG_MOD 804>; 778 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 779 resets = <&cpg 804>; 780 status = "disabled"; 781 }; 782 783 sdhi0: mmc@ee100000 { 784 compatible = "renesas,sdhi-r8a7792", 785 "renesas,rcar-gen2-sdhi"; 786 reg = <0 0xee100000 0 0x328>; 787 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 788 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 789 <&dmac1 0xcd>, <&dmac1 0xce>; 790 dma-names = "tx", "rx", "tx", "rx"; 791 clocks = <&cpg CPG_MOD 314>; 792 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 793 resets = <&cpg 314>; 794 status = "disabled"; 795 }; 796 797 gic: interrupt-controller@f1001000 { 798 compatible = "arm,gic-400"; 799 #interrupt-cells = <3>; 800 interrupt-controller; 801 reg = <0 0xf1001000 0 0x1000>, 802 <0 0xf1002000 0 0x2000>, 803 <0 0xf1004000 0 0x2000>, 804 <0 0xf1006000 0 0x2000>; 805 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 806 IRQ_TYPE_LEVEL_HIGH)>; 807 clocks = <&cpg CPG_MOD 408>; 808 clock-names = "clk"; 809 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 810 resets = <&cpg 408>; 811 }; 812 813 vsp@fe928000 { 814 compatible = "renesas,vsp1"; 815 reg = <0 0xfe928000 0 0x8000>; 816 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&cpg CPG_MOD 131>; 818 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 819 resets = <&cpg 131>; 820 }; 821 822 vsp@fe930000 { 823 compatible = "renesas,vsp1"; 824 reg = <0 0xfe930000 0 0x8000>; 825 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD 128>; 827 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 828 resets = <&cpg 128>; 829 }; 830 831 vsp@fe938000 { 832 compatible = "renesas,vsp1"; 833 reg = <0 0xfe938000 0 0x8000>; 834 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 127>; 836 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 837 resets = <&cpg 127>; 838 }; 839 840 jpu: jpeg-codec@fe980000 { 841 compatible = "renesas,jpu-r8a7792", 842 "renesas,rcar-gen2-jpu"; 843 reg = <0 0xfe980000 0 0x10300>; 844 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&cpg CPG_MOD 106>; 846 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 847 resets = <&cpg 106>; 848 }; 849 850 du: display@feb00000 { 851 compatible = "renesas,du-r8a7792"; 852 reg = <0 0xfeb00000 0 0x40000>; 853 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 856 clock-names = "du.0", "du.1"; 857 resets = <&cpg 724>; 858 reset-names = "du.0"; 859 status = "disabled"; 860 861 ports { 862 #address-cells = <1>; 863 #size-cells = <0>; 864 865 port@0 { 866 reg = <0>; 867 du_out_rgb0: endpoint { 868 }; 869 }; 870 port@1 { 871 reg = <1>; 872 du_out_rgb1: endpoint { 873 }; 874 }; 875 }; 876 }; 877 878 prr: chipid@ff000044 { 879 compatible = "renesas,prr"; 880 reg = <0 0xff000044 0 4>; 881 }; 882 883 cmt0: timer@ffca0000 { 884 compatible = "renesas,r8a7792-cmt0", 885 "renesas,rcar-gen2-cmt0"; 886 reg = <0 0xffca0000 0 0x1004>; 887 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cpg CPG_MOD 124>; 890 clock-names = "fck"; 891 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 892 resets = <&cpg 124>; 893 894 status = "disabled"; 895 }; 896 897 cmt1: timer@e6130000 { 898 compatible = "renesas,r8a7792-cmt1", 899 "renesas,rcar-gen2-cmt1"; 900 reg = <0 0xe6130000 0 0x1004>; 901 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cpg CPG_MOD 329>; 910 clock-names = "fck"; 911 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 912 resets = <&cpg 329>; 913 914 status = "disabled"; 915 }; 916 }; 917 918 timer { 919 compatible = "arm,armv7-timer"; 920 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 921 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 922 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 923 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 924 }; 925}; 926