1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,cortex-a5-pmu"; 40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 41 }; 42 43 etb@740000 { 44 compatible = "arm,coresight-etb10", "arm,primecell"; 45 reg = <0x740000 0x1000>; 46 47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 48 clock-names = "apb_pclk"; 49 50 in-ports { 51 port { 52 etb_in: endpoint { 53 remote-endpoint = <&etm_out>; 54 }; 55 }; 56 }; 57 }; 58 59 etm@73c000 { 60 compatible = "arm,coresight-etm3x", "arm,primecell"; 61 reg = <0x73c000 0x1000>; 62 63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 64 clock-names = "apb_pclk"; 65 66 out-ports { 67 port { 68 etm_out: endpoint { 69 remote-endpoint = <&etb_in>; 70 }; 71 }; 72 }; 73 }; 74 75 memory@20000000 { 76 device_type = "memory"; 77 reg = <0x20000000 0x20000000>; 78 }; 79 80 clocks { 81 slow_xtal: slow_xtal { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 main_xtal: main_xtal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <0>; 91 }; 92 }; 93 94 ns_sram: sram@200000 { 95 compatible = "mmio-sram"; 96 reg = <0x00200000 0x20000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0 0x00200000 0x20000>; 100 }; 101 102 ahb { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges; 107 108 nfc_sram: sram@100000 { 109 compatible = "mmio-sram"; 110 no-memory-wc; 111 reg = <0x00100000 0x2400>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0 0x00100000 0x2400>; 115 116 }; 117 118 usb0: gadget@300000 { 119 compatible = "atmel,sama5d3-udc"; 120 reg = <0x00300000 0x100000 121 0xfc02c000 0x400>; 122 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 123 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 124 clock-names = "pclk", "hclk"; 125 status = "disabled"; 126 }; 127 128 usb1: ohci@400000 { 129 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 130 reg = <0x00400000 0x100000>; 131 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 132 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 133 clock-names = "ohci_clk", "hclk", "uhpck"; 134 status = "disabled"; 135 }; 136 137 usb2: ehci@500000 { 138 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 139 reg = <0x00500000 0x100000>; 140 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 141 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 142 clock-names = "usb_clk", "ehci_clk"; 143 status = "disabled"; 144 }; 145 146 L2: cache-controller@a00000 { 147 compatible = "arm,pl310-cache"; 148 reg = <0x00a00000 0x1000>; 149 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 150 cache-unified; 151 cache-level = <2>; 152 }; 153 154 ebi: ebi@10000000 { 155 compatible = "atmel,sama5d3-ebi"; 156 #address-cells = <2>; 157 #size-cells = <1>; 158 atmel,smc = <&hsmc>; 159 reg = <0x10000000 0x10000000 160 0x60000000 0x30000000>; 161 ranges = <0x0 0x0 0x10000000 0x10000000 162 0x1 0x0 0x60000000 0x10000000 163 0x2 0x0 0x70000000 0x10000000 164 0x3 0x0 0x80000000 0x10000000>; 165 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 166 status = "disabled"; 167 168 nand_controller: nand-controller { 169 compatible = "atmel,sama5d3-nand-controller"; 170 atmel,nfc-sram = <&nfc_sram>; 171 atmel,nfc-io = <&nfc_io>; 172 ecc-engine = <&pmecc>; 173 #address-cells = <2>; 174 #size-cells = <1>; 175 ranges; 176 status = "disabled"; 177 }; 178 }; 179 180 sdmmc0: sdio-host@a0000000 { 181 compatible = "atmel,sama5d2-sdhci"; 182 reg = <0xa0000000 0x300>; 183 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 184 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 185 clock-names = "hclock", "multclk", "baseclk"; 186 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 187 assigned-clock-rates = <480000000>; 188 status = "disabled"; 189 }; 190 191 sdmmc1: sdio-host@b0000000 { 192 compatible = "atmel,sama5d2-sdhci"; 193 reg = <0xb0000000 0x300>; 194 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 195 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 196 clock-names = "hclock", "multclk", "baseclk"; 197 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 198 assigned-clock-rates = <480000000>; 199 status = "disabled"; 200 }; 201 202 nfc_io: nfc-io@c0000000 { 203 compatible = "atmel,sama5d3-nfc-io", "syscon"; 204 reg = <0xc0000000 0x8000000>; 205 }; 206 207 apb { 208 compatible = "simple-bus"; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges; 212 213 hlcdc: hlcdc@f0000000 { 214 compatible = "atmel,sama5d2-hlcdc"; 215 reg = <0xf0000000 0x2000>; 216 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 217 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 218 clock-names = "periph_clk","sys_clk", "slow_clk"; 219 status = "disabled"; 220 221 hlcdc-display-controller { 222 compatible = "atmel,hlcdc-display-controller"; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 226 port@0 { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 reg = <0>; 230 }; 231 }; 232 233 hlcdc_pwm: hlcdc-pwm { 234 compatible = "atmel,hlcdc-pwm"; 235 #pwm-cells = <3>; 236 }; 237 }; 238 239 isc: isc@f0008000 { 240 compatible = "atmel,sama5d2-isc"; 241 reg = <0xf0008000 0x4000>; 242 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 243 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 244 clock-names = "hclock", "iscck", "gck"; 245 #clock-cells = <0>; 246 clock-output-names = "isc-mck"; 247 status = "disabled"; 248 }; 249 250 ramc0: ramc@f000c000 { 251 compatible = "atmel,sama5d3-ddramc"; 252 reg = <0xf000c000 0x200>; 253 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 254 clock-names = "ddrck", "mpddr"; 255 }; 256 257 dma0: dma-controller@f0010000 { 258 compatible = "atmel,sama5d4-dma"; 259 reg = <0xf0010000 0x1000>; 260 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 261 #dma-cells = <1>; 262 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 263 clock-names = "dma_clk"; 264 }; 265 266 /* Place dma1 here despite its address */ 267 dma1: dma-controller@f0004000 { 268 compatible = "atmel,sama5d4-dma"; 269 reg = <0xf0004000 0x1000>; 270 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 271 #dma-cells = <1>; 272 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 273 clock-names = "dma_clk"; 274 }; 275 276 pmc: pmc@f0014000 { 277 compatible = "atmel,sama5d2-pmc", "syscon"; 278 reg = <0xf0014000 0x160>; 279 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 280 #clock-cells = <2>; 281 clocks = <&clk32k>, <&main_xtal>; 282 clock-names = "slow_clk", "main_xtal"; 283 }; 284 285 qspi0: spi@f0020000 { 286 compatible = "atmel,sama5d2-qspi"; 287 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 288 reg-names = "qspi_base", "qspi_mmap"; 289 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 290 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 qspi1: spi@f0024000 { 297 compatible = "atmel,sama5d2-qspi"; 298 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 299 reg-names = "qspi_base", "qspi_mmap"; 300 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 301 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 status = "disabled"; 305 }; 306 307 sha@f0028000 { 308 compatible = "atmel,at91sam9g46-sha"; 309 reg = <0xf0028000 0x100>; 310 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 311 dmas = <&dma0 312 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 313 AT91_XDMAC_DT_PERID(30))>; 314 dma-names = "tx"; 315 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 316 clock-names = "sha_clk"; 317 status = "okay"; 318 }; 319 320 aes@f002c000 { 321 compatible = "atmel,at91sam9g46-aes"; 322 reg = <0xf002c000 0x100>; 323 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 324 dmas = <&dma0 325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 326 AT91_XDMAC_DT_PERID(26))>, 327 <&dma0 328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 329 AT91_XDMAC_DT_PERID(27))>; 330 dma-names = "tx", "rx"; 331 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 332 clock-names = "aes_clk"; 333 status = "okay"; 334 }; 335 336 spi0: spi@f8000000 { 337 compatible = "atmel,at91rm9200-spi"; 338 reg = <0xf8000000 0x100>; 339 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 340 dmas = <&dma0 341 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 342 AT91_XDMAC_DT_PERID(6))>, 343 <&dma0 344 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 345 AT91_XDMAC_DT_PERID(7))>; 346 dma-names = "tx", "rx"; 347 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 348 clock-names = "spi_clk"; 349 atmel,fifo-size = <16>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 status = "disabled"; 353 }; 354 355 ssc0: ssc@f8004000 { 356 compatible = "atmel,at91sam9g45-ssc"; 357 reg = <0xf8004000 0x4000>; 358 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 359 dmas = <&dma0 360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 361 AT91_XDMAC_DT_PERID(21))>, 362 <&dma0 363 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 364 AT91_XDMAC_DT_PERID(22))>; 365 dma-names = "tx", "rx"; 366 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 367 clock-names = "pclk"; 368 status = "disabled"; 369 }; 370 371 macb0: ethernet@f8008000 { 372 compatible = "atmel,sama5d2-gem"; 373 reg = <0xf8008000 0x1000>; 374 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 375 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 376 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 380 clock-names = "hclk", "pclk"; 381 status = "disabled"; 382 }; 383 384 tcb0: timer@f800c000 { 385 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <0xf800c000 0x100>; 389 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 390 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 391 clock-names = "t0_clk", "gclk", "slow_clk"; 392 }; 393 394 tcb1: timer@f8010000 { 395 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 reg = <0xf8010000 0x100>; 399 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 400 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 401 clock-names = "t0_clk", "gclk", "slow_clk"; 402 }; 403 404 hsmc: hsmc@f8014000 { 405 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 406 reg = <0xf8014000 0x1000>; 407 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 408 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 ranges; 412 413 pmecc: ecc-engine@f8014070 { 414 compatible = "atmel,sama5d2-pmecc"; 415 reg = <0xf8014070 0x490>, 416 <0xf8014500 0x100>; 417 }; 418 }; 419 420 pdmic: pdmic@f8018000 { 421 compatible = "atmel,sama5d2-pdmic"; 422 reg = <0xf8018000 0x124>; 423 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 424 dmas = <&dma0 425 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 426 | AT91_XDMAC_DT_PERID(50))>; 427 dma-names = "rx"; 428 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 429 clock-names = "pclk", "gclk"; 430 status = "disabled"; 431 }; 432 433 uart0: serial@f801c000 { 434 compatible = "atmel,at91sam9260-usart"; 435 reg = <0xf801c000 0x100>; 436 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 437 dmas = <&dma0 438 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 439 AT91_XDMAC_DT_PERID(35))>, 440 <&dma0 441 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 442 AT91_XDMAC_DT_PERID(36))>; 443 dma-names = "tx", "rx"; 444 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 445 clock-names = "usart"; 446 status = "disabled"; 447 }; 448 449 uart1: serial@f8020000 { 450 compatible = "atmel,at91sam9260-usart"; 451 reg = <0xf8020000 0x100>; 452 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 453 dmas = <&dma0 454 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 455 AT91_XDMAC_DT_PERID(37))>, 456 <&dma0 457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 458 AT91_XDMAC_DT_PERID(38))>; 459 dma-names = "tx", "rx"; 460 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 461 clock-names = "usart"; 462 status = "disabled"; 463 }; 464 465 uart2: serial@f8024000 { 466 compatible = "atmel,at91sam9260-usart"; 467 reg = <0xf8024000 0x100>; 468 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 469 dmas = <&dma0 470 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 471 AT91_XDMAC_DT_PERID(39))>, 472 <&dma0 473 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 474 AT91_XDMAC_DT_PERID(40))>; 475 dma-names = "tx", "rx"; 476 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 477 clock-names = "usart"; 478 status = "disabled"; 479 }; 480 481 i2c0: i2c@f8028000 { 482 compatible = "atmel,sama5d2-i2c"; 483 reg = <0xf8028000 0x100>; 484 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 485 dmas = <&dma0 486 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 487 AT91_XDMAC_DT_PERID(0))>, 488 <&dma0 489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 490 AT91_XDMAC_DT_PERID(1))>; 491 dma-names = "tx", "rx"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 495 atmel,fifo-size = <16>; 496 status = "disabled"; 497 }; 498 499 pwm0: pwm@f802c000 { 500 compatible = "atmel,sama5d2-pwm"; 501 reg = <0xf802c000 0x4000>; 502 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 503 #pwm-cells = <3>; 504 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 505 status = "disabled"; 506 }; 507 508 sfr: sfr@f8030000 { 509 compatible = "atmel,sama5d2-sfr", "syscon"; 510 reg = <0xf8030000 0x98>; 511 }; 512 513 flx0: flexcom@f8034000 { 514 compatible = "atmel,sama5d2-flexcom"; 515 reg = <0xf8034000 0x200>; 516 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 517 #address-cells = <1>; 518 #size-cells = <1>; 519 ranges = <0x0 0xf8034000 0x800>; 520 status = "disabled"; 521 522 uart5: serial@200 { 523 compatible = "atmel,at91sam9260-usart"; 524 reg = <0x200 0x200>; 525 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 526 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 527 clock-names = "usart"; 528 dmas = <&dma0 529 (AT91_XDMAC_DT_MEM_IF(0) | 530 AT91_XDMAC_DT_PER_IF(1) | 531 AT91_XDMAC_DT_PERID(11))>, 532 <&dma0 533 (AT91_XDMAC_DT_MEM_IF(0) | 534 AT91_XDMAC_DT_PER_IF(1) | 535 AT91_XDMAC_DT_PERID(12))>; 536 dma-names = "tx", "rx"; 537 atmel,fifo-size = <32>; 538 status = "disabled"; 539 }; 540 541 spi2: spi@400 { 542 compatible = "atmel,at91rm9200-spi"; 543 reg = <0x400 0x200>; 544 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 548 clock-names = "spi_clk"; 549 dmas = <&dma0 550 (AT91_XDMAC_DT_MEM_IF(0) | 551 AT91_XDMAC_DT_PER_IF(1) | 552 AT91_XDMAC_DT_PERID(11))>, 553 <&dma0 554 (AT91_XDMAC_DT_MEM_IF(0) | 555 AT91_XDMAC_DT_PER_IF(1) | 556 AT91_XDMAC_DT_PERID(12))>; 557 dma-names = "tx", "rx"; 558 atmel,fifo-size = <16>; 559 status = "disabled"; 560 }; 561 562 i2c2: i2c@600 { 563 compatible = "atmel,sama5d2-i2c"; 564 reg = <0x600 0x200>; 565 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 569 dmas = <&dma0 570 (AT91_XDMAC_DT_MEM_IF(0) | 571 AT91_XDMAC_DT_PER_IF(1) | 572 AT91_XDMAC_DT_PERID(11))>, 573 <&dma0 574 (AT91_XDMAC_DT_MEM_IF(0) | 575 AT91_XDMAC_DT_PER_IF(1) | 576 AT91_XDMAC_DT_PERID(12))>; 577 dma-names = "tx", "rx"; 578 atmel,fifo-size = <16>; 579 status = "disabled"; 580 }; 581 }; 582 583 flx1: flexcom@f8038000 { 584 compatible = "atmel,sama5d2-flexcom"; 585 reg = <0xf8038000 0x200>; 586 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 ranges = <0x0 0xf8038000 0x800>; 590 status = "disabled"; 591 592 uart6: serial@200 { 593 compatible = "atmel,at91sam9260-usart"; 594 reg = <0x200 0x200>; 595 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 596 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 597 clock-names = "usart"; 598 dmas = <&dma0 599 (AT91_XDMAC_DT_MEM_IF(0) | 600 AT91_XDMAC_DT_PER_IF(1) | 601 AT91_XDMAC_DT_PERID(13))>, 602 <&dma0 603 (AT91_XDMAC_DT_MEM_IF(0) | 604 AT91_XDMAC_DT_PER_IF(1) | 605 AT91_XDMAC_DT_PERID(14))>; 606 dma-names = "tx", "rx"; 607 atmel,fifo-size = <32>; 608 status = "disabled"; 609 }; 610 611 spi3: spi@400 { 612 compatible = "atmel,at91rm9200-spi"; 613 reg = <0x400 0x200>; 614 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 618 clock-names = "spi_clk"; 619 dmas = <&dma0 620 (AT91_XDMAC_DT_MEM_IF(0) | 621 AT91_XDMAC_DT_PER_IF(1) | 622 AT91_XDMAC_DT_PERID(13))>, 623 <&dma0 624 (AT91_XDMAC_DT_MEM_IF(0) | 625 AT91_XDMAC_DT_PER_IF(1) | 626 AT91_XDMAC_DT_PERID(14))>; 627 dma-names = "tx", "rx"; 628 atmel,fifo-size = <16>; 629 status = "disabled"; 630 }; 631 632 i2c3: i2c@600 { 633 compatible = "atmel,sama5d2-i2c"; 634 reg = <0x600 0x200>; 635 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 639 dmas = <&dma0 640 (AT91_XDMAC_DT_MEM_IF(0) | 641 AT91_XDMAC_DT_PER_IF(1) | 642 AT91_XDMAC_DT_PERID(13))>, 643 <&dma0 644 (AT91_XDMAC_DT_MEM_IF(0) | 645 AT91_XDMAC_DT_PER_IF(1) | 646 AT91_XDMAC_DT_PERID(14))>; 647 dma-names = "tx", "rx"; 648 atmel,fifo-size = <16>; 649 status = "disabled"; 650 }; 651 }; 652 653 securam: sram@f8044000 { 654 compatible = "atmel,sama5d2-securam", "mmio-sram"; 655 reg = <0xf8044000 0x1420>; 656 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 no-memory-wc; 660 ranges = <0 0xf8044000 0x1420>; 661 }; 662 663 reset_controller: rstc@f8048000 { 664 compatible = "atmel,sama5d3-rstc"; 665 reg = <0xf8048000 0x10>; 666 clocks = <&clk32k>; 667 }; 668 669 shutdown_controller: shdwc@f8048010 { 670 compatible = "atmel,sama5d2-shdwc"; 671 reg = <0xf8048010 0x10>; 672 clocks = <&clk32k>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 atmel,wakeup-rtc-timer; 676 }; 677 678 pit: timer@f8048030 { 679 compatible = "atmel,at91sam9260-pit"; 680 reg = <0xf8048030 0x10>; 681 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 682 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 683 }; 684 685 watchdog: watchdog@f8048040 { 686 compatible = "atmel,sama5d4-wdt"; 687 reg = <0xf8048040 0x10>; 688 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 689 clocks = <&clk32k>; 690 status = "disabled"; 691 }; 692 693 clk32k: sckc@f8048050 { 694 compatible = "atmel,sama5d4-sckc"; 695 reg = <0xf8048050 0x4>; 696 697 clocks = <&slow_xtal>; 698 #clock-cells = <0>; 699 }; 700 701 rtc: rtc@f80480b0 { 702 compatible = "atmel,sama5d2-rtc"; 703 reg = <0xf80480b0 0x30>; 704 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 705 clocks = <&clk32k>; 706 }; 707 708 i2s0: i2s@f8050000 { 709 compatible = "atmel,sama5d2-i2s"; 710 reg = <0xf8050000 0x100>; 711 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 712 dmas = <&dma0 713 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 714 AT91_XDMAC_DT_PERID(31))>, 715 <&dma0 716 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 717 AT91_XDMAC_DT_PERID(32))>; 718 dma-names = "tx", "rx"; 719 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 720 clock-names = "pclk", "gclk"; 721 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 722 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 723 status = "disabled"; 724 }; 725 726 can0: can@f8054000 { 727 compatible = "bosch,m_can"; 728 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 729 reg-names = "m_can", "message_ram"; 730 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 731 <64 IRQ_TYPE_LEVEL_HIGH 7>; 732 interrupt-names = "int0", "int1"; 733 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 734 clock-names = "hclk", "cclk"; 735 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 736 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 737 assigned-clock-rates = <40000000>; 738 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 739 status = "disabled"; 740 }; 741 742 spi1: spi@fc000000 { 743 compatible = "atmel,at91rm9200-spi"; 744 reg = <0xfc000000 0x100>; 745 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 746 dmas = <&dma0 747 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 748 AT91_XDMAC_DT_PERID(8))>, 749 <&dma0 750 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 751 AT91_XDMAC_DT_PERID(9))>; 752 dma-names = "tx", "rx"; 753 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 754 clock-names = "spi_clk"; 755 atmel,fifo-size = <16>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 uart3: serial@fc008000 { 762 compatible = "atmel,at91sam9260-usart"; 763 reg = <0xfc008000 0x100>; 764 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 765 dmas = <&dma1 766 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 767 AT91_XDMAC_DT_PERID(41))>, 768 <&dma1 769 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 770 AT91_XDMAC_DT_PERID(42))>; 771 dma-names = "tx", "rx"; 772 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 773 clock-names = "usart"; 774 status = "disabled"; 775 }; 776 777 uart4: serial@fc00c000 { 778 compatible = "atmel,at91sam9260-usart"; 779 reg = <0xfc00c000 0x100>; 780 dmas = <&dma0 781 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 782 AT91_XDMAC_DT_PERID(43))>, 783 <&dma0 784 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 785 AT91_XDMAC_DT_PERID(44))>; 786 dma-names = "tx", "rx"; 787 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 788 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 789 clock-names = "usart"; 790 status = "disabled"; 791 }; 792 793 flx2: flexcom@fc010000 { 794 compatible = "atmel,sama5d2-flexcom"; 795 reg = <0xfc010000 0x200>; 796 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 797 #address-cells = <1>; 798 #size-cells = <1>; 799 ranges = <0x0 0xfc010000 0x800>; 800 status = "disabled"; 801 802 uart7: serial@200 { 803 compatible = "atmel,at91sam9260-usart"; 804 reg = <0x200 0x200>; 805 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 806 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 807 clock-names = "usart"; 808 dmas = <&dma0 809 (AT91_XDMAC_DT_MEM_IF(0) | 810 AT91_XDMAC_DT_PER_IF(1) | 811 AT91_XDMAC_DT_PERID(15))>, 812 <&dma0 813 (AT91_XDMAC_DT_MEM_IF(0) | 814 AT91_XDMAC_DT_PER_IF(1) | 815 AT91_XDMAC_DT_PERID(16))>; 816 dma-names = "tx", "rx"; 817 atmel,fifo-size = <32>; 818 status = "disabled"; 819 }; 820 821 spi4: spi@400 { 822 compatible = "atmel,at91rm9200-spi"; 823 reg = <0x400 0x200>; 824 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 828 clock-names = "spi_clk"; 829 dmas = <&dma0 830 (AT91_XDMAC_DT_MEM_IF(0) | 831 AT91_XDMAC_DT_PER_IF(1) | 832 AT91_XDMAC_DT_PERID(15))>, 833 <&dma0 834 (AT91_XDMAC_DT_MEM_IF(0) | 835 AT91_XDMAC_DT_PER_IF(1) | 836 AT91_XDMAC_DT_PERID(16))>; 837 dma-names = "tx", "rx"; 838 atmel,fifo-size = <16>; 839 status = "disabled"; 840 }; 841 842 i2c4: i2c@600 { 843 compatible = "atmel,sama5d2-i2c"; 844 reg = <0x600 0x200>; 845 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 849 dmas = <&dma0 850 (AT91_XDMAC_DT_MEM_IF(0) | 851 AT91_XDMAC_DT_PER_IF(1) | 852 AT91_XDMAC_DT_PERID(15))>, 853 <&dma0 854 (AT91_XDMAC_DT_MEM_IF(0) | 855 AT91_XDMAC_DT_PER_IF(1) | 856 AT91_XDMAC_DT_PERID(16))>; 857 dma-names = "tx", "rx"; 858 atmel,fifo-size = <16>; 859 status = "disabled"; 860 }; 861 }; 862 863 flx3: flexcom@fc014000 { 864 compatible = "atmel,sama5d2-flexcom"; 865 reg = <0xfc014000 0x200>; 866 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 ranges = <0x0 0xfc014000 0x800>; 870 status = "disabled"; 871 872 uart8: serial@200 { 873 compatible = "atmel,at91sam9260-usart"; 874 reg = <0x200 0x200>; 875 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 876 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 877 clock-names = "usart"; 878 dmas = <&dma0 879 (AT91_XDMAC_DT_MEM_IF(0) | 880 AT91_XDMAC_DT_PER_IF(1) | 881 AT91_XDMAC_DT_PERID(17))>, 882 <&dma0 883 (AT91_XDMAC_DT_MEM_IF(0) | 884 AT91_XDMAC_DT_PER_IF(1) | 885 AT91_XDMAC_DT_PERID(18))>; 886 dma-names = "tx", "rx"; 887 atmel,fifo-size = <32>; 888 status = "disabled"; 889 }; 890 891 spi5: spi@400 { 892 compatible = "atmel,at91rm9200-spi"; 893 reg = <0x400 0x200>; 894 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 898 clock-names = "spi_clk"; 899 dmas = <&dma0 900 (AT91_XDMAC_DT_MEM_IF(0) | 901 AT91_XDMAC_DT_PER_IF(1) | 902 AT91_XDMAC_DT_PERID(17))>, 903 <&dma0 904 (AT91_XDMAC_DT_MEM_IF(0) | 905 AT91_XDMAC_DT_PER_IF(1) | 906 AT91_XDMAC_DT_PERID(18))>; 907 dma-names = "tx", "rx"; 908 atmel,fifo-size = <16>; 909 status = "disabled"; 910 }; 911 912 i2c5: i2c@600 { 913 compatible = "atmel,sama5d2-i2c"; 914 reg = <0x600 0x200>; 915 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 919 dmas = <&dma0 920 (AT91_XDMAC_DT_MEM_IF(0) | 921 AT91_XDMAC_DT_PER_IF(1) | 922 AT91_XDMAC_DT_PERID(17))>, 923 <&dma0 924 (AT91_XDMAC_DT_MEM_IF(0) | 925 AT91_XDMAC_DT_PER_IF(1) | 926 AT91_XDMAC_DT_PERID(18))>; 927 dma-names = "tx", "rx"; 928 atmel,fifo-size = <16>; 929 status = "disabled"; 930 }; 931 932 }; 933 934 flx4: flexcom@fc018000 { 935 compatible = "atmel,sama5d2-flexcom"; 936 reg = <0xfc018000 0x200>; 937 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 938 #address-cells = <1>; 939 #size-cells = <1>; 940 ranges = <0x0 0xfc018000 0x800>; 941 status = "disabled"; 942 943 uart9: serial@200 { 944 compatible = "atmel,at91sam9260-usart"; 945 reg = <0x200 0x200>; 946 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 947 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 948 clock-names = "usart"; 949 dmas = <&dma0 950 (AT91_XDMAC_DT_MEM_IF(0) | 951 AT91_XDMAC_DT_PER_IF(1) | 952 AT91_XDMAC_DT_PERID(19))>, 953 <&dma0 954 (AT91_XDMAC_DT_MEM_IF(0) | 955 AT91_XDMAC_DT_PER_IF(1) | 956 AT91_XDMAC_DT_PERID(20))>; 957 dma-names = "tx", "rx"; 958 atmel,fifo-size = <32>; 959 status = "disabled"; 960 }; 961 962 spi6: spi@400 { 963 compatible = "atmel,at91rm9200-spi"; 964 reg = <0x400 0x200>; 965 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 969 clock-names = "spi_clk"; 970 dmas = <&dma0 971 (AT91_XDMAC_DT_MEM_IF(0) | 972 AT91_XDMAC_DT_PER_IF(1) | 973 AT91_XDMAC_DT_PERID(19))>, 974 <&dma0 975 (AT91_XDMAC_DT_MEM_IF(0) | 976 AT91_XDMAC_DT_PER_IF(1) | 977 AT91_XDMAC_DT_PERID(20))>; 978 dma-names = "tx", "rx"; 979 atmel,fifo-size = <16>; 980 status = "disabled"; 981 }; 982 983 i2c6: i2c@600 { 984 compatible = "atmel,sama5d2-i2c"; 985 reg = <0x600 0x200>; 986 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 990 dmas = <&dma0 991 (AT91_XDMAC_DT_MEM_IF(0) | 992 AT91_XDMAC_DT_PER_IF(1) | 993 AT91_XDMAC_DT_PERID(19))>, 994 <&dma0 995 (AT91_XDMAC_DT_MEM_IF(0) | 996 AT91_XDMAC_DT_PER_IF(1) | 997 AT91_XDMAC_DT_PERID(20))>; 998 dma-names = "tx", "rx"; 999 atmel,fifo-size = <16>; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 trng@fc01c000 { 1005 compatible = "atmel,at91sam9g45-trng"; 1006 reg = <0xfc01c000 0x100>; 1007 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1008 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1009 }; 1010 1011 aic: interrupt-controller@fc020000 { 1012 #interrupt-cells = <3>; 1013 compatible = "atmel,sama5d2-aic"; 1014 interrupt-controller; 1015 reg = <0xfc020000 0x200>; 1016 atmel,external-irqs = <49>; 1017 }; 1018 1019 i2c1: i2c@fc028000 { 1020 compatible = "atmel,sama5d2-i2c"; 1021 reg = <0xfc028000 0x100>; 1022 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1023 dmas = <&dma0 1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1025 AT91_XDMAC_DT_PERID(2))>, 1026 <&dma0 1027 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1028 AT91_XDMAC_DT_PERID(3))>; 1029 dma-names = "tx", "rx"; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1033 atmel,fifo-size = <16>; 1034 status = "disabled"; 1035 }; 1036 1037 adc: adc@fc030000 { 1038 compatible = "atmel,sama5d2-adc"; 1039 reg = <0xfc030000 0x100>; 1040 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1041 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1042 clock-names = "adc_clk"; 1043 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1044 dma-names = "rx"; 1045 atmel,min-sample-rate-hz = <200000>; 1046 atmel,max-sample-rate-hz = <20000000>; 1047 atmel,startup-time-ms = <4>; 1048 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1049 #io-channel-cells = <1>; 1050 status = "disabled"; 1051 }; 1052 1053 resistive_touch: resistive-touch { 1054 compatible = "resistive-adc-touch"; 1055 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1056 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1057 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1058 io-channel-names = "x", "y", "pressure"; 1059 touchscreen-min-pressure = <50000>; 1060 status = "disabled"; 1061 }; 1062 1063 pioA: pinctrl@fc038000 { 1064 compatible = "atmel,sama5d2-pinctrl"; 1065 reg = <0xfc038000 0x600>; 1066 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1067 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1068 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1069 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1070 interrupt-controller; 1071 #interrupt-cells = <2>; 1072 gpio-controller; 1073 #gpio-cells = <2>; 1074 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1075 }; 1076 1077 pioBU: secumod@fc040000 { 1078 compatible = "atmel,sama5d2-secumod", "syscon"; 1079 reg = <0xfc040000 0x100>; 1080 1081 gpio-controller; 1082 #gpio-cells = <2>; 1083 }; 1084 1085 tdes@fc044000 { 1086 compatible = "atmel,at91sam9g46-tdes"; 1087 reg = <0xfc044000 0x100>; 1088 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1089 dmas = <&dma0 1090 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1091 AT91_XDMAC_DT_PERID(28))>, 1092 <&dma0 1093 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1094 AT91_XDMAC_DT_PERID(29))>; 1095 dma-names = "tx", "rx"; 1096 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1097 clock-names = "tdes_clk"; 1098 status = "okay"; 1099 }; 1100 1101 classd: classd@fc048000 { 1102 compatible = "atmel,sama5d2-classd"; 1103 reg = <0xfc048000 0x100>; 1104 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1105 dmas = <&dma0 1106 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1107 AT91_XDMAC_DT_PERID(47))>; 1108 dma-names = "tx"; 1109 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1110 clock-names = "pclk", "gclk"; 1111 status = "disabled"; 1112 }; 1113 1114 i2s1: i2s@fc04c000 { 1115 compatible = "atmel,sama5d2-i2s"; 1116 reg = <0xfc04c000 0x100>; 1117 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1118 dmas = <&dma0 1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1120 AT91_XDMAC_DT_PERID(33))>, 1121 <&dma0 1122 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1123 AT91_XDMAC_DT_PERID(34))>; 1124 dma-names = "tx", "rx"; 1125 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1126 clock-names = "pclk", "gclk"; 1127 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1128 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1129 status = "disabled"; 1130 }; 1131 1132 can1: can@fc050000 { 1133 compatible = "bosch,m_can"; 1134 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1135 reg-names = "m_can", "message_ram"; 1136 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1137 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1138 interrupt-names = "int0", "int1"; 1139 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1140 clock-names = "hclk", "cclk"; 1141 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1142 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1143 assigned-clock-rates = <40000000>; 1144 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1145 status = "disabled"; 1146 }; 1147 1148 sfrbu: sfr@fc05c000 { 1149 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1150 reg = <0xfc05c000 0x20>; 1151 }; 1152 1153 chipid@fc069000 { 1154 compatible = "atmel,sama5d2-chipid"; 1155 reg = <0xfc069000 0x8>; 1156 }; 1157 }; 1158 }; 1159}; 1160