1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
5 */
6#include "stih410-clock.dtsi"
7#include "stih407-family.dtsi"
8#include "stih410-pinctrl.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10/ {
11	aliases {
12		bdisp0 = &bdisp0;
13	};
14
15	soc {
16		usb2_picophy1: phy2@0 {
17			compatible = "st,stih407-usb2-phy";
18			reg = <0 0>;
19			#phy-cells = <0>;
20			st,syscfg = <&syscfg_core 0xf8 0xf4>;
21			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
22				 <&picophyreset STIH407_PICOPHY0_RESET>;
23			reset-names = "global", "port";
24
25			status = "disabled";
26		};
27
28		usb2_picophy2: phy3@0 {
29			compatible = "st,stih407-usb2-phy";
30			reg = <0 0>;
31			#phy-cells = <0>;
32			st,syscfg = <&syscfg_core 0xfc 0xf4>;
33			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
34				 <&picophyreset STIH407_PICOPHY1_RESET>;
35			reset-names = "global", "port";
36
37			status = "disabled";
38		};
39
40		ohci0: usb@9a03c00 {
41			compatible = "st,st-ohci-300x";
42			reg = <0x9a03c00 0x100>;
43			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
44			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
45				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
46			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
47				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
48			reset-names = "power", "softreset";
49			phys = <&usb2_picophy1>;
50			phy-names = "usb";
51
52			status = "disabled";
53		};
54
55		ehci0: usb@9a03e00 {
56			compatible = "st,st-ehci-300x";
57			reg = <0x9a03e00 0x100>;
58			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
59			pinctrl-names = "default";
60			pinctrl-0 = <&pinctrl_usb0>;
61			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
62				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
63			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
64				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
65			reset-names = "power", "softreset";
66			phys = <&usb2_picophy1>;
67			phy-names = "usb";
68
69			status = "disabled";
70		};
71
72		ohci1: usb@9a83c00 {
73			compatible = "st,st-ohci-300x";
74			reg = <0x9a83c00 0x100>;
75			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
76			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
77				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
78			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
79				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
80			reset-names = "power", "softreset";
81			phys = <&usb2_picophy2>;
82			phy-names = "usb";
83
84			status = "disabled";
85		};
86
87		ehci1: usb@9a83e00 {
88			compatible = "st,st-ehci-300x";
89			reg = <0x9a83e00 0x100>;
90			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
91			pinctrl-names = "default";
92			pinctrl-0 = <&pinctrl_usb1>;
93			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
94				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
95			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
96				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
97			reset-names = "power", "softreset";
98			phys = <&usb2_picophy2>;
99			phy-names = "usb";
100
101			status = "disabled";
102		};
103
104		sti-display-subsystem@0 {
105			compatible = "st,sti-display-subsystem";
106			#address-cells = <1>;
107			#size-cells = <1>;
108
109			reg = <0 0>;
110			assigned-clocks	= <&clk_s_d2_quadfs 0>,
111					  <&clk_s_d2_quadfs 1>,
112					  <&clk_s_c0_pll1 0>,
113					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
114					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
115					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
116					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
117					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
118					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
119					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
120					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;
121
122			assigned-clock-parents = <0>,
123						 <0>,
124						 <0>,
125						 <&clk_s_c0_pll1 0>,
126						 <&clk_s_c0_pll1 0>,
127						 <&clk_s_d2_quadfs 0>,
128						 <&clk_s_d2_quadfs 1>,
129						 <&clk_s_d2_quadfs 0>,
130						 <&clk_s_d2_quadfs 0>,
131						 <&clk_s_d2_quadfs 0>,
132						 <&clk_s_d2_quadfs 0>;
133
134			assigned-clock-rates = <297000000>,
135					       <297000000>,
136					       <0>,
137					       <400000000>,
138					       <400000000>;
139
140			ranges;
141
142			sti-compositor@9d11000 {
143				compatible = "st,stih407-compositor";
144				reg = <0x9d11000 0x1000>;
145
146				clock-names = "compo_main",
147					      "compo_aux",
148					      "pix_main",
149					      "pix_aux",
150					      "pix_gdp1",
151					      "pix_gdp2",
152					      "pix_gdp3",
153					      "pix_gdp4",
154					      "main_parent",
155					      "aux_parent";
156
157				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
158					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
159					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
160					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
161					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
162					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
163					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
164					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
165					 <&clk_s_d2_quadfs 0>,
166					 <&clk_s_d2_quadfs 1>;
167
168				reset-names = "compo-main", "compo-aux";
169				resets = <&softreset STIH407_COMPO_SOFTRESET>,
170					 <&softreset STIH407_COMPO_SOFTRESET>;
171				st,vtg = <&vtg_main>, <&vtg_aux>;
172			};
173
174			sti-tvout@8d08000 {
175				compatible = "st,stih407-tvout";
176				reg = <0x8d08000 0x1000>;
177				reg-names = "tvout-reg";
178				reset-names = "tvout";
179				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
180				#address-cells = <1>;
181				#size-cells = <1>;
182				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
183						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
184						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
185						  <&clk_s_d0_flexgen CLK_PCM_0>,
186						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
187						  <&clk_s_d2_flexgen CLK_HDDAC>;
188
189				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
190							 <&clk_tmdsout_hdmi>,
191							 <&clk_s_d2_quadfs 0>,
192							 <&clk_s_d0_quadfs 0>,
193							 <&clk_s_d2_quadfs 0>,
194							 <&clk_s_d2_quadfs 0>;
195			};
196
197			sti_hdmi: sti-hdmi@8d04000 {
198				compatible = "st,stih407-hdmi";
199				reg = <0x8d04000 0x1000>;
200				reg-names = "hdmi-reg";
201				#sound-dai-cells = <0>;
202				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
203				interrupt-names	= "irq";
204				clock-names = "pix",
205					      "tmds",
206					      "phy",
207					      "audio",
208					      "main_parent",
209					      "aux_parent";
210
211				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
212					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
213					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
214					 <&clk_s_d0_flexgen CLK_PCM_0>,
215					 <&clk_s_d2_quadfs 0>,
216					 <&clk_s_d2_quadfs 1>;
217
218				hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
219				reset-names = "hdmi";
220				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
221				ddc = <&hdmiddc>;
222			};
223
224			sti-hda@8d02000 {
225				compatible = "st,stih407-hda";
226				status = "disabled";
227				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
228				reg-names = "hda-reg", "video-dacs-ctrl";
229				clock-names = "pix",
230					      "hddac",
231					      "main_parent",
232					      "aux_parent";
233				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
234					 <&clk_s_d2_flexgen CLK_HDDAC>,
235					 <&clk_s_d2_quadfs 0>,
236					 <&clk_s_d2_quadfs 1>;
237			};
238
239			sti-hqvdp@9c00000 {
240				compatible = "st,stih407-hqvdp";
241				reg = <0x9C00000 0x100000>;
242				clock-names = "hqvdp", "pix_main";
243				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
244					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
245				reset-names = "hqvdp";
246				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
247				st,vtg = <&vtg_main>;
248			};
249		};
250
251		bdisp0:bdisp@9f10000 {
252			compatible = "st,stih407-bdisp";
253			reg = <0x9f10000 0x1000>;
254			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
255			clock-names = "bdisp";
256			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
257		};
258
259		hva@8c85000 {
260			compatible = "st,st-hva";
261			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
262			reg-names = "hva_registers", "hva_esram";
263			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
264				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
265			clock-names = "clk_hva";
266			clocks = <&clk_s_c0_flexgen CLK_HVA>;
267		};
268
269		thermal@91a0000 {
270			compatible = "st,stih407-thermal";
271			reg = <0x91a0000 0x28>;
272			clock-names = "thermal";
273			clocks = <&clk_sysin>;
274			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
275		};
276
277		delta0@0 {
278			compatible = "st,st-delta";
279			clock-names = "delta",
280				      "delta-st231",
281				      "delta-flash-promip";
282			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
283				 <&clk_s_c0_flexgen CLK_ST231_DMU>,
284				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
285		};
286
287		sti-cec@94a087c {
288			compatible = "st,stih-cec";
289			reg = <0x94a087c 0x64>;
290			clocks = <&clk_sysin>;
291			clock-names = "cec-clk";
292			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
293			interrupt-names = "cec-irq";
294			pinctrl-names = "default";
295			pinctrl-0 = <&pinctrl_cec0_default>;
296			resets = <&softreset STIH407_LPM_SOFTRESET>;
297			hdmi-phandle = <&sti_hdmi>;
298		};
299	};
300};
301