1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include "stm32mp151.dtsi"
8
9/ {
10	cpus {
11		cpu1: cpu@1 {
12			compatible = "arm,cortex-a7";
13			clock-frequency = <650000000>;
14			device_type = "cpu";
15			reg = <1>;
16		};
17	};
18
19	arm-pmu {
20		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
21			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
22		interrupt-affinity = <&cpu0>, <&cpu1>;
23	};
24
25	soc {
26		m_can1: can@4400e000 {
27			compatible = "bosch,m_can";
28			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
29			reg-names = "m_can", "message_ram";
30			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
31				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
32			interrupt-names = "int0", "int1";
33			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
34			clock-names = "hclk", "cclk";
35			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
36			status = "disabled";
37		};
38
39		m_can2: can@4400f000 {
40			compatible = "bosch,m_can";
41			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
42			reg-names = "m_can", "message_ram";
43			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
44				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
45			interrupt-names = "int0", "int1";
46			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
47			clock-names = "hclk", "cclk";
48			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
49			status = "disabled";
50		};
51	};
52};
53