1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/thermal/thermal.h> 47#include <dt-bindings/dma/sun4i-a10.h> 48#include <dt-bindings/clock/sun7i-a20-ccu.h> 49#include <dt-bindings/reset/sun4i-a10-ccu.h> 50#include <dt-bindings/pinctrl/sun4i-a10.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 57 aliases { 58 ethernet0 = &gmac; 59 }; 60 61 chosen { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges; 65 66 framebuffer-lcd0-hdmi { 67 compatible = "allwinner,simple-framebuffer", 68 "simple-framebuffer"; 69 allwinner,pipeline = "de_be0-lcd0-hdmi"; 70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, 71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, 73 <&ccu CLK_HDMI>; 74 status = "disabled"; 75 }; 76 77 framebuffer-lcd0 { 78 compatible = "allwinner,simple-framebuffer", 79 "simple-framebuffer"; 80 allwinner,pipeline = "de_be0-lcd0"; 81 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, 82 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, 83 <&ccu CLK_DRAM_DE_BE0>; 84 status = "disabled"; 85 }; 86 87 framebuffer-lcd0-tve0 { 88 compatible = "allwinner,simple-framebuffer", 89 "simple-framebuffer"; 90 allwinner,pipeline = "de_be0-lcd0-tve0"; 91 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, 92 <&ccu CLK_AHB_DE_BE0>, 93 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, 94 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; 95 status = "disabled"; 96 }; 97 }; 98 99 cpus { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 cpu0: cpu@0 { 104 compatible = "arm,cortex-a7"; 105 device_type = "cpu"; 106 reg = <0>; 107 clocks = <&ccu CLK_CPU>; 108 clock-latency = <244144>; /* 8 32k periods */ 109 operating-points = < 110 /* kHz uV */ 111 960000 1400000 112 912000 1400000 113 864000 1300000 114 720000 1200000 115 528000 1100000 116 312000 1000000 117 144000 1000000 118 >; 119 #cooling-cells = <2>; 120 }; 121 122 cpu1: cpu@1 { 123 compatible = "arm,cortex-a7"; 124 device_type = "cpu"; 125 reg = <1>; 126 clocks = <&ccu CLK_CPU>; 127 clock-latency = <244144>; /* 8 32k periods */ 128 operating-points = < 129 /* kHz uV */ 130 960000 1400000 131 912000 1400000 132 864000 1300000 133 720000 1200000 134 528000 1100000 135 312000 1000000 136 144000 1000000 137 >; 138 #cooling-cells = <2>; 139 }; 140 }; 141 142 thermal-zones { 143 cpu-thermal { 144 /* milliseconds */ 145 polling-delay-passive = <250>; 146 polling-delay = <1000>; 147 thermal-sensors = <&rtp>; 148 149 cooling-maps { 150 map0 { 151 trip = <&cpu_alert0>; 152 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 153 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 154 }; 155 }; 156 157 trips { 158 cpu_alert0: cpu_alert0 { 159 /* milliCelsius */ 160 temperature = <75000>; 161 hysteresis = <2000>; 162 type = "passive"; 163 }; 164 165 cpu_crit: cpu_crit { 166 /* milliCelsius */ 167 temperature = <100000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 }; 173 }; 174 175 reserved-memory { 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges; 179 180 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ 181 default-pool { 182 compatible = "shared-dma-pool"; 183 size = <0x6000000>; 184 alloc-ranges = <0x40000000 0x10000000>; 185 reusable; 186 linux,cma-default; 187 }; 188 }; 189 190 timer { 191 compatible = "arm,armv7-timer"; 192 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 193 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 194 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 195 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 196 }; 197 198 pmu { 199 compatible = "arm,cortex-a7-pmu"; 200 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 202 }; 203 204 clocks { 205 #address-cells = <1>; 206 #size-cells = <1>; 207 ranges; 208 209 osc24M: clk-24M { 210 #clock-cells = <0>; 211 compatible = "fixed-clock"; 212 clock-frequency = <24000000>; 213 clock-output-names = "osc24M"; 214 }; 215 216 osc32k: clk-32k { 217 #clock-cells = <0>; 218 compatible = "fixed-clock"; 219 clock-frequency = <32768>; 220 clock-output-names = "osc32k"; 221 }; 222 223 /* 224 * The following two are dummy clocks, placeholders 225 * used in the gmac_tx clock. The gmac driver will 226 * choose one parent depending on the PHY interface 227 * mode, using clk_set_rate auto-reparenting. 228 * 229 * The actual TX clock rate is not controlled by the 230 * gmac_tx clock. 231 */ 232 mii_phy_tx_clk: clk-mii-phy-tx { 233 #clock-cells = <0>; 234 compatible = "fixed-clock"; 235 clock-frequency = <25000000>; 236 clock-output-names = "mii_phy_tx"; 237 }; 238 239 gmac_int_tx_clk: clk-gmac-int-tx { 240 #clock-cells = <0>; 241 compatible = "fixed-clock"; 242 clock-frequency = <125000000>; 243 clock-output-names = "gmac_int_tx"; 244 }; 245 246 gmac_tx_clk: clk@1c20164 { 247 #clock-cells = <0>; 248 compatible = "allwinner,sun7i-a20-gmac-clk"; 249 reg = <0x01c20164 0x4>; 250 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 251 clock-output-names = "gmac_tx"; 252 }; 253 }; 254 255 256 de: display-engine { 257 compatible = "allwinner,sun7i-a20-display-engine"; 258 allwinner,pipelines = <&fe0>, <&fe1>; 259 status = "disabled"; 260 }; 261 262 soc { 263 compatible = "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges; 267 268 system-control@1c00000 { 269 compatible = "allwinner,sun7i-a20-system-control", 270 "allwinner,sun4i-a10-system-control"; 271 reg = <0x01c00000 0x30>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges; 275 276 sram_a: sram@0 { 277 compatible = "mmio-sram"; 278 reg = <0x00000000 0xc000>; 279 #address-cells = <1>; 280 #size-cells = <1>; 281 ranges = <0 0x00000000 0xc000>; 282 283 emac_sram: sram-section@8000 { 284 compatible = "allwinner,sun7i-a20-sram-a3-a4", 285 "allwinner,sun4i-a10-sram-a3-a4"; 286 reg = <0x8000 0x4000>; 287 status = "disabled"; 288 }; 289 }; 290 291 sram_d: sram@10000 { 292 compatible = "mmio-sram"; 293 reg = <0x00010000 0x1000>; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges = <0 0x00010000 0x1000>; 297 298 otg_sram: sram-section@0 { 299 compatible = "allwinner,sun7i-a20-sram-d", 300 "allwinner,sun4i-a10-sram-d"; 301 reg = <0x0000 0x1000>; 302 status = "disabled"; 303 }; 304 }; 305 306 sram_c: sram@1d00000 { 307 compatible = "mmio-sram"; 308 reg = <0x01d00000 0xd0000>; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 ranges = <0 0x01d00000 0xd0000>; 312 313 ve_sram: sram-section@0 { 314 compatible = "allwinner,sun7i-a20-sram-c1", 315 "allwinner,sun4i-a10-sram-c1"; 316 reg = <0x000000 0x80000>; 317 }; 318 }; 319 }; 320 321 nmi_intc: interrupt-controller@1c00030 { 322 compatible = "allwinner,sun7i-a20-sc-nmi"; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 reg = <0x01c00030 0x0c>; 326 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 327 }; 328 329 dma: dma-controller@1c02000 { 330 compatible = "allwinner,sun4i-a10-dma"; 331 reg = <0x01c02000 0x1000>; 332 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_AHB_DMA>; 334 #dma-cells = <2>; 335 }; 336 337 nfc: nand-controller@1c03000 { 338 compatible = "allwinner,sun4i-a10-nand"; 339 reg = <0x01c03000 0x1000>; 340 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 342 clock-names = "ahb", "mod"; 343 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 344 dma-names = "rxtx"; 345 status = "disabled"; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 }; 349 350 spi0: spi@1c05000 { 351 compatible = "allwinner,sun4i-a10-spi"; 352 reg = <0x01c05000 0x1000>; 353 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 355 clock-names = "ahb", "mod"; 356 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 357 <&dma SUN4I_DMA_DEDICATED 26>; 358 dma-names = "rx", "tx"; 359 status = "disabled"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 num-cs = <4>; 363 }; 364 365 spi1: spi@1c06000 { 366 compatible = "allwinner,sun4i-a10-spi"; 367 reg = <0x01c06000 0x1000>; 368 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 370 clock-names = "ahb", "mod"; 371 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 372 <&dma SUN4I_DMA_DEDICATED 8>; 373 dma-names = "rx", "tx"; 374 status = "disabled"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 num-cs = <1>; 378 }; 379 380 csi0: csi@1c09000 { 381 compatible = "allwinner,sun7i-a20-csi0"; 382 reg = <0x01c09000 0x1000>; 383 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; 385 clock-names = "bus", "isp", "ram"; 386 resets = <&ccu RST_CSI0>; 387 status = "disabled"; 388 }; 389 390 emac: ethernet@1c0b000 { 391 compatible = "allwinner,sun4i-a10-emac"; 392 reg = <0x01c0b000 0x1000>; 393 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&ccu CLK_AHB_EMAC>; 395 allwinner,sram = <&emac_sram 1>; 396 status = "disabled"; 397 }; 398 399 mdio: mdio@1c0b080 { 400 compatible = "allwinner,sun4i-a10-mdio"; 401 reg = <0x01c0b080 0x14>; 402 status = "disabled"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 }; 406 407 tcon0: lcd-controller@1c0c000 { 408 compatible = "allwinner,sun7i-a20-tcon0", 409 "allwinner,sun7i-a20-tcon"; 410 reg = <0x01c0c000 0x1000>; 411 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 412 resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>; 413 reset-names = "lcd", "lvds"; 414 clocks = <&ccu CLK_AHB_LCD0>, 415 <&ccu CLK_TCON0_CH0>, 416 <&ccu CLK_TCON0_CH1>; 417 clock-names = "ahb", 418 "tcon-ch0", 419 "tcon-ch1"; 420 clock-output-names = "tcon0-pixel-clock"; 421 #clock-cells = <0>; 422 dmas = <&dma SUN4I_DMA_DEDICATED 14>; 423 424 ports { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 428 tcon0_in: port@0 { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 reg = <0>; 432 433 tcon0_in_be0: endpoint@0 { 434 reg = <0>; 435 remote-endpoint = <&be0_out_tcon0>; 436 }; 437 438 tcon0_in_be1: endpoint@1 { 439 reg = <1>; 440 remote-endpoint = <&be1_out_tcon0>; 441 }; 442 }; 443 444 tcon0_out: port@1 { 445 #address-cells = <1>; 446 #size-cells = <0>; 447 reg = <1>; 448 449 tcon0_out_hdmi: endpoint@1 { 450 reg = <1>; 451 remote-endpoint = <&hdmi_in_tcon0>; 452 allwinner,tcon-channel = <1>; 453 }; 454 }; 455 }; 456 }; 457 458 tcon1: lcd-controller@1c0d000 { 459 compatible = "allwinner,sun7i-a20-tcon1", 460 "allwinner,sun7i-a20-tcon"; 461 reg = <0x01c0d000 0x1000>; 462 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 463 resets = <&ccu RST_TCON1>; 464 reset-names = "lcd"; 465 clocks = <&ccu CLK_AHB_LCD1>, 466 <&ccu CLK_TCON1_CH0>, 467 <&ccu CLK_TCON1_CH1>; 468 clock-names = "ahb", 469 "tcon-ch0", 470 "tcon-ch1"; 471 clock-output-names = "tcon1-pixel-clock"; 472 #clock-cells = <0>; 473 dmas = <&dma SUN4I_DMA_DEDICATED 15>; 474 475 ports { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 479 tcon1_in: port@0 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 reg = <0>; 483 484 tcon1_in_be0: endpoint@0 { 485 reg = <0>; 486 remote-endpoint = <&be0_out_tcon1>; 487 }; 488 489 tcon1_in_be1: endpoint@1 { 490 reg = <1>; 491 remote-endpoint = <&be1_out_tcon1>; 492 }; 493 }; 494 495 tcon1_out: port@1 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <1>; 499 500 tcon1_out_hdmi: endpoint@1 { 501 reg = <1>; 502 remote-endpoint = <&hdmi_in_tcon1>; 503 allwinner,tcon-channel = <1>; 504 }; 505 }; 506 }; 507 }; 508 509 video-codec@1c0e000 { 510 compatible = "allwinner,sun7i-a20-video-engine"; 511 reg = <0x01c0e000 0x1000>; 512 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, 513 <&ccu CLK_DRAM_VE>; 514 clock-names = "ahb", "mod", "ram"; 515 resets = <&ccu RST_VE>; 516 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 517 allwinner,sram = <&ve_sram 1>; 518 }; 519 520 mmc0: mmc@1c0f000 { 521 compatible = "allwinner,sun7i-a20-mmc"; 522 reg = <0x01c0f000 0x1000>; 523 clocks = <&ccu CLK_AHB_MMC0>, 524 <&ccu CLK_MMC0>, 525 <&ccu CLK_MMC0_OUTPUT>, 526 <&ccu CLK_MMC0_SAMPLE>; 527 clock-names = "ahb", 528 "mmc", 529 "output", 530 "sample"; 531 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&mmc0_pins>; 534 status = "disabled"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 }; 538 539 mmc1: mmc@1c10000 { 540 compatible = "allwinner,sun7i-a20-mmc"; 541 reg = <0x01c10000 0x1000>; 542 clocks = <&ccu CLK_AHB_MMC1>, 543 <&ccu CLK_MMC1>, 544 <&ccu CLK_MMC1_OUTPUT>, 545 <&ccu CLK_MMC1_SAMPLE>; 546 clock-names = "ahb", 547 "mmc", 548 "output", 549 "sample"; 550 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 551 status = "disabled"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 }; 555 556 mmc2: mmc@1c11000 { 557 compatible = "allwinner,sun7i-a20-mmc"; 558 reg = <0x01c11000 0x1000>; 559 clocks = <&ccu CLK_AHB_MMC2>, 560 <&ccu CLK_MMC2>, 561 <&ccu CLK_MMC2_OUTPUT>, 562 <&ccu CLK_MMC2_SAMPLE>; 563 clock-names = "ahb", 564 "mmc", 565 "output", 566 "sample"; 567 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&mmc2_pins>; 570 status = "disabled"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 }; 574 575 mmc3: mmc@1c12000 { 576 compatible = "allwinner,sun7i-a20-mmc"; 577 reg = <0x01c12000 0x1000>; 578 clocks = <&ccu CLK_AHB_MMC3>, 579 <&ccu CLK_MMC3>, 580 <&ccu CLK_MMC3_OUTPUT>, 581 <&ccu CLK_MMC3_SAMPLE>; 582 clock-names = "ahb", 583 "mmc", 584 "output", 585 "sample"; 586 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&mmc3_pins>; 589 status = "disabled"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 }; 593 594 usb_otg: usb@1c13000 { 595 compatible = "allwinner,sun4i-a10-musb"; 596 reg = <0x01c13000 0x0400>; 597 clocks = <&ccu CLK_AHB_OTG>; 598 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "mc"; 600 phys = <&usbphy 0>; 601 phy-names = "usb"; 602 extcon = <&usbphy 0>; 603 allwinner,sram = <&otg_sram 1>; 604 dr_mode = "otg"; 605 status = "disabled"; 606 }; 607 608 usbphy: phy@1c13400 { 609 #phy-cells = <1>; 610 compatible = "allwinner,sun7i-a20-usb-phy"; 611 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; 612 reg-names = "phy_ctrl", "pmu1", "pmu2"; 613 clocks = <&ccu CLK_USB_PHY>; 614 clock-names = "usb_phy"; 615 resets = <&ccu RST_USB_PHY0>, 616 <&ccu RST_USB_PHY1>, 617 <&ccu RST_USB_PHY2>; 618 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 619 status = "disabled"; 620 }; 621 622 ehci0: usb@1c14000 { 623 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 624 reg = <0x01c14000 0x100>; 625 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&ccu CLK_AHB_EHCI0>; 627 phys = <&usbphy 1>; 628 phy-names = "usb"; 629 status = "disabled"; 630 }; 631 632 ohci0: usb@1c14400 { 633 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 634 reg = <0x01c14400 0x100>; 635 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; 637 phys = <&usbphy 1>; 638 phy-names = "usb"; 639 status = "disabled"; 640 }; 641 642 crypto: crypto-engine@1c15000 { 643 compatible = "allwinner,sun7i-a20-crypto", 644 "allwinner,sun4i-a10-crypto"; 645 reg = <0x01c15000 0x1000>; 646 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; 648 clock-names = "ahb", "mod"; 649 }; 650 651 hdmi: hdmi@1c16000 { 652 compatible = "allwinner,sun7i-a20-hdmi", 653 "allwinner,sun5i-a10s-hdmi"; 654 reg = <0x01c16000 0x1000>; 655 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, 657 <&ccu CLK_PLL_VIDEO0_2X>, 658 <&ccu CLK_PLL_VIDEO1_2X>; 659 clock-names = "ahb", "mod", "pll-0", "pll-1"; 660 dmas = <&dma SUN4I_DMA_NORMAL 16>, 661 <&dma SUN4I_DMA_NORMAL 16>, 662 <&dma SUN4I_DMA_DEDICATED 24>; 663 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 664 status = "disabled"; 665 666 ports { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 670 hdmi_in: port@0 { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 reg = <0>; 674 675 hdmi_in_tcon0: endpoint@0 { 676 reg = <0>; 677 remote-endpoint = <&tcon0_out_hdmi>; 678 }; 679 680 hdmi_in_tcon1: endpoint@1 { 681 reg = <1>; 682 remote-endpoint = <&tcon1_out_hdmi>; 683 }; 684 }; 685 686 hdmi_out: port@1 { 687 reg = <1>; 688 }; 689 }; 690 }; 691 692 spi2: spi@1c17000 { 693 compatible = "allwinner,sun4i-a10-spi"; 694 reg = <0x01c17000 0x1000>; 695 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 697 clock-names = "ahb", "mod"; 698 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 699 <&dma SUN4I_DMA_DEDICATED 28>; 700 dma-names = "rx", "tx"; 701 status = "disabled"; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 num-cs = <1>; 705 }; 706 707 ahci: sata@1c18000 { 708 compatible = "allwinner,sun4i-a10-ahci"; 709 reg = <0x01c18000 0x1000>; 710 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; 712 status = "disabled"; 713 }; 714 715 ehci1: usb@1c1c000 { 716 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 717 reg = <0x01c1c000 0x100>; 718 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&ccu CLK_AHB_EHCI1>; 720 phys = <&usbphy 2>; 721 phy-names = "usb"; 722 status = "disabled"; 723 }; 724 725 ohci1: usb@1c1c400 { 726 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 727 reg = <0x01c1c400 0x100>; 728 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; 730 phys = <&usbphy 2>; 731 phy-names = "usb"; 732 status = "disabled"; 733 }; 734 735 csi1: csi@1c1d000 { 736 compatible = "allwinner,sun7i-a20-csi1", 737 "allwinner,sun4i-a10-csi1"; 738 reg = <0x01c1d000 0x1000>; 739 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; 741 clock-names = "bus", "ram"; 742 resets = <&ccu RST_CSI1>; 743 status = "disabled"; 744 }; 745 746 spi3: spi@1c1f000 { 747 compatible = "allwinner,sun4i-a10-spi"; 748 reg = <0x01c1f000 0x1000>; 749 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; 751 clock-names = "ahb", "mod"; 752 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 753 <&dma SUN4I_DMA_DEDICATED 30>; 754 dma-names = "rx", "tx"; 755 status = "disabled"; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 num-cs = <1>; 759 }; 760 761 ccu: clock@1c20000 { 762 compatible = "allwinner,sun7i-a20-ccu"; 763 reg = <0x01c20000 0x400>; 764 clocks = <&osc24M>, <&osc32k>; 765 clock-names = "hosc", "losc"; 766 #clock-cells = <1>; 767 #reset-cells = <1>; 768 }; 769 770 pio: pinctrl@1c20800 { 771 compatible = "allwinner,sun7i-a20-pinctrl"; 772 reg = <0x01c20800 0x400>; 773 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 775 clock-names = "apb", "hosc", "losc"; 776 gpio-controller; 777 interrupt-controller; 778 #interrupt-cells = <3>; 779 #gpio-cells = <3>; 780 781 /omit-if-no-ref/ 782 can_pa_pins: can-pa-pins { 783 pins = "PA16", "PA17"; 784 function = "can"; 785 }; 786 787 /omit-if-no-ref/ 788 can_ph_pins: can-ph-pins { 789 pins = "PH20", "PH21"; 790 function = "can"; 791 }; 792 793 /omit-if-no-ref/ 794 clk_out_a_pin: clk-out-a-pin { 795 pins = "PI12"; 796 function = "clk_out_a"; 797 }; 798 799 /omit-if-no-ref/ 800 clk_out_b_pin: clk-out-b-pin { 801 pins = "PI13"; 802 function = "clk_out_b"; 803 }; 804 805 /omit-if-no-ref/ 806 csi0_8bits_pins: csi-8bits-pins { 807 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 808 "PE6", "PE7", "PE8", "PE9", "PE10", 809 "PE11"; 810 function = "csi0"; 811 }; 812 813 /omit-if-no-ref/ 814 csi0_clk_pin: csi-clk-pin { 815 pins = "PE1"; 816 function = "csi0"; 817 }; 818 819 /omit-if-no-ref/ 820 csi1_8bits_pg_pins: csi1-8bits-pg-pins { 821 pins = "PG0", "PG2", "PG3", "PG4", "PG5", 822 "PG6", "PG7", "PG8", "PG9", "PG10", 823 "PG11"; 824 function = "csi1"; 825 }; 826 827 /omit-if-no-ref/ 828 csi1_24bits_ph_pins: csi1-24bits-ph-pins { 829 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 830 "PH5", "PH6", "PH7", "PH8", "PH9", 831 "PH10", "PH11", "PH12", "PH13", "PH14", 832 "PH15", "PH16", "PH17", "PH18", "PH19", 833 "PH20", "PH21", "PH22", "PH23", "PH24", 834 "PH25", "PH26", "PH27"; 835 function = "csi1"; 836 }; 837 838 /omit-if-no-ref/ 839 csi1_clk_pg_pin: csi1-clk-pg-pin { 840 pins = "PG1"; 841 function = "csi1"; 842 }; 843 844 /omit-if-no-ref/ 845 emac_pa_pins: emac-pa-pins { 846 pins = "PA0", "PA1", "PA2", 847 "PA3", "PA4", "PA5", "PA6", 848 "PA7", "PA8", "PA9", "PA10", 849 "PA11", "PA12", "PA13", "PA14", 850 "PA15", "PA16"; 851 function = "emac"; 852 }; 853 854 /omit-if-no-ref/ 855 emac_ph_pins: emac-ph-pins { 856 pins = "PH8", "PH9", "PH10", "PH11", 857 "PH14", "PH15", "PH16", "PH17", 858 "PH18", "PH19", "PH20", "PH21", 859 "PH22", "PH23", "PH24", "PH25", 860 "PH26"; 861 function = "emac"; 862 }; 863 864 /omit-if-no-ref/ 865 gmac_mii_pins: gmac-mii-pins { 866 pins = "PA0", "PA1", "PA2", 867 "PA3", "PA4", "PA5", "PA6", 868 "PA7", "PA8", "PA9", "PA10", 869 "PA11", "PA12", "PA13", "PA14", 870 "PA15", "PA16"; 871 function = "gmac"; 872 }; 873 874 /omit-if-no-ref/ 875 gmac_rgmii_pins: gmac-rgmii-pins { 876 pins = "PA0", "PA1", "PA2", 877 "PA3", "PA4", "PA5", "PA6", 878 "PA7", "PA8", "PA10", 879 "PA11", "PA12", "PA13", 880 "PA15", "PA16"; 881 function = "gmac"; 882 /* 883 * data lines in RGMII mode use DDR mode 884 * and need a higher signal drive strength 885 */ 886 drive-strength = <40>; 887 }; 888 889 /omit-if-no-ref/ 890 i2c0_pins: i2c0-pins { 891 pins = "PB0", "PB1"; 892 function = "i2c0"; 893 }; 894 895 /omit-if-no-ref/ 896 i2c1_pins: i2c1-pins { 897 pins = "PB18", "PB19"; 898 function = "i2c1"; 899 }; 900 901 /omit-if-no-ref/ 902 i2c2_pins: i2c2-pins { 903 pins = "PB20", "PB21"; 904 function = "i2c2"; 905 }; 906 907 /omit-if-no-ref/ 908 i2c3_pins: i2c3-pins { 909 pins = "PI0", "PI1"; 910 function = "i2c3"; 911 }; 912 913 /omit-if-no-ref/ 914 ir0_rx_pin: ir0-rx-pin { 915 pins = "PB4"; 916 function = "ir0"; 917 }; 918 919 /omit-if-no-ref/ 920 ir0_tx_pin: ir0-tx-pin { 921 pins = "PB3"; 922 function = "ir0"; 923 }; 924 925 /omit-if-no-ref/ 926 ir1_rx_pin: ir1-rx-pin { 927 pins = "PB23"; 928 function = "ir1"; 929 }; 930 931 /omit-if-no-ref/ 932 ir1_tx_pin: ir1-tx-pin { 933 pins = "PB22"; 934 function = "ir1"; 935 }; 936 937 /omit-if-no-ref/ 938 lcd_lvds0_pins: lcd-lvds0-pins { 939 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 940 "PD5", "PD6", "PD7", "PD8", "PD9"; 941 function = "lvds0"; 942 }; 943 944 /omit-if-no-ref/ 945 lcd_lvds1_pins: lcd-lvds1-pins { 946 pins = "PD10", "PD11", "PD12", "PD13", "PD14", 947 "PD15", "PD16", "PD17", "PD18", "PD19"; 948 function = "lvds1"; 949 }; 950 951 /omit-if-no-ref/ 952 mmc0_pins: mmc0-pins { 953 pins = "PF0", "PF1", "PF2", 954 "PF3", "PF4", "PF5"; 955 function = "mmc0"; 956 drive-strength = <30>; 957 bias-pull-up; 958 }; 959 960 /omit-if-no-ref/ 961 mmc2_pins: mmc2-pins { 962 pins = "PC6", "PC7", "PC8", 963 "PC9", "PC10", "PC11"; 964 function = "mmc2"; 965 drive-strength = <30>; 966 bias-pull-up; 967 }; 968 969 /omit-if-no-ref/ 970 mmc3_pins: mmc3-pins { 971 pins = "PI4", "PI5", "PI6", 972 "PI7", "PI8", "PI9"; 973 function = "mmc3"; 974 drive-strength = <30>; 975 bias-pull-up; 976 }; 977 978 /omit-if-no-ref/ 979 ps2_0_pins: ps2-0-pins { 980 pins = "PI20", "PI21"; 981 function = "ps2"; 982 }; 983 984 /omit-if-no-ref/ 985 ps2_1_ph_pins: ps2-1-ph-pins { 986 pins = "PH12", "PH13"; 987 function = "ps2"; 988 }; 989 990 /omit-if-no-ref/ 991 pwm0_pin: pwm0-pin { 992 pins = "PB2"; 993 function = "pwm"; 994 }; 995 996 /omit-if-no-ref/ 997 pwm1_pin: pwm1-pin { 998 pins = "PI3"; 999 function = "pwm"; 1000 }; 1001 1002 /omit-if-no-ref/ 1003 spdif_tx_pin: spdif-tx-pin { 1004 pins = "PB13"; 1005 function = "spdif"; 1006 bias-pull-up; 1007 }; 1008 1009 /omit-if-no-ref/ 1010 spi0_pi_pins: spi0-pi-pins { 1011 pins = "PI11", "PI12", "PI13"; 1012 function = "spi0"; 1013 }; 1014 1015 /omit-if-no-ref/ 1016 spi0_cs0_pi_pin: spi0-cs0-pi-pin { 1017 pins = "PI10"; 1018 function = "spi0"; 1019 }; 1020 1021 /omit-if-no-ref/ 1022 spi0_cs1_pi_pin: spi0-cs1-pi-pin { 1023 pins = "PI14"; 1024 function = "spi0"; 1025 }; 1026 1027 /omit-if-no-ref/ 1028 spi1_pi_pins: spi1-pi-pins { 1029 pins = "PI17", "PI18", "PI19"; 1030 function = "spi1"; 1031 }; 1032 1033 /omit-if-no-ref/ 1034 spi1_cs0_pi_pin: spi1-cs0-pi-pin { 1035 pins = "PI16"; 1036 function = "spi1"; 1037 }; 1038 1039 /omit-if-no-ref/ 1040 spi2_pb_pins: spi2-pb-pins { 1041 pins = "PB15", "PB16", "PB17"; 1042 function = "spi2"; 1043 }; 1044 1045 /omit-if-no-ref/ 1046 spi2_cs0_pb_pin: spi2-cs0-pb-pin { 1047 pins = "PB14"; 1048 function = "spi2"; 1049 }; 1050 1051 /omit-if-no-ref/ 1052 spi2_pc_pins: spi2-pc-pins { 1053 pins = "PC20", "PC21", "PC22"; 1054 function = "spi2"; 1055 }; 1056 1057 /omit-if-no-ref/ 1058 spi2_cs0_pc_pin: spi2-cs0-pc-pin { 1059 pins = "PC19"; 1060 function = "spi2"; 1061 }; 1062 1063 /omit-if-no-ref/ 1064 uart0_pb_pins: uart0-pb-pins { 1065 pins = "PB22", "PB23"; 1066 function = "uart0"; 1067 }; 1068 1069 /omit-if-no-ref/ 1070 uart0_pf_pins: uart0-pf-pins { 1071 pins = "PF2", "PF4"; 1072 function = "uart0"; 1073 }; 1074 1075 /omit-if-no-ref/ 1076 uart1_pa_pins: uart1-pa-pins { 1077 pins = "PA10", "PA11"; 1078 function = "uart1"; 1079 }; 1080 1081 /omit-if-no-ref/ 1082 uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { 1083 pins = "PA12", "PA13"; 1084 function = "uart1"; 1085 }; 1086 1087 /omit-if-no-ref/ 1088 uart2_pa_pins: uart2-pa-pins { 1089 pins = "PA2", "PA3"; 1090 function = "uart2"; 1091 }; 1092 1093 /omit-if-no-ref/ 1094 uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { 1095 pins = "PA0", "PA1"; 1096 function = "uart2"; 1097 }; 1098 1099 /omit-if-no-ref/ 1100 uart2_pi_pins: uart2-pi-pins { 1101 pins = "PI18", "PI19"; 1102 function = "uart2"; 1103 }; 1104 1105 /omit-if-no-ref/ 1106 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { 1107 pins = "PI16", "PI17"; 1108 function = "uart2"; 1109 }; 1110 1111 /omit-if-no-ref/ 1112 uart3_pg_pins: uart3-pg-pins { 1113 pins = "PG6", "PG7"; 1114 function = "uart3"; 1115 }; 1116 1117 /omit-if-no-ref/ 1118 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { 1119 pins = "PG8", "PG9"; 1120 function = "uart3"; 1121 }; 1122 1123 /omit-if-no-ref/ 1124 uart3_ph_pins: uart3-ph-pins { 1125 pins = "PH0", "PH1"; 1126 function = "uart3"; 1127 }; 1128 1129 /omit-if-no-ref/ 1130 uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { 1131 pins = "PH2", "PH3"; 1132 function = "uart3"; 1133 }; 1134 1135 /omit-if-no-ref/ 1136 uart4_pg_pins: uart4-pg-pins { 1137 pins = "PG10", "PG11"; 1138 function = "uart4"; 1139 }; 1140 1141 /omit-if-no-ref/ 1142 uart4_ph_pins: uart4-ph-pins { 1143 pins = "PH4", "PH5"; 1144 function = "uart4"; 1145 }; 1146 1147 /omit-if-no-ref/ 1148 uart5_ph_pins: uart5-ph-pins { 1149 pins = "PH6", "PH7"; 1150 function = "uart5"; 1151 }; 1152 1153 /omit-if-no-ref/ 1154 uart5_pi_pins: uart5-pi-pins { 1155 pins = "PI10", "PI11"; 1156 function = "uart5"; 1157 }; 1158 1159 /omit-if-no-ref/ 1160 uart6_pa_pins: uart6-pa-pins { 1161 pins = "PA12", "PA13"; 1162 function = "uart6"; 1163 }; 1164 1165 /omit-if-no-ref/ 1166 uart6_pi_pins: uart6-pi-pins { 1167 pins = "PI12", "PI13"; 1168 function = "uart6"; 1169 }; 1170 1171 /omit-if-no-ref/ 1172 uart7_pa_pins: uart7-pa-pins { 1173 pins = "PA14", "PA15"; 1174 function = "uart7"; 1175 }; 1176 1177 /omit-if-no-ref/ 1178 uart7_pi_pins: uart7-pi-pins { 1179 pins = "PI20", "PI21"; 1180 function = "uart7"; 1181 }; 1182 }; 1183 1184 timer@1c20c00 { 1185 compatible = "allwinner,sun4i-a10-timer"; 1186 reg = <0x01c20c00 0x90>; 1187 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&osc24M>; 1194 }; 1195 1196 wdt: watchdog@1c20c90 { 1197 compatible = "allwinner,sun4i-a10-wdt"; 1198 reg = <0x01c20c90 0x10>; 1199 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&osc24M>; 1201 }; 1202 1203 rtc: rtc@1c20d00 { 1204 compatible = "allwinner,sun7i-a20-rtc"; 1205 reg = <0x01c20d00 0x20>; 1206 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1207 }; 1208 1209 pwm: pwm@1c20e00 { 1210 compatible = "allwinner,sun7i-a20-pwm"; 1211 reg = <0x01c20e00 0xc>; 1212 clocks = <&osc24M>; 1213 #pwm-cells = <3>; 1214 status = "disabled"; 1215 }; 1216 1217 spdif: spdif@1c21000 { 1218 #sound-dai-cells = <0>; 1219 compatible = "allwinner,sun4i-a10-spdif"; 1220 reg = <0x01c21000 0x400>; 1221 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; 1223 clock-names = "apb", "spdif"; 1224 dmas = <&dma SUN4I_DMA_NORMAL 2>, 1225 <&dma SUN4I_DMA_NORMAL 2>; 1226 dma-names = "rx", "tx"; 1227 status = "disabled"; 1228 }; 1229 1230 ir0: ir@1c21800 { 1231 compatible = "allwinner,sun4i-a10-ir"; 1232 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; 1233 clock-names = "apb", "ir"; 1234 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1235 reg = <0x01c21800 0x40>; 1236 status = "disabled"; 1237 }; 1238 1239 ir1: ir@1c21c00 { 1240 compatible = "allwinner,sun4i-a10-ir"; 1241 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; 1242 clock-names = "apb", "ir"; 1243 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1244 reg = <0x01c21c00 0x40>; 1245 status = "disabled"; 1246 }; 1247 1248 i2s1: i2s@1c22000 { 1249 #sound-dai-cells = <0>; 1250 compatible = "allwinner,sun4i-a10-i2s"; 1251 reg = <0x01c22000 0x400>; 1252 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; 1254 clock-names = "apb", "mod"; 1255 dmas = <&dma SUN4I_DMA_NORMAL 4>, 1256 <&dma SUN4I_DMA_NORMAL 4>; 1257 dma-names = "rx", "tx"; 1258 status = "disabled"; 1259 }; 1260 1261 i2s0: i2s@1c22400 { 1262 #sound-dai-cells = <0>; 1263 compatible = "allwinner,sun4i-a10-i2s"; 1264 reg = <0x01c22400 0x400>; 1265 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; 1267 clock-names = "apb", "mod"; 1268 dmas = <&dma SUN4I_DMA_NORMAL 3>, 1269 <&dma SUN4I_DMA_NORMAL 3>; 1270 dma-names = "rx", "tx"; 1271 status = "disabled"; 1272 }; 1273 1274 lradc: lradc@1c22800 { 1275 compatible = "allwinner,sun4i-a10-lradc-keys"; 1276 reg = <0x01c22800 0x100>; 1277 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1278 status = "disabled"; 1279 }; 1280 1281 codec: codec@1c22c00 { 1282 #sound-dai-cells = <0>; 1283 compatible = "allwinner,sun7i-a20-codec"; 1284 reg = <0x01c22c00 0x40>; 1285 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1286 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 1287 clock-names = "apb", "codec"; 1288 dmas = <&dma SUN4I_DMA_NORMAL 19>, 1289 <&dma SUN4I_DMA_NORMAL 19>; 1290 dma-names = "rx", "tx"; 1291 status = "disabled"; 1292 }; 1293 1294 sid: eeprom@1c23800 { 1295 compatible = "allwinner,sun7i-a20-sid"; 1296 reg = <0x01c23800 0x200>; 1297 }; 1298 1299 i2s2: i2s@1c24400 { 1300 #sound-dai-cells = <0>; 1301 compatible = "allwinner,sun4i-a10-i2s"; 1302 reg = <0x01c24400 0x400>; 1303 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; 1305 clock-names = "apb", "mod"; 1306 dmas = <&dma SUN4I_DMA_NORMAL 6>, 1307 <&dma SUN4I_DMA_NORMAL 6>; 1308 dma-names = "rx", "tx"; 1309 status = "disabled"; 1310 }; 1311 1312 rtp: rtp@1c25000 { 1313 compatible = "allwinner,sun5i-a13-ts"; 1314 reg = <0x01c25000 0x100>; 1315 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1316 #thermal-sensor-cells = <0>; 1317 }; 1318 1319 uart0: serial@1c28000 { 1320 compatible = "snps,dw-apb-uart"; 1321 reg = <0x01c28000 0x400>; 1322 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1323 reg-shift = <2>; 1324 reg-io-width = <4>; 1325 clocks = <&ccu CLK_APB1_UART0>; 1326 status = "disabled"; 1327 }; 1328 1329 uart1: serial@1c28400 { 1330 compatible = "snps,dw-apb-uart"; 1331 reg = <0x01c28400 0x400>; 1332 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1333 reg-shift = <2>; 1334 reg-io-width = <4>; 1335 clocks = <&ccu CLK_APB1_UART1>; 1336 status = "disabled"; 1337 }; 1338 1339 uart2: serial@1c28800 { 1340 compatible = "snps,dw-apb-uart"; 1341 reg = <0x01c28800 0x400>; 1342 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1343 reg-shift = <2>; 1344 reg-io-width = <4>; 1345 clocks = <&ccu CLK_APB1_UART2>; 1346 status = "disabled"; 1347 }; 1348 1349 uart3: serial@1c28c00 { 1350 compatible = "snps,dw-apb-uart"; 1351 reg = <0x01c28c00 0x400>; 1352 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1353 reg-shift = <2>; 1354 reg-io-width = <4>; 1355 clocks = <&ccu CLK_APB1_UART3>; 1356 status = "disabled"; 1357 }; 1358 1359 uart4: serial@1c29000 { 1360 compatible = "snps,dw-apb-uart"; 1361 reg = <0x01c29000 0x400>; 1362 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1363 reg-shift = <2>; 1364 reg-io-width = <4>; 1365 clocks = <&ccu CLK_APB1_UART4>; 1366 status = "disabled"; 1367 }; 1368 1369 uart5: serial@1c29400 { 1370 compatible = "snps,dw-apb-uart"; 1371 reg = <0x01c29400 0x400>; 1372 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1373 reg-shift = <2>; 1374 reg-io-width = <4>; 1375 clocks = <&ccu CLK_APB1_UART5>; 1376 status = "disabled"; 1377 }; 1378 1379 uart6: serial@1c29800 { 1380 compatible = "snps,dw-apb-uart"; 1381 reg = <0x01c29800 0x400>; 1382 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1383 reg-shift = <2>; 1384 reg-io-width = <4>; 1385 clocks = <&ccu CLK_APB1_UART6>; 1386 status = "disabled"; 1387 }; 1388 1389 uart7: serial@1c29c00 { 1390 compatible = "snps,dw-apb-uart"; 1391 reg = <0x01c29c00 0x400>; 1392 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1393 reg-shift = <2>; 1394 reg-io-width = <4>; 1395 clocks = <&ccu CLK_APB1_UART7>; 1396 status = "disabled"; 1397 }; 1398 1399 ps20: ps2@1c2a000 { 1400 compatible = "allwinner,sun4i-a10-ps2"; 1401 reg = <0x01c2a000 0x400>; 1402 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1403 clocks = <&ccu CLK_APB1_PS20>; 1404 status = "disabled"; 1405 }; 1406 1407 ps21: ps2@1c2a400 { 1408 compatible = "allwinner,sun4i-a10-ps2"; 1409 reg = <0x01c2a400 0x400>; 1410 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&ccu CLK_APB1_PS21>; 1412 status = "disabled"; 1413 }; 1414 1415 i2c0: i2c@1c2ac00 { 1416 compatible = "allwinner,sun7i-a20-i2c", 1417 "allwinner,sun4i-a10-i2c"; 1418 reg = <0x01c2ac00 0x400>; 1419 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&ccu CLK_APB1_I2C0>; 1421 pinctrl-names = "default"; 1422 pinctrl-0 = <&i2c0_pins>; 1423 status = "disabled"; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 }; 1427 1428 i2c1: i2c@1c2b000 { 1429 compatible = "allwinner,sun7i-a20-i2c", 1430 "allwinner,sun4i-a10-i2c"; 1431 reg = <0x01c2b000 0x400>; 1432 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&ccu CLK_APB1_I2C1>; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&i2c1_pins>; 1436 status = "disabled"; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 }; 1440 1441 i2c2: i2c@1c2b400 { 1442 compatible = "allwinner,sun7i-a20-i2c", 1443 "allwinner,sun4i-a10-i2c"; 1444 reg = <0x01c2b400 0x400>; 1445 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&ccu CLK_APB1_I2C2>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&i2c2_pins>; 1449 status = "disabled"; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 }; 1453 1454 i2c3: i2c@1c2b800 { 1455 compatible = "allwinner,sun7i-a20-i2c", 1456 "allwinner,sun4i-a10-i2c"; 1457 reg = <0x01c2b800 0x400>; 1458 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&ccu CLK_APB1_I2C3>; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&i2c3_pins>; 1462 status = "disabled"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 }; 1466 1467 can0: can@1c2bc00 { 1468 compatible = "allwinner,sun7i-a20-can", 1469 "allwinner,sun4i-a10-can"; 1470 reg = <0x01c2bc00 0x400>; 1471 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1472 clocks = <&ccu CLK_APB1_CAN>; 1473 status = "disabled"; 1474 }; 1475 1476 i2c4: i2c@1c2c000 { 1477 compatible = "allwinner,sun7i-a20-i2c", 1478 "allwinner,sun4i-a10-i2c"; 1479 reg = <0x01c2c000 0x400>; 1480 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1481 clocks = <&ccu CLK_APB1_I2C4>; 1482 status = "disabled"; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 }; 1486 1487 mali: gpu@1c40000 { 1488 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 1489 reg = <0x01c40000 0x10000>; 1490 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1497 interrupt-names = "gp", 1498 "gpmmu", 1499 "pp0", 1500 "ppmmu0", 1501 "pp1", 1502 "ppmmu1", 1503 "pmu"; 1504 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; 1505 clock-names = "bus", "core"; 1506 resets = <&ccu RST_GPU>; 1507 1508 assigned-clocks = <&ccu CLK_GPU>; 1509 assigned-clock-rates = <384000000>; 1510 }; 1511 1512 gmac: ethernet@1c50000 { 1513 compatible = "allwinner,sun7i-a20-gmac"; 1514 reg = <0x01c50000 0x10000>; 1515 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1516 interrupt-names = "macirq"; 1517 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; 1518 clock-names = "stmmaceth", "allwinner_gmac_tx"; 1519 snps,pbl = <2>; 1520 snps,fixed-burst; 1521 snps,force_sf_dma_mode; 1522 status = "disabled"; 1523 1524 gmac_mdio: mdio { 1525 compatible = "snps,dwmac-mdio"; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 }; 1529 }; 1530 1531 hstimer@1c60000 { 1532 compatible = "allwinner,sun7i-a20-hstimer"; 1533 reg = <0x01c60000 0x1000>; 1534 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1538 clocks = <&ccu CLK_AHB_HSTIMER>; 1539 }; 1540 1541 gic: interrupt-controller@1c81000 { 1542 compatible = "arm,gic-400"; 1543 reg = <0x01c81000 0x1000>, 1544 <0x01c82000 0x2000>, 1545 <0x01c84000 0x2000>, 1546 <0x01c86000 0x2000>; 1547 interrupt-controller; 1548 #interrupt-cells = <3>; 1549 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1550 }; 1551 1552 fe0: display-frontend@1e00000 { 1553 compatible = "allwinner,sun7i-a20-display-frontend"; 1554 reg = <0x01e00000 0x20000>; 1555 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1556 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, 1557 <&ccu CLK_DRAM_DE_FE0>; 1558 clock-names = "ahb", "mod", 1559 "ram"; 1560 resets = <&ccu RST_DE_FE0>; 1561 1562 ports { 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 1566 fe0_out: port@1 { 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 reg = <1>; 1570 1571 fe0_out_be0: endpoint@0 { 1572 reg = <0>; 1573 remote-endpoint = <&be0_in_fe0>; 1574 }; 1575 1576 fe0_out_be1: endpoint@1 { 1577 reg = <1>; 1578 remote-endpoint = <&be1_in_fe0>; 1579 }; 1580 }; 1581 }; 1582 }; 1583 1584 fe1: display-frontend@1e20000 { 1585 compatible = "allwinner,sun7i-a20-display-frontend"; 1586 reg = <0x01e20000 0x20000>; 1587 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1588 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, 1589 <&ccu CLK_DRAM_DE_FE1>; 1590 clock-names = "ahb", "mod", 1591 "ram"; 1592 resets = <&ccu RST_DE_FE1>; 1593 1594 ports { 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 1598 fe1_out: port@1 { 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 reg = <1>; 1602 1603 fe1_out_be0: endpoint@0 { 1604 reg = <0>; 1605 remote-endpoint = <&be0_in_fe1>; 1606 }; 1607 1608 fe1_out_be1: endpoint@1 { 1609 reg = <1>; 1610 remote-endpoint = <&be1_in_fe1>; 1611 }; 1612 }; 1613 }; 1614 }; 1615 1616 be1: display-backend@1e40000 { 1617 compatible = "allwinner,sun7i-a20-display-backend"; 1618 reg = <0x01e40000 0x10000>; 1619 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1620 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, 1621 <&ccu CLK_DRAM_DE_BE1>; 1622 clock-names = "ahb", "mod", 1623 "ram"; 1624 resets = <&ccu RST_DE_BE1>; 1625 1626 ports { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 1630 be1_in: port@0 { 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 reg = <0>; 1634 1635 be1_in_fe0: endpoint@0 { 1636 reg = <0>; 1637 remote-endpoint = <&fe0_out_be1>; 1638 }; 1639 1640 be1_in_fe1: endpoint@1 { 1641 reg = <1>; 1642 remote-endpoint = <&fe1_out_be1>; 1643 }; 1644 }; 1645 1646 be1_out: port@1 { 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 reg = <1>; 1650 1651 be1_out_tcon0: endpoint@0 { 1652 reg = <0>; 1653 remote-endpoint = <&tcon0_in_be1>; 1654 }; 1655 1656 be1_out_tcon1: endpoint@1 { 1657 reg = <1>; 1658 remote-endpoint = <&tcon1_in_be1>; 1659 }; 1660 }; 1661 }; 1662 }; 1663 1664 be0: display-backend@1e60000 { 1665 compatible = "allwinner,sun7i-a20-display-backend"; 1666 reg = <0x01e60000 0x10000>; 1667 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 1669 <&ccu CLK_DRAM_DE_BE0>; 1670 clock-names = "ahb", "mod", 1671 "ram"; 1672 resets = <&ccu RST_DE_BE0>; 1673 1674 ports { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 be0_in: port@0 { 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 reg = <0>; 1682 1683 be0_in_fe0: endpoint@0 { 1684 reg = <0>; 1685 remote-endpoint = <&fe0_out_be0>; 1686 }; 1687 1688 be0_in_fe1: endpoint@1 { 1689 reg = <1>; 1690 remote-endpoint = <&fe1_out_be0>; 1691 }; 1692 }; 1693 1694 be0_out: port@1 { 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 reg = <1>; 1698 1699 be0_out_tcon0: endpoint@0 { 1700 reg = <0>; 1701 remote-endpoint = <&tcon0_in_be0>; 1702 }; 1703 1704 be0_out_tcon1: endpoint@1 { 1705 reg = <1>; 1706 remote-endpoint = <&tcon1_in_be0>; 1707 }; 1708 }; 1709 }; 1710 }; 1711 }; 1712}; 1713