1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra124-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x0 0x80000000 0x0 0x0>; 22 }; 23 24 pcie@1003000 { 25 compatible = "nvidia,tegra124-pcie"; 26 device_type = "pci"; 27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 30 reg-names = "pads", "afi", "cs"; 31 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 32 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 33 interrupt-names = "intr", "msi"; 34 35 #interrupt-cells = <1>; 36 interrupt-map-mask = <0 0 0 0>; 37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 38 39 bus-range = <0x00 0xff>; 40 #address-cells = <3>; 41 #size-cells = <2>; 42 43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 48 49 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 50 <&tegra_car TEGRA124_CLK_AFI>, 51 <&tegra_car TEGRA124_CLK_PLL_E>, 52 <&tegra_car TEGRA124_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 status = "disabled"; 59 60 pci@1,0 { 61 device_type = "pci"; 62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 63 reg = <0x000800 0 0 0 0>; 64 bus-range = <0x00 0xff>; 65 status = "disabled"; 66 67 #address-cells = <3>; 68 #size-cells = <2>; 69 ranges; 70 71 nvidia,num-lanes = <2>; 72 }; 73 74 pci@2,0 { 75 device_type = "pci"; 76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 77 reg = <0x001000 0 0 0 0>; 78 bus-range = <0x00 0xff>; 79 status = "disabled"; 80 81 #address-cells = <3>; 82 #size-cells = <2>; 83 ranges; 84 85 nvidia,num-lanes = <1>; 86 }; 87 }; 88 89 host1x@50000000 { 90 compatible = "nvidia,tegra124-host1x"; 91 reg = <0x0 0x50000000 0x0 0x00034000>; 92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 94 interrupt-names = "syncpt", "host1x"; 95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 96 clock-names = "host1x"; 97 resets = <&tegra_car 28>; 98 reset-names = "host1x"; 99 iommus = <&mc TEGRA_SWGROUP_HC>; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 105 106 dc@54200000 { 107 compatible = "nvidia,tegra124-dc"; 108 reg = <0x0 0x54200000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 111 clock-names = "dc"; 112 resets = <&tegra_car 27>; 113 reset-names = "dc"; 114 115 iommus = <&mc TEGRA_SWGROUP_DC>; 116 117 nvidia,head = <0>; 118 119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, 120 <&mc TEGRA124_MC_DISPLAY0B &emc>, 121 <&mc TEGRA124_MC_DISPLAY0C &emc>, 122 <&mc TEGRA124_MC_DISPLAYHC &emc>, 123 <&mc TEGRA124_MC_DISPLAYD &emc>, 124 <&mc TEGRA124_MC_DISPLAYT &emc>; 125 interconnect-names = "wina", 126 "winb", 127 "winc", 128 "cursor", 129 "wind", 130 "wint"; 131 }; 132 133 dc@54240000 { 134 compatible = "nvidia,tegra124-dc"; 135 reg = <0x0 0x54240000 0x0 0x00040000>; 136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 138 clock-names = "dc"; 139 resets = <&tegra_car 26>; 140 reset-names = "dc"; 141 142 iommus = <&mc TEGRA_SWGROUP_DCB>; 143 144 nvidia,head = <1>; 145 146 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, 147 <&mc TEGRA124_MC_DISPLAY0BB &emc>, 148 <&mc TEGRA124_MC_DISPLAY0CB &emc>, 149 <&mc TEGRA124_MC_DISPLAYHCB &emc>; 150 interconnect-names = "wina", 151 "winb", 152 "winc", 153 "cursor"; 154 }; 155 156 hdmi: hdmi@54280000 { 157 compatible = "nvidia,tegra124-hdmi"; 158 reg = <0x0 0x54280000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 161 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 162 clock-names = "hdmi", "parent"; 163 resets = <&tegra_car 51>; 164 reset-names = "hdmi"; 165 status = "disabled"; 166 }; 167 168 vic@54340000 { 169 compatible = "nvidia,tegra124-vic"; 170 reg = <0x0 0x54340000 0x0 0x00040000>; 171 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&tegra_car TEGRA124_CLK_VIC03>; 173 clock-names = "vic"; 174 resets = <&tegra_car 178>; 175 reset-names = "vic"; 176 177 iommus = <&mc TEGRA_SWGROUP_VIC>; 178 }; 179 180 sor@54540000 { 181 compatible = "nvidia,tegra124-sor"; 182 reg = <0x0 0x54540000 0x0 0x00040000>; 183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 185 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 186 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 187 <&tegra_car TEGRA124_CLK_PLL_DP>, 188 <&tegra_car TEGRA124_CLK_CLK_M>; 189 clock-names = "sor", "out", "parent", "dp", "safe"; 190 resets = <&tegra_car 182>; 191 reset-names = "sor"; 192 status = "disabled"; 193 }; 194 195 dpaux: dpaux@545c0000 { 196 compatible = "nvidia,tegra124-dpaux"; 197 reg = <0x0 0x545c0000 0x0 0x00040000>; 198 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 200 <&tegra_car TEGRA124_CLK_PLL_DP>; 201 clock-names = "dpaux", "parent"; 202 resets = <&tegra_car 181>; 203 reset-names = "dpaux"; 204 status = "disabled"; 205 206 i2c-bus { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 }; 210 }; 211 }; 212 213 gic: interrupt-controller@50041000 { 214 compatible = "arm,cortex-a15-gic"; 215 #interrupt-cells = <3>; 216 interrupt-controller; 217 reg = <0x0 0x50041000 0x0 0x1000>, 218 <0x0 0x50042000 0x0 0x1000>, 219 <0x0 0x50044000 0x0 0x2000>, 220 <0x0 0x50046000 0x0 0x2000>; 221 interrupts = <GIC_PPI 9 222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 223 interrupt-parent = <&gic>; 224 }; 225 226 /* 227 * Please keep the following 0, notation in place as a former mainline 228 * U-Boot version was looking for that particular notation in order to 229 * perform required fix-ups on that GPU node. 230 */ 231 gpu@0,57000000 { 232 compatible = "nvidia,gk20a"; 233 reg = <0x0 0x57000000 0x0 0x01000000>, 234 <0x0 0x58000000 0x0 0x01000000>; 235 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "stall", "nonstall"; 238 clocks = <&tegra_car TEGRA124_CLK_GPU>, 239 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 240 clock-names = "gpu", "pwr"; 241 resets = <&tegra_car 184>; 242 reset-names = "gpu"; 243 244 iommus = <&mc TEGRA_SWGROUP_GPU>; 245 246 status = "disabled"; 247 }; 248 249 lic: interrupt-controller@60004000 { 250 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 251 reg = <0x0 0x60004000 0x0 0x100>, 252 <0x0 0x60004100 0x0 0x100>, 253 <0x0 0x60004200 0x0 0x100>, 254 <0x0 0x60004300 0x0 0x100>, 255 <0x0 0x60004400 0x0 0x100>; 256 interrupt-controller; 257 #interrupt-cells = <3>; 258 interrupt-parent = <&gic>; 259 }; 260 261 timer@60005000 { 262 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 263 reg = <0x0 0x60005000 0x0 0x400>; 264 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 271 }; 272 273 tegra_car: clock@60006000 { 274 compatible = "nvidia,tegra124-car"; 275 reg = <0x0 0x60006000 0x0 0x1000>; 276 #clock-cells = <1>; 277 #reset-cells = <1>; 278 nvidia,external-memory-controller = <&emc>; 279 }; 280 281 flow-controller@60007000 { 282 compatible = "nvidia,tegra124-flowctrl"; 283 reg = <0x0 0x60007000 0x0 0x1000>; 284 }; 285 286 actmon@6000c800 { 287 compatible = "nvidia,tegra124-actmon"; 288 reg = <0x0 0x6000c800 0x0 0x400>; 289 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 291 <&tegra_car TEGRA124_CLK_EMC>; 292 clock-names = "actmon", "emc"; 293 resets = <&tegra_car 119>; 294 reset-names = "actmon"; 295 operating-points-v2 = <&emc_bw_dfs_opp_table>; 296 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 297 interconnect-names = "cpu-read"; 298 }; 299 300 gpio: gpio@6000d000 { 301 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 302 reg = <0x0 0x6000d000 0x0 0x1000>; 303 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 311 #gpio-cells = <2>; 312 gpio-controller; 313 #interrupt-cells = <2>; 314 interrupt-controller; 315 /* 316 gpio-ranges = <&pinmux 0 0 251>; 317 */ 318 }; 319 320 apbdma: dma@60020000 { 321 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 322 reg = <0x0 0x60020000 0x0 0x1400>; 323 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 356 resets = <&tegra_car 34>; 357 reset-names = "dma"; 358 #dma-cells = <1>; 359 }; 360 361 apbmisc@70000800 { 362 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 363 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 364 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 365 }; 366 367 pinmux: pinmux@70000868 { 368 compatible = "nvidia,tegra124-pinmux"; 369 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 370 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 371 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 372 }; 373 374 /* 375 * There are two serial driver i.e. 8250 based simple serial 376 * driver and APB DMA based serial driver for higher baudrate 377 * and performace. To enable the 8250 based driver, the compatible 378 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 379 * the APB DMA based serial driver, the compatible is 380 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 381 */ 382 uarta: serial@70006000 { 383 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 384 reg = <0x0 0x70006000 0x0 0x40>; 385 reg-shift = <2>; 386 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 388 resets = <&tegra_car 6>; 389 reset-names = "serial"; 390 dmas = <&apbdma 8>, <&apbdma 8>; 391 dma-names = "rx", "tx"; 392 status = "disabled"; 393 }; 394 395 uartb: serial@70006040 { 396 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 397 reg = <0x0 0x70006040 0x0 0x40>; 398 reg-shift = <2>; 399 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 401 resets = <&tegra_car 7>; 402 reset-names = "serial"; 403 dmas = <&apbdma 9>, <&apbdma 9>; 404 dma-names = "rx", "tx"; 405 status = "disabled"; 406 }; 407 408 uartc: serial@70006200 { 409 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 410 reg = <0x0 0x70006200 0x0 0x40>; 411 reg-shift = <2>; 412 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 414 resets = <&tegra_car 55>; 415 reset-names = "serial"; 416 dmas = <&apbdma 10>, <&apbdma 10>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 }; 420 421 uartd: serial@70006300 { 422 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 423 reg = <0x0 0x70006300 0x0 0x40>; 424 reg-shift = <2>; 425 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 427 resets = <&tegra_car 65>; 428 reset-names = "serial"; 429 dmas = <&apbdma 19>, <&apbdma 19>; 430 dma-names = "rx", "tx"; 431 status = "disabled"; 432 }; 433 434 pwm: pwm@7000a000 { 435 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 436 reg = <0x0 0x7000a000 0x0 0x100>; 437 #pwm-cells = <2>; 438 clocks = <&tegra_car TEGRA124_CLK_PWM>; 439 resets = <&tegra_car 17>; 440 reset-names = "pwm"; 441 status = "disabled"; 442 }; 443 444 i2c@7000c000 { 445 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 446 reg = <0x0 0x7000c000 0x0 0x100>; 447 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 451 clock-names = "div-clk"; 452 resets = <&tegra_car 12>; 453 reset-names = "i2c"; 454 dmas = <&apbdma 21>, <&apbdma 21>; 455 dma-names = "rx", "tx"; 456 status = "disabled"; 457 }; 458 459 i2c@7000c400 { 460 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 461 reg = <0x0 0x7000c400 0x0 0x100>; 462 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 466 clock-names = "div-clk"; 467 resets = <&tegra_car 54>; 468 reset-names = "i2c"; 469 dmas = <&apbdma 22>, <&apbdma 22>; 470 dma-names = "rx", "tx"; 471 status = "disabled"; 472 }; 473 474 i2c@7000c500 { 475 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 476 reg = <0x0 0x7000c500 0x0 0x100>; 477 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 481 clock-names = "div-clk"; 482 resets = <&tegra_car 67>; 483 reset-names = "i2c"; 484 dmas = <&apbdma 23>, <&apbdma 23>; 485 dma-names = "rx", "tx"; 486 status = "disabled"; 487 }; 488 489 i2c@7000c700 { 490 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 491 reg = <0x0 0x7000c700 0x0 0x100>; 492 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 496 clock-names = "div-clk"; 497 resets = <&tegra_car 103>; 498 reset-names = "i2c"; 499 dmas = <&apbdma 26>, <&apbdma 26>; 500 dma-names = "rx", "tx"; 501 status = "disabled"; 502 }; 503 504 i2c@7000d000 { 505 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 506 reg = <0x0 0x7000d000 0x0 0x100>; 507 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 511 clock-names = "div-clk"; 512 resets = <&tegra_car 47>; 513 reset-names = "i2c"; 514 dmas = <&apbdma 24>, <&apbdma 24>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 i2c@7000d100 { 520 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 521 reg = <0x0 0x7000d100 0x0 0x100>; 522 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 526 clock-names = "div-clk"; 527 resets = <&tegra_car 166>; 528 reset-names = "i2c"; 529 dmas = <&apbdma 30>, <&apbdma 30>; 530 dma-names = "rx", "tx"; 531 status = "disabled"; 532 }; 533 534 spi@7000d400 { 535 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 536 reg = <0x0 0x7000d400 0x0 0x200>; 537 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 541 clock-names = "spi"; 542 resets = <&tegra_car 41>; 543 reset-names = "spi"; 544 dmas = <&apbdma 15>, <&apbdma 15>; 545 dma-names = "rx", "tx"; 546 status = "disabled"; 547 }; 548 549 spi@7000d600 { 550 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 551 reg = <0x0 0x7000d600 0x0 0x200>; 552 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 556 clock-names = "spi"; 557 resets = <&tegra_car 44>; 558 reset-names = "spi"; 559 dmas = <&apbdma 16>, <&apbdma 16>; 560 dma-names = "rx", "tx"; 561 status = "disabled"; 562 }; 563 564 spi@7000d800 { 565 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 566 reg = <0x0 0x7000d800 0x0 0x200>; 567 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 571 clock-names = "spi"; 572 resets = <&tegra_car 46>; 573 reset-names = "spi"; 574 dmas = <&apbdma 17>, <&apbdma 17>; 575 dma-names = "rx", "tx"; 576 status = "disabled"; 577 }; 578 579 spi@7000da00 { 580 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 581 reg = <0x0 0x7000da00 0x0 0x200>; 582 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 586 clock-names = "spi"; 587 resets = <&tegra_car 68>; 588 reset-names = "spi"; 589 dmas = <&apbdma 18>, <&apbdma 18>; 590 dma-names = "rx", "tx"; 591 status = "disabled"; 592 }; 593 594 spi@7000dc00 { 595 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 596 reg = <0x0 0x7000dc00 0x0 0x200>; 597 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 601 clock-names = "spi"; 602 resets = <&tegra_car 104>; 603 reset-names = "spi"; 604 dmas = <&apbdma 27>, <&apbdma 27>; 605 dma-names = "rx", "tx"; 606 status = "disabled"; 607 }; 608 609 spi@7000de00 { 610 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 611 reg = <0x0 0x7000de00 0x0 0x200>; 612 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 616 clock-names = "spi"; 617 resets = <&tegra_car 105>; 618 reset-names = "spi"; 619 dmas = <&apbdma 28>, <&apbdma 28>; 620 dma-names = "rx", "tx"; 621 status = "disabled"; 622 }; 623 624 rtc@7000e000 { 625 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 626 reg = <0x0 0x7000e000 0x0 0x100>; 627 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&tegra_car TEGRA124_CLK_RTC>; 629 }; 630 631 tegra_pmc: pmc@7000e400 { 632 compatible = "nvidia,tegra124-pmc"; 633 reg = <0x0 0x7000e400 0x0 0x400>; 634 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 635 clock-names = "pclk", "clk32k_in"; 636 #clock-cells = <1>; 637 }; 638 639 fuse@7000f800 { 640 compatible = "nvidia,tegra124-efuse"; 641 reg = <0x0 0x7000f800 0x0 0x400>; 642 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 643 clock-names = "fuse"; 644 resets = <&tegra_car 39>; 645 reset-names = "fuse"; 646 }; 647 648 mc: memory-controller@70019000 { 649 compatible = "nvidia,tegra124-mc"; 650 reg = <0x0 0x70019000 0x0 0x1000>; 651 clocks = <&tegra_car TEGRA124_CLK_MC>; 652 clock-names = "mc"; 653 654 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 655 656 #iommu-cells = <1>; 657 #reset-cells = <1>; 658 #interconnect-cells = <1>; 659 }; 660 661 emc: external-memory-controller@7001b000 { 662 compatible = "nvidia,tegra124-emc"; 663 reg = <0x0 0x7001b000 0x0 0x1000>; 664 clocks = <&tegra_car TEGRA124_CLK_EMC>; 665 clock-names = "emc"; 666 667 nvidia,memory-controller = <&mc>; 668 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 669 670 #interconnect-cells = <0>; 671 }; 672 673 sata@70020000 { 674 compatible = "nvidia,tegra124-ahci"; 675 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 676 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 677 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&tegra_car TEGRA124_CLK_SATA>, 679 <&tegra_car TEGRA124_CLK_SATA_OOB>, 680 <&tegra_car TEGRA124_CLK_CML1>, 681 <&tegra_car TEGRA124_CLK_PLL_E>; 682 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 683 resets = <&tegra_car 124>, 684 <&tegra_car 129>, 685 <&tegra_car 123>; 686 reset-names = "sata", "sata-cold", "sata-oob"; 687 status = "disabled"; 688 }; 689 690 hda@70030000 { 691 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 692 reg = <0x0 0x70030000 0x0 0x10000>; 693 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&tegra_car TEGRA124_CLK_HDA>, 695 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 696 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 697 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 698 resets = <&tegra_car 125>, /* hda */ 699 <&tegra_car 128>, /* hda2hdmi */ 700 <&tegra_car 111>; /* hda2codec_2x */ 701 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 702 status = "disabled"; 703 }; 704 705 usb@70090000 { 706 compatible = "nvidia,tegra124-xusb"; 707 reg = <0x0 0x70090000 0x0 0x8000>, 708 <0x0 0x70098000 0x0 0x1000>, 709 <0x0 0x70099000 0x0 0x1000>; 710 reg-names = "hcd", "fpci", "ipfs"; 711 712 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 714 715 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 716 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 717 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 718 <&tegra_car TEGRA124_CLK_XUSB_SS>, 719 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 720 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 721 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 722 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 723 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 724 <&tegra_car TEGRA124_CLK_CLK_M>, 725 <&tegra_car TEGRA124_CLK_PLL_E>; 726 clock-names = "xusb_host", "xusb_host_src", 727 "xusb_falcon_src", "xusb_ss", 728 "xusb_ss_src", "xusb_ss_div2", 729 "xusb_hs_src", "xusb_fs_src", 730 "pll_u_480m", "clk_m", "pll_e"; 731 resets = <&tegra_car 89>, <&tegra_car 156>, 732 <&tegra_car 143>; 733 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 734 735 nvidia,xusb-padctl = <&padctl>; 736 737 status = "disabled"; 738 }; 739 740 padctl: padctl@7009f000 { 741 compatible = "nvidia,tegra124-xusb-padctl"; 742 reg = <0x0 0x7009f000 0x0 0x1000>; 743 resets = <&tegra_car 142>; 744 reset-names = "padctl"; 745 746 pads { 747 usb2 { 748 status = "disabled"; 749 750 lanes { 751 usb2-0 { 752 status = "disabled"; 753 #phy-cells = <0>; 754 }; 755 756 usb2-1 { 757 status = "disabled"; 758 #phy-cells = <0>; 759 }; 760 761 usb2-2 { 762 status = "disabled"; 763 #phy-cells = <0>; 764 }; 765 }; 766 }; 767 768 ulpi { 769 status = "disabled"; 770 771 lanes { 772 ulpi-0 { 773 status = "disabled"; 774 #phy-cells = <0>; 775 }; 776 }; 777 }; 778 779 hsic { 780 status = "disabled"; 781 782 lanes { 783 hsic-0 { 784 status = "disabled"; 785 #phy-cells = <0>; 786 }; 787 788 hsic-1 { 789 status = "disabled"; 790 #phy-cells = <0>; 791 }; 792 }; 793 }; 794 795 pcie { 796 status = "disabled"; 797 798 lanes { 799 pcie-0 { 800 status = "disabled"; 801 #phy-cells = <0>; 802 }; 803 804 pcie-1 { 805 status = "disabled"; 806 #phy-cells = <0>; 807 }; 808 809 pcie-2 { 810 status = "disabled"; 811 #phy-cells = <0>; 812 }; 813 814 pcie-3 { 815 status = "disabled"; 816 #phy-cells = <0>; 817 }; 818 819 pcie-4 { 820 status = "disabled"; 821 #phy-cells = <0>; 822 }; 823 }; 824 }; 825 826 sata { 827 status = "disabled"; 828 829 lanes { 830 sata-0 { 831 status = "disabled"; 832 #phy-cells = <0>; 833 }; 834 }; 835 }; 836 }; 837 838 ports { 839 usb2-0 { 840 status = "disabled"; 841 }; 842 843 usb2-1 { 844 status = "disabled"; 845 }; 846 847 usb2-2 { 848 status = "disabled"; 849 }; 850 851 ulpi-0 { 852 status = "disabled"; 853 }; 854 855 hsic-0 { 856 status = "disabled"; 857 }; 858 859 hsic-1 { 860 status = "disabled"; 861 }; 862 863 usb3-0 { 864 status = "disabled"; 865 }; 866 867 usb3-1 { 868 status = "disabled"; 869 }; 870 }; 871 }; 872 873 mmc@700b0000 { 874 compatible = "nvidia,tegra124-sdhci"; 875 reg = <0x0 0x700b0000 0x0 0x200>; 876 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 878 clock-names = "sdhci"; 879 resets = <&tegra_car 14>; 880 reset-names = "sdhci"; 881 status = "disabled"; 882 }; 883 884 mmc@700b0200 { 885 compatible = "nvidia,tegra124-sdhci"; 886 reg = <0x0 0x700b0200 0x0 0x200>; 887 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 889 clock-names = "sdhci"; 890 resets = <&tegra_car 9>; 891 reset-names = "sdhci"; 892 status = "disabled"; 893 }; 894 895 mmc@700b0400 { 896 compatible = "nvidia,tegra124-sdhci"; 897 reg = <0x0 0x700b0400 0x0 0x200>; 898 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 900 clock-names = "sdhci"; 901 resets = <&tegra_car 69>; 902 reset-names = "sdhci"; 903 status = "disabled"; 904 }; 905 906 mmc@700b0600 { 907 compatible = "nvidia,tegra124-sdhci"; 908 reg = <0x0 0x700b0600 0x0 0x200>; 909 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 911 clock-names = "sdhci"; 912 resets = <&tegra_car 15>; 913 reset-names = "sdhci"; 914 status = "disabled"; 915 }; 916 917 cec@70015000 { 918 compatible = "nvidia,tegra124-cec"; 919 reg = <0x0 0x70015000 0x0 0x00001000>; 920 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&tegra_car TEGRA124_CLK_CEC>; 922 clock-names = "cec"; 923 status = "disabled"; 924 hdmi-phandle = <&hdmi>; 925 }; 926 927 soctherm: thermal-sensor@700e2000 { 928 compatible = "nvidia,tegra124-soctherm"; 929 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 930 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 931 reg-names = "soctherm-reg", "car-reg"; 932 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "thermal", "edp"; 935 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 936 <&tegra_car TEGRA124_CLK_SOC_THERM>; 937 clock-names = "tsensor", "soctherm"; 938 resets = <&tegra_car 78>; 939 reset-names = "soctherm"; 940 #thermal-sensor-cells = <1>; 941 942 throttle-cfgs { 943 throttle_heavy: heavy { 944 nvidia,priority = <100>; 945 nvidia,cpu-throt-percent = <85>; 946 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 947 948 #cooling-cells = <2>; 949 }; 950 }; 951 }; 952 953 dfll: clock@70110000 { 954 compatible = "nvidia,tegra124-dfll"; 955 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 956 <0 0x70110000 0 0x100>, /* I2C output control */ 957 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 958 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 959 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 961 <&tegra_car TEGRA124_CLK_DFLL_REF>, 962 <&tegra_car TEGRA124_CLK_I2C5>; 963 clock-names = "soc", "ref", "i2c"; 964 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 965 reset-names = "dvco"; 966 #clock-cells = <0>; 967 clock-output-names = "dfllCPU_out"; 968 nvidia,sample-rate = <12500>; 969 nvidia,droop-ctrl = <0x00000f00>; 970 nvidia,force-mode = <1>; 971 nvidia,cf = <10>; 972 nvidia,ci = <0>; 973 nvidia,cg = <2>; 974 status = "disabled"; 975 }; 976 977 ahub@70300000 { 978 compatible = "nvidia,tegra124-ahub"; 979 reg = <0x0 0x70300000 0x0 0x200>, 980 <0x0 0x70300800 0x0 0x800>, 981 <0x0 0x70300200 0x0 0x600>; 982 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 984 <&tegra_car TEGRA124_CLK_APBIF>; 985 clock-names = "d_audio", "apbif"; 986 resets = <&tegra_car 106>, /* d_audio */ 987 <&tegra_car 107>, /* apbif */ 988 <&tegra_car 30>, /* i2s0 */ 989 <&tegra_car 11>, /* i2s1 */ 990 <&tegra_car 18>, /* i2s2 */ 991 <&tegra_car 101>, /* i2s3 */ 992 <&tegra_car 102>, /* i2s4 */ 993 <&tegra_car 108>, /* dam0 */ 994 <&tegra_car 109>, /* dam1 */ 995 <&tegra_car 110>, /* dam2 */ 996 <&tegra_car 10>, /* spdif */ 997 <&tegra_car 153>, /* amx */ 998 <&tegra_car 185>, /* amx1 */ 999 <&tegra_car 154>, /* adx */ 1000 <&tegra_car 180>, /* adx1 */ 1001 <&tegra_car 186>, /* afc0 */ 1002 <&tegra_car 187>, /* afc1 */ 1003 <&tegra_car 188>, /* afc2 */ 1004 <&tegra_car 189>, /* afc3 */ 1005 <&tegra_car 190>, /* afc4 */ 1006 <&tegra_car 191>; /* afc5 */ 1007 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1008 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1009 "spdif", "amx", "amx1", "adx", "adx1", 1010 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 1011 dmas = <&apbdma 1>, <&apbdma 1>, 1012 <&apbdma 2>, <&apbdma 2>, 1013 <&apbdma 3>, <&apbdma 3>, 1014 <&apbdma 4>, <&apbdma 4>, 1015 <&apbdma 6>, <&apbdma 6>, 1016 <&apbdma 7>, <&apbdma 7>, 1017 <&apbdma 12>, <&apbdma 12>, 1018 <&apbdma 13>, <&apbdma 13>, 1019 <&apbdma 14>, <&apbdma 14>, 1020 <&apbdma 29>, <&apbdma 29>; 1021 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1022 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1023 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1024 "rx9", "tx9"; 1025 ranges; 1026 #address-cells = <2>; 1027 #size-cells = <2>; 1028 1029 tegra_i2s0: i2s@70301000 { 1030 compatible = "nvidia,tegra124-i2s"; 1031 reg = <0x0 0x70301000 0x0 0x100>; 1032 nvidia,ahub-cif-ids = <4 4>; 1033 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1034 resets = <&tegra_car 30>; 1035 reset-names = "i2s"; 1036 status = "disabled"; 1037 }; 1038 1039 tegra_i2s1: i2s@70301100 { 1040 compatible = "nvidia,tegra124-i2s"; 1041 reg = <0x0 0x70301100 0x0 0x100>; 1042 nvidia,ahub-cif-ids = <5 5>; 1043 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1044 resets = <&tegra_car 11>; 1045 reset-names = "i2s"; 1046 status = "disabled"; 1047 }; 1048 1049 tegra_i2s2: i2s@70301200 { 1050 compatible = "nvidia,tegra124-i2s"; 1051 reg = <0x0 0x70301200 0x0 0x100>; 1052 nvidia,ahub-cif-ids = <6 6>; 1053 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1054 resets = <&tegra_car 18>; 1055 reset-names = "i2s"; 1056 status = "disabled"; 1057 }; 1058 1059 tegra_i2s3: i2s@70301300 { 1060 compatible = "nvidia,tegra124-i2s"; 1061 reg = <0x0 0x70301300 0x0 0x100>; 1062 nvidia,ahub-cif-ids = <7 7>; 1063 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1064 resets = <&tegra_car 101>; 1065 reset-names = "i2s"; 1066 status = "disabled"; 1067 }; 1068 1069 tegra_i2s4: i2s@70301400 { 1070 compatible = "nvidia,tegra124-i2s"; 1071 reg = <0x0 0x70301400 0x0 0x100>; 1072 nvidia,ahub-cif-ids = <8 8>; 1073 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1074 resets = <&tegra_car 102>; 1075 reset-names = "i2s"; 1076 status = "disabled"; 1077 }; 1078 }; 1079 1080 usb@7d000000 { 1081 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1082 reg = <0x0 0x7d000000 0x0 0x4000>; 1083 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1084 phy_type = "utmi"; 1085 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1086 resets = <&tegra_car 22>; 1087 reset-names = "usb"; 1088 nvidia,phy = <&phy1>; 1089 status = "disabled"; 1090 }; 1091 1092 phy1: usb-phy@7d000000 { 1093 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1094 reg = <0x0 0x7d000000 0x0 0x4000>, 1095 <0x0 0x7d000000 0x0 0x4000>; 1096 phy_type = "utmi"; 1097 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1098 <&tegra_car TEGRA124_CLK_PLL_U>, 1099 <&tegra_car TEGRA124_CLK_USBD>; 1100 clock-names = "reg", "pll_u", "utmi-pads"; 1101 resets = <&tegra_car 22>, <&tegra_car 22>; 1102 reset-names = "usb", "utmi-pads"; 1103 #phy-cells = <0>; 1104 nvidia,hssync-start-delay = <0>; 1105 nvidia,idle-wait-delay = <17>; 1106 nvidia,elastic-limit = <16>; 1107 nvidia,term-range-adj = <6>; 1108 nvidia,xcvr-setup = <9>; 1109 nvidia,xcvr-lsfslew = <0>; 1110 nvidia,xcvr-lsrslew = <3>; 1111 nvidia,hssquelch-level = <2>; 1112 nvidia,hsdiscon-level = <5>; 1113 nvidia,xcvr-hsslew = <12>; 1114 nvidia,has-utmi-pad-registers; 1115 status = "disabled"; 1116 }; 1117 1118 usb@7d004000 { 1119 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1120 reg = <0x0 0x7d004000 0x0 0x4000>; 1121 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1122 phy_type = "utmi"; 1123 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1124 resets = <&tegra_car 58>; 1125 reset-names = "usb"; 1126 nvidia,phy = <&phy2>; 1127 status = "disabled"; 1128 }; 1129 1130 phy2: usb-phy@7d004000 { 1131 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1132 reg = <0x0 0x7d004000 0x0 0x4000>, 1133 <0x0 0x7d000000 0x0 0x4000>; 1134 phy_type = "utmi"; 1135 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1136 <&tegra_car TEGRA124_CLK_PLL_U>, 1137 <&tegra_car TEGRA124_CLK_USBD>; 1138 clock-names = "reg", "pll_u", "utmi-pads"; 1139 resets = <&tegra_car 58>, <&tegra_car 22>; 1140 reset-names = "usb", "utmi-pads"; 1141 #phy-cells = <0>; 1142 nvidia,hssync-start-delay = <0>; 1143 nvidia,idle-wait-delay = <17>; 1144 nvidia,elastic-limit = <16>; 1145 nvidia,term-range-adj = <6>; 1146 nvidia,xcvr-setup = <9>; 1147 nvidia,xcvr-lsfslew = <0>; 1148 nvidia,xcvr-lsrslew = <3>; 1149 nvidia,hssquelch-level = <2>; 1150 nvidia,hsdiscon-level = <5>; 1151 nvidia,xcvr-hsslew = <12>; 1152 status = "disabled"; 1153 }; 1154 1155 usb@7d008000 { 1156 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1157 reg = <0x0 0x7d008000 0x0 0x4000>; 1158 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1159 phy_type = "utmi"; 1160 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1161 resets = <&tegra_car 59>; 1162 reset-names = "usb"; 1163 nvidia,phy = <&phy3>; 1164 status = "disabled"; 1165 }; 1166 1167 phy3: usb-phy@7d008000 { 1168 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1169 reg = <0x0 0x7d008000 0x0 0x4000>, 1170 <0x0 0x7d000000 0x0 0x4000>; 1171 phy_type = "utmi"; 1172 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1173 <&tegra_car TEGRA124_CLK_PLL_U>, 1174 <&tegra_car TEGRA124_CLK_USBD>; 1175 clock-names = "reg", "pll_u", "utmi-pads"; 1176 resets = <&tegra_car 59>, <&tegra_car 22>; 1177 reset-names = "usb", "utmi-pads"; 1178 #phy-cells = <0>; 1179 nvidia,hssync-start-delay = <0>; 1180 nvidia,idle-wait-delay = <17>; 1181 nvidia,elastic-limit = <16>; 1182 nvidia,term-range-adj = <6>; 1183 nvidia,xcvr-setup = <9>; 1184 nvidia,xcvr-lsfslew = <0>; 1185 nvidia,xcvr-lsrslew = <3>; 1186 nvidia,hssquelch-level = <2>; 1187 nvidia,hsdiscon-level = <5>; 1188 nvidia,xcvr-hsslew = <12>; 1189 status = "disabled"; 1190 }; 1191 1192 cpus { 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 1196 cpu@0 { 1197 device_type = "cpu"; 1198 compatible = "arm,cortex-a15"; 1199 reg = <0>; 1200 1201 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 1202 <&tegra_car TEGRA124_CLK_CCLK_LP>, 1203 <&tegra_car TEGRA124_CLK_PLL_X>, 1204 <&tegra_car TEGRA124_CLK_PLL_P>, 1205 <&dfll>; 1206 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1207 /* FIXME: what's the actual transition time? */ 1208 clock-latency = <300000>; 1209 }; 1210 1211 cpu@1 { 1212 device_type = "cpu"; 1213 compatible = "arm,cortex-a15"; 1214 reg = <1>; 1215 }; 1216 1217 cpu@2 { 1218 device_type = "cpu"; 1219 compatible = "arm,cortex-a15"; 1220 reg = <2>; 1221 }; 1222 1223 cpu@3 { 1224 device_type = "cpu"; 1225 compatible = "arm,cortex-a15"; 1226 reg = <3>; 1227 }; 1228 }; 1229 1230 pmu { 1231 compatible = "arm,cortex-a15-pmu"; 1232 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1236 interrupt-affinity = <&{/cpus/cpu@0}>, 1237 <&{/cpus/cpu@1}>, 1238 <&{/cpus/cpu@2}>, 1239 <&{/cpus/cpu@3}>; 1240 }; 1241 1242 thermal-zones { 1243 cpu { 1244 polling-delay-passive = <1000>; 1245 polling-delay = <1000>; 1246 1247 thermal-sensors = 1248 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1249 1250 trips { 1251 cpu-shutdown-trip { 1252 temperature = <103000>; 1253 hysteresis = <0>; 1254 type = "critical"; 1255 }; 1256 cpu_throttle_trip: throttle-trip { 1257 temperature = <100000>; 1258 hysteresis = <1000>; 1259 type = "hot"; 1260 }; 1261 }; 1262 1263 cooling-maps { 1264 map0 { 1265 trip = <&cpu_throttle_trip>; 1266 cooling-device = <&throttle_heavy 1 1>; 1267 }; 1268 }; 1269 }; 1270 1271 mem { 1272 polling-delay-passive = <1000>; 1273 polling-delay = <1000>; 1274 1275 thermal-sensors = 1276 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1277 1278 trips { 1279 mem-shutdown-trip { 1280 temperature = <103000>; 1281 hysteresis = <0>; 1282 type = "critical"; 1283 }; 1284 mem-throttle-trip { 1285 temperature = <99000>; 1286 hysteresis = <1000>; 1287 type = "hot"; 1288 }; 1289 }; 1290 1291 cooling-maps { 1292 /* 1293 * There are currently no cooling maps, 1294 * because there are no cooling devices. 1295 */ 1296 }; 1297 }; 1298 1299 gpu { 1300 polling-delay-passive = <1000>; 1301 polling-delay = <1000>; 1302 1303 thermal-sensors = 1304 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1305 1306 trips { 1307 gpu-shutdown-trip { 1308 temperature = <101000>; 1309 hysteresis = <0>; 1310 type = "critical"; 1311 }; 1312 gpu_throttle_trip: throttle-trip { 1313 temperature = <99000>; 1314 hysteresis = <1000>; 1315 type = "hot"; 1316 }; 1317 }; 1318 1319 cooling-maps { 1320 map0 { 1321 trip = <&gpu_throttle_trip>; 1322 cooling-device = <&throttle_heavy 1 1>; 1323 }; 1324 }; 1325 }; 1326 1327 pllx { 1328 polling-delay-passive = <1000>; 1329 polling-delay = <1000>; 1330 1331 thermal-sensors = 1332 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1333 1334 trips { 1335 pllx-shutdown-trip { 1336 temperature = <103000>; 1337 hysteresis = <0>; 1338 type = "critical"; 1339 }; 1340 pllx-throttle-trip { 1341 temperature = <99000>; 1342 hysteresis = <1000>; 1343 type = "hot"; 1344 }; 1345 }; 1346 1347 cooling-maps { 1348 /* 1349 * There are currently no cooling maps, 1350 * because there are no cooling devices. 1351 */ 1352 }; 1353 }; 1354 }; 1355 1356 timer { 1357 compatible = "arm,armv7-timer"; 1358 interrupts = <GIC_PPI 13 1359 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1360 <GIC_PPI 14 1361 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1362 <GIC_PPI 11 1363 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1364 <GIC_PPI 10 1365 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1366 interrupt-parent = <&gic>; 1367 }; 1368}; 1369