1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 - 2014 Xilinx 4 */ 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 compatible = "arm,cortex-a9"; 17 device_type = "cpu"; 18 reg = <0>; 19 clocks = <&clkc 3>; 20 clock-latency = <1000>; 21 cpu0-supply = <®ulator_vccpint>; 22 operating-points = < 23 /* kHz uV */ 24 666667 1000000 25 333334 1000000 26 >; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <1>; 33 clocks = <&clkc 3>; 34 }; 35 }; 36 37 fpga_full: fpga-full { 38 compatible = "fpga-region"; 39 fpga-mgr = <&devcfg>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges; 43 }; 44 45 pmu@f8891000 { 46 compatible = "arm,cortex-a9-pmu"; 47 interrupts = <0 5 4>, <0 6 4>; 48 interrupt-parent = <&intc>; 49 reg = <0xf8891000 0x1000>, 50 <0xf8893000 0x1000>; 51 }; 52 53 regulator_vccpint: fixedregulator { 54 compatible = "regulator-fixed"; 55 regulator-name = "VCCPINT"; 56 regulator-min-microvolt = <1000000>; 57 regulator-max-microvolt = <1000000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 replicator { 63 compatible = "arm,coresight-static-replicator"; 64 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 65 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 66 67 out-ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 /* replicator output ports */ 72 port@0 { 73 reg = <0>; 74 replicator_out_port0: endpoint { 75 remote-endpoint = <&tpiu_in_port>; 76 }; 77 }; 78 port@1 { 79 reg = <1>; 80 replicator_out_port1: endpoint { 81 remote-endpoint = <&etb_in_port>; 82 }; 83 }; 84 }; 85 in-ports { 86 /* replicator input port */ 87 port { 88 replicator_in_port0: endpoint { 89 remote-endpoint = <&funnel_out_port>; 90 }; 91 }; 92 }; 93 }; 94 95 amba: axi { 96 compatible = "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 interrupt-parent = <&intc>; 100 ranges; 101 102 adc: adc@f8007100 { 103 compatible = "xlnx,zynq-xadc-1.00.a"; 104 reg = <0xf8007100 0x20>; 105 interrupts = <0 7 4>; 106 interrupt-parent = <&intc>; 107 clocks = <&clkc 12>; 108 }; 109 110 can0: can@e0008000 { 111 compatible = "xlnx,zynq-can-1.0"; 112 status = "disabled"; 113 clocks = <&clkc 19>, <&clkc 36>; 114 clock-names = "can_clk", "pclk"; 115 reg = <0xe0008000 0x1000>; 116 interrupts = <0 28 4>; 117 interrupt-parent = <&intc>; 118 tx-fifo-depth = <0x40>; 119 rx-fifo-depth = <0x40>; 120 }; 121 122 can1: can@e0009000 { 123 compatible = "xlnx,zynq-can-1.0"; 124 status = "disabled"; 125 clocks = <&clkc 20>, <&clkc 37>; 126 clock-names = "can_clk", "pclk"; 127 reg = <0xe0009000 0x1000>; 128 interrupts = <0 51 4>; 129 interrupt-parent = <&intc>; 130 tx-fifo-depth = <0x40>; 131 rx-fifo-depth = <0x40>; 132 }; 133 134 gpio0: gpio@e000a000 { 135 compatible = "xlnx,zynq-gpio-1.0"; 136 #gpio-cells = <2>; 137 clocks = <&clkc 42>; 138 gpio-controller; 139 interrupt-controller; 140 #interrupt-cells = <2>; 141 interrupt-parent = <&intc>; 142 interrupts = <0 20 4>; 143 reg = <0xe000a000 0x1000>; 144 }; 145 146 i2c0: i2c@e0004000 { 147 compatible = "cdns,i2c-r1p10"; 148 status = "disabled"; 149 clocks = <&clkc 38>; 150 interrupt-parent = <&intc>; 151 interrupts = <0 25 4>; 152 reg = <0xe0004000 0x1000>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 }; 156 157 i2c1: i2c@e0005000 { 158 compatible = "cdns,i2c-r1p10"; 159 status = "disabled"; 160 clocks = <&clkc 39>; 161 interrupt-parent = <&intc>; 162 interrupts = <0 48 4>; 163 reg = <0xe0005000 0x1000>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 }; 167 168 intc: interrupt-controller@f8f01000 { 169 compatible = "arm,cortex-a9-gic"; 170 #interrupt-cells = <3>; 171 interrupt-controller; 172 reg = <0xF8F01000 0x1000>, 173 <0xF8F00100 0x100>; 174 }; 175 176 L2: cache-controller@f8f02000 { 177 compatible = "arm,pl310-cache"; 178 reg = <0xF8F02000 0x1000>; 179 interrupts = <0 2 4>; 180 arm,data-latency = <3 2 2>; 181 arm,tag-latency = <2 2 2>; 182 cache-unified; 183 cache-level = <2>; 184 }; 185 186 mc: memory-controller@f8006000 { 187 compatible = "xlnx,zynq-ddrc-a05"; 188 reg = <0xf8006000 0x1000>; 189 }; 190 191 uart0: serial@e0000000 { 192 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 193 status = "disabled"; 194 clocks = <&clkc 23>, <&clkc 40>; 195 clock-names = "uart_clk", "pclk"; 196 reg = <0xE0000000 0x1000>; 197 interrupts = <0 27 4>; 198 }; 199 200 uart1: serial@e0001000 { 201 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 202 status = "disabled"; 203 clocks = <&clkc 24>, <&clkc 41>; 204 clock-names = "uart_clk", "pclk"; 205 reg = <0xE0001000 0x1000>; 206 interrupts = <0 50 4>; 207 }; 208 209 spi0: spi@e0006000 { 210 compatible = "xlnx,zynq-spi-r1p6"; 211 reg = <0xe0006000 0x1000>; 212 status = "disabled"; 213 interrupt-parent = <&intc>; 214 interrupts = <0 26 4>; 215 clocks = <&clkc 25>, <&clkc 34>; 216 clock-names = "ref_clk", "pclk"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 }; 220 221 spi1: spi@e0007000 { 222 compatible = "xlnx,zynq-spi-r1p6"; 223 reg = <0xe0007000 0x1000>; 224 status = "disabled"; 225 interrupt-parent = <&intc>; 226 interrupts = <0 49 4>; 227 clocks = <&clkc 26>, <&clkc 35>; 228 clock-names = "ref_clk", "pclk"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 }; 232 233 gem0: ethernet@e000b000 { 234 compatible = "cdns,zynq-gem", "cdns,gem"; 235 reg = <0xe000b000 0x1000>; 236 status = "disabled"; 237 interrupts = <0 22 4>; 238 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 239 clock-names = "pclk", "hclk", "tx_clk"; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 }; 243 244 gem1: ethernet@e000c000 { 245 compatible = "cdns,zynq-gem", "cdns,gem"; 246 reg = <0xe000c000 0x1000>; 247 status = "disabled"; 248 interrupts = <0 45 4>; 249 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 250 clock-names = "pclk", "hclk", "tx_clk"; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 }; 254 255 sdhci0: mmc@e0100000 { 256 compatible = "arasan,sdhci-8.9a"; 257 status = "disabled"; 258 clock-names = "clk_xin", "clk_ahb"; 259 clocks = <&clkc 21>, <&clkc 32>; 260 interrupt-parent = <&intc>; 261 interrupts = <0 24 4>; 262 reg = <0xe0100000 0x1000>; 263 }; 264 265 sdhci1: mmc@e0101000 { 266 compatible = "arasan,sdhci-8.9a"; 267 status = "disabled"; 268 clock-names = "clk_xin", "clk_ahb"; 269 clocks = <&clkc 22>, <&clkc 33>; 270 interrupt-parent = <&intc>; 271 interrupts = <0 47 4>; 272 reg = <0xe0101000 0x1000>; 273 }; 274 275 slcr: slcr@f8000000 { 276 #address-cells = <1>; 277 #size-cells = <1>; 278 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 279 reg = <0xF8000000 0x1000>; 280 ranges; 281 clkc: clkc@100 { 282 #clock-cells = <1>; 283 compatible = "xlnx,ps7-clkc"; 284 fclk-enable = <0>; 285 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 286 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 287 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 288 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 289 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 290 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 291 "gem1_aper", "sdio0_aper", "sdio1_aper", 292 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 293 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 294 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 295 "dbg_trc", "dbg_apb"; 296 reg = <0x100 0x100>; 297 }; 298 299 rstc: rstc@200 { 300 compatible = "xlnx,zynq-reset"; 301 reg = <0x200 0x48>; 302 #reset-cells = <1>; 303 syscon = <&slcr>; 304 }; 305 306 pinctrl0: pinctrl@700 { 307 compatible = "xlnx,pinctrl-zynq"; 308 reg = <0x700 0x200>; 309 syscon = <&slcr>; 310 }; 311 }; 312 313 dmac_s: dmac@f8003000 { 314 compatible = "arm,pl330", "arm,primecell"; 315 reg = <0xf8003000 0x1000>; 316 interrupt-parent = <&intc>; 317 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 318 "dma4", "dma5", "dma6", "dma7"; 319 interrupts = <0 13 4>, 320 <0 14 4>, <0 15 4>, 321 <0 16 4>, <0 17 4>, 322 <0 40 4>, <0 41 4>, 323 <0 42 4>, <0 43 4>; 324 #dma-cells = <1>; 325 #dma-channels = <8>; 326 #dma-requests = <4>; 327 clocks = <&clkc 27>; 328 clock-names = "apb_pclk"; 329 }; 330 331 devcfg: devcfg@f8007000 { 332 compatible = "xlnx,zynq-devcfg-1.0"; 333 reg = <0xf8007000 0x100>; 334 interrupt-parent = <&intc>; 335 interrupts = <0 8 4>; 336 clocks = <&clkc 12>; 337 clock-names = "ref_clk"; 338 syscon = <&slcr>; 339 }; 340 341 global_timer: timer@f8f00200 { 342 compatible = "arm,cortex-a9-global-timer"; 343 reg = <0xf8f00200 0x20>; 344 interrupts = <1 11 0x301>; 345 interrupt-parent = <&intc>; 346 clocks = <&clkc 4>; 347 }; 348 349 ttc0: timer@f8001000 { 350 interrupt-parent = <&intc>; 351 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 352 compatible = "cdns,ttc"; 353 clocks = <&clkc 6>; 354 reg = <0xF8001000 0x1000>; 355 }; 356 357 ttc1: timer@f8002000 { 358 interrupt-parent = <&intc>; 359 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 360 compatible = "cdns,ttc"; 361 clocks = <&clkc 6>; 362 reg = <0xF8002000 0x1000>; 363 }; 364 365 scutimer: timer@f8f00600 { 366 interrupt-parent = <&intc>; 367 interrupts = <1 13 0x301>; 368 compatible = "arm,cortex-a9-twd-timer"; 369 reg = <0xf8f00600 0x20>; 370 clocks = <&clkc 4>; 371 }; 372 373 usb0: usb@e0002000 { 374 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 375 status = "disabled"; 376 clocks = <&clkc 28>; 377 interrupt-parent = <&intc>; 378 interrupts = <0 21 4>; 379 reg = <0xe0002000 0x1000>; 380 phy_type = "ulpi"; 381 }; 382 383 usb1: usb@e0003000 { 384 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 385 status = "disabled"; 386 clocks = <&clkc 29>; 387 interrupt-parent = <&intc>; 388 interrupts = <0 44 4>; 389 reg = <0xe0003000 0x1000>; 390 phy_type = "ulpi"; 391 }; 392 393 watchdog0: watchdog@f8005000 { 394 clocks = <&clkc 45>; 395 compatible = "cdns,wdt-r1p2"; 396 interrupt-parent = <&intc>; 397 interrupts = <0 9 1>; 398 reg = <0xf8005000 0x1000>; 399 timeout-sec = <10>; 400 }; 401 402 etb@f8801000 { 403 compatible = "arm,coresight-etb10", "arm,primecell"; 404 reg = <0xf8801000 0x1000>; 405 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 406 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 407 in-ports { 408 port { 409 etb_in_port: endpoint { 410 remote-endpoint = <&replicator_out_port1>; 411 }; 412 }; 413 }; 414 }; 415 416 tpiu@f8803000 { 417 compatible = "arm,coresight-tpiu", "arm,primecell"; 418 reg = <0xf8803000 0x1000>; 419 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 420 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 421 in-ports { 422 port { 423 tpiu_in_port: endpoint { 424 remote-endpoint = <&replicator_out_port0>; 425 }; 426 }; 427 }; 428 }; 429 430 funnel@f8804000 { 431 compatible = "arm,coresight-static-funnel", "arm,primecell"; 432 reg = <0xf8804000 0x1000>; 433 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 434 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 435 436 /* funnel output ports */ 437 out-ports { 438 port { 439 funnel_out_port: endpoint { 440 remote-endpoint = 441 <&replicator_in_port0>; 442 }; 443 }; 444 }; 445 446 in-ports { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 450 /* funnel input ports */ 451 port@0 { 452 reg = <0>; 453 funnel0_in_port0: endpoint { 454 remote-endpoint = <&ptm0_out_port>; 455 }; 456 }; 457 458 port@1 { 459 reg = <1>; 460 funnel0_in_port1: endpoint { 461 remote-endpoint = <&ptm1_out_port>; 462 }; 463 }; 464 465 port@2 { 466 reg = <2>; 467 funnel0_in_port2: endpoint { 468 }; 469 }; 470 /* The other input ports are not connect to anything */ 471 }; 472 }; 473 474 ptm@f889c000 { 475 compatible = "arm,coresight-etm3x", "arm,primecell"; 476 reg = <0xf889c000 0x1000>; 477 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 478 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 479 cpu = <&cpu0>; 480 out-ports { 481 port { 482 ptm0_out_port: endpoint { 483 remote-endpoint = <&funnel0_in_port0>; 484 }; 485 }; 486 }; 487 }; 488 489 ptm@f889d000 { 490 compatible = "arm,coresight-etm3x", "arm,primecell"; 491 reg = <0xf889d000 0x1000>; 492 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 493 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 494 cpu = <&cpu1>; 495 out-ports { 496 port { 497 ptm1_out_port: endpoint { 498 remote-endpoint = <&funnel0_in_port1>; 499 }; 500 }; 501 }; 502 }; 503 }; 504}; 505