1 /*
2  * include/asm-xtensa/cache.h
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * (C) 2001 - 2005 Tensilica Inc.
9  */
10 
11 #ifndef _XTENSA_CACHE_H
12 #define _XTENSA_CACHE_H
13 
14 #include <asm/core.h>
15 
16 #define L1_CACHE_SHIFT	XCHAL_DCACHE_LINEWIDTH
17 #define L1_CACHE_BYTES	XCHAL_DCACHE_LINESIZE
18 #define SMP_CACHE_BYTES	L1_CACHE_BYTES
19 
20 #define DCACHE_WAY_SIZE	(XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
21 #define ICACHE_WAY_SIZE	(XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
22 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
23 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
24 
25 /* Maximum cache size per way. */
26 #if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
27 # define CACHE_WAY_SIZE DCACHE_WAY_SIZE
28 #else
29 # define CACHE_WAY_SIZE ICACHE_WAY_SIZE
30 #endif
31 
32 #define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
33 
34 /*
35  * R/O after init is actually writable, it cannot go to .rodata
36  * according to vmlinux linker script.
37  */
38 #define __ro_after_init __read_mostly
39 
40 #endif	/* _XTENSA_CACHE_H */
41