1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _HARDWARE_MANAGER_H_
24 #define _HARDWARE_MANAGER_H_
25 
26 
27 
28 struct pp_hwmgr;
29 struct pp_hw_power_state;
30 struct pp_power_state;
31 enum amd_dpm_forced_level;
32 struct PP_TemperatureRange;
33 
34 
35 struct phm_fan_speed_info {
36 	uint32_t min_percent;
37 	uint32_t max_percent;
38 	uint32_t min_rpm;
39 	uint32_t max_rpm;
40 	bool supports_percent_read;
41 	bool supports_percent_write;
42 	bool supports_rpm_read;
43 	bool supports_rpm_write;
44 };
45 
46 /* Automatic Power State Throttling */
47 enum PHM_AutoThrottleSource
48 {
49     PHM_AutoThrottleSource_Thermal,
50     PHM_AutoThrottleSource_External
51 };
52 
53 typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
54 
55 enum phm_platform_caps {
56 	PHM_PlatformCaps_AtomBiosPpV1 = 0,
57 	PHM_PlatformCaps_PowerPlaySupport,
58 	PHM_PlatformCaps_ACOverdriveSupport,
59 	PHM_PlatformCaps_BacklightSupport,
60 	PHM_PlatformCaps_ThermalController,
61 	PHM_PlatformCaps_BiosPowerSourceControl,
62 	PHM_PlatformCaps_DisableVoltageTransition,
63 	PHM_PlatformCaps_DisableEngineTransition,
64 	PHM_PlatformCaps_DisableMemoryTransition,
65 	PHM_PlatformCaps_DynamicPowerManagement,
66 	PHM_PlatformCaps_EnableASPML0s,
67 	PHM_PlatformCaps_EnableASPML1,
68 	PHM_PlatformCaps_OD5inACSupport,
69 	PHM_PlatformCaps_OD5inDCSupport,
70 	PHM_PlatformCaps_SoftStateOD5,
71 	PHM_PlatformCaps_NoOD5Support,
72 	PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
73 	PHM_PlatformCaps_ActivityReporting,
74 	PHM_PlatformCaps_EnableBackbias,
75 	PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
76 	PHM_PlatformCaps_ShowPowerBudgetWarning,
77 	PHM_PlatformCaps_PowerBudgetWaiverAvailable,
78 	PHM_PlatformCaps_GFXClockGatingSupport,
79 	PHM_PlatformCaps_MMClockGatingSupport,
80 	PHM_PlatformCaps_AutomaticDCTransition,
81 	PHM_PlatformCaps_GeminiPrimary,
82 	PHM_PlatformCaps_MemorySpreadSpectrumSupport,
83 	PHM_PlatformCaps_EngineSpreadSpectrumSupport,
84 	PHM_PlatformCaps_StepVddc,
85 	PHM_PlatformCaps_DynamicPCIEGen2Support,
86 	PHM_PlatformCaps_SMC,
87 	PHM_PlatformCaps_FaultyInternalThermalReading,          /* Internal thermal controller reports faulty temperature value when DAC2 is active */
88 	PHM_PlatformCaps_EnableVoltageControl,                  /* indicates voltage can be controlled */
89 	PHM_PlatformCaps_EnableSideportControl,                 /* indicates Sideport can be controlled */
90 	PHM_PlatformCaps_VideoPlaybackEEUNotification,          /* indicates EEU notification of video start/stop is required */
91 	PHM_PlatformCaps_TurnOffPll_ASPML1,                     /* PCIE Turn Off PLL in ASPM L1 */
92 	PHM_PlatformCaps_EnableHTLinkControl,                   /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
93 	PHM_PlatformCaps_PerformanceStateOnly,                  /* indicates only performance power state to be used on current system. */
94 	PHM_PlatformCaps_ExclusiveModeAlwaysHigh,               /* In Exclusive (3D) mode always stay in High state. */
95 	PHM_PlatformCaps_DisableMGClockGating,                  /* to disable Medium Grain Clock Gating or not */
96 	PHM_PlatformCaps_DisableMGCGTSSM,                       /* TO disable Medium Grain Clock Gating Shader Complex control */
97 	PHM_PlatformCaps_UVDAlwaysHigh,                         /* In UVD mode always stay in High state */
98 	PHM_PlatformCaps_DisablePowerGating,                    /* to disable power gating */
99 	PHM_PlatformCaps_CustomThermalPolicy,                   /* indicates only performance power state to be used on current system. */
100 	PHM_PlatformCaps_StayInBootState,                       /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
101 	PHM_PlatformCaps_SMCAllowSeparateSWThermalState,        /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
102 	PHM_PlatformCaps_MultiUVDStateSupport,                  /* Powerplay state table supports multi UVD states. */
103 	PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,             /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
104 	PHM_PlatformCaps_EnableMCUHTLinkControl,                /* Enable HT link control by MCU */
105 	PHM_PlatformCaps_ABM,                                   /* ABM support.*/
106 	PHM_PlatformCaps_KongThermalPolicy,                     /* A thermal policy specific for Kong */
107 	PHM_PlatformCaps_SwitchVDDNB,                           /* if the users want to switch VDDNB */
108 	PHM_PlatformCaps_ULPS,                                  /* support ULPS mode either through ACPI state or ULPS state */
109 	PHM_PlatformCaps_NativeULPS,                            /* hardware capable of ULPS state (other than through the ACPI state) */
110 	PHM_PlatformCaps_EnableMVDDControl,                     /* indicates that memory voltage can be controlled */
111 	PHM_PlatformCaps_ControlVDDCI,                          /* Control VDDCI separately from VDDC. */
112 	PHM_PlatformCaps_DisableDCODT,                          /* indicates if DC ODT apply or not */
113 	PHM_PlatformCaps_DynamicACTiming,                       /* if the SMC dynamically re-programs MC SEQ register values */
114 	PHM_PlatformCaps_EnableThermalIntByGPIO,                /* enable throttle control through GPIO */
115 	PHM_PlatformCaps_BootStateOnAlert,                      /* Go to boot state on alerts, e.g. on an AC->DC transition. */
116 	PHM_PlatformCaps_DontWaitForVBlankOnAlert,              /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
117 	PHM_PlatformCaps_Force3DClockSupport,                   /* indicates if the platform supports force 3D clock. */
118 	PHM_PlatformCaps_MicrocodeFanControl,                   /* Fan is controlled by the SMC microcode. */
119 	PHM_PlatformCaps_AdjustUVDPriorityForSP,
120 	PHM_PlatformCaps_DisableLightSleep,                     /* Light sleep for evergreen family. */
121 	PHM_PlatformCaps_DisableMCLS,                           /* MC Light sleep */
122 	PHM_PlatformCaps_RegulatorHot,                          /* Enable throttling on 'regulator hot' events. */
123 	PHM_PlatformCaps_BACO,                                  /* Support Bus Alive Chip Off mode */
124 	PHM_PlatformCaps_DisableDPM,                            /* Disable DPM, supported from Llano */
125 	PHM_PlatformCaps_DynamicM3Arbiter,                      /* support dynamically change m3 arbitor parameters */
126 	PHM_PlatformCaps_SclkDeepSleep,                         /* support sclk deep sleep */
127 	PHM_PlatformCaps_DynamicPatchPowerState,                /* this ASIC supports to patch power state dynamically */
128 	PHM_PlatformCaps_ThermalAutoThrottling,                 /* enabling auto thermal throttling, */
129 	PHM_PlatformCaps_SumoThermalPolicy,                     /* A thermal policy specific for Sumo */
130 	PHM_PlatformCaps_PCIEPerformanceRequest,                /* support to change RC voltage */
131 	PHM_PlatformCaps_BLControlledByGPU,                     /* support varibright */
132 	PHM_PlatformCaps_PowerContainment,                      /* support DPM2 power containment (AKA TDP clamping) */
133 	PHM_PlatformCaps_SQRamping,                             /* support DPM2 SQ power throttle */
134 	PHM_PlatformCaps_CAC,                                   /* support Capacitance * Activity power estimation */
135 	PHM_PlatformCaps_NIChipsets,                            /* Northern Island and beyond chipsets */
136 	PHM_PlatformCaps_TrinityChipsets,                       /* Trinity chipset */
137 	PHM_PlatformCaps_EvergreenChipsets,                     /* Evergreen family chipset */
138 	PHM_PlatformCaps_PowerControl,                          /* Cayman and beyond chipsets */
139 	PHM_PlatformCaps_DisableLSClockGating,                  /* to disable Light Sleep control for HDP memories */
140 	PHM_PlatformCaps_BoostState,                            /* this ASIC supports boost state */
141 	PHM_PlatformCaps_UserMaxClockForMultiDisplays,          /* indicates if max memory clock is used for all status when multiple displays are connected */
142 	PHM_PlatformCaps_RegWriteDelay,                         /* indicates if back to back reg write delay is required */
143 	PHM_PlatformCaps_NonABMSupportInPPLib,                  /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
144 	PHM_PlatformCaps_GFXDynamicMGPowerGating,               /* Enable Dynamic MG PowerGating on Trinity */
145 	PHM_PlatformCaps_DisableSMUUVDHandshake,                /* Disable SMU UVD Handshake */
146 	PHM_PlatformCaps_DTE,                                   /* Support Digital Temperature Estimation */
147 	PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,            /* This is for the feature requested by David B., and Tonny W.*/
148 	PHM_PlatformCaps_UVDPowerGating,                        /* enable UVD power gating, supported from Llano */
149 	PHM_PlatformCaps_UVDDynamicPowerGating,                 /* enable UVD Dynamic power gating, supported from UVD5 */
150 	PHM_PlatformCaps_VCEPowerGating,                        /* Enable VCE power gating, supported for TN and later ASICs */
151 	PHM_PlatformCaps_SamuPowerGating,                       /* Enable SAMU power gating, supported for KV and later ASICs */
152 	PHM_PlatformCaps_UVDDPM,                                /* UVD clock DPM */
153 	PHM_PlatformCaps_VCEDPM,                                /* VCE clock DPM */
154 	PHM_PlatformCaps_SamuDPM,                               /* SAMU clock DPM */
155 	PHM_PlatformCaps_AcpDPM,                                /* ACP clock DPM */
156 	PHM_PlatformCaps_SclkDeepSleepAboveLow,                 /* Enable SCLK Deep Sleep on all DPM states */
157 	PHM_PlatformCaps_DynamicUVDState,                       /* Dynamic UVD State */
158 	PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
159 	PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,            /* Set UVD Clk With Dummy Back End */
160 	PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,            /* Set VCE Clk With Dummy Back End */
161 	PHM_PlatformCaps_WantACPClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
162 	PHM_PlatformCaps_OD6inACSupport,                        /* indicates that the ASIC/back end supports OD6 */
163 	PHM_PlatformCaps_OD6inDCSupport,                        /* indicates that the ASIC/back end supports OD6 in DC */
164 	PHM_PlatformCaps_EnablePlatformPowerManagement,         /* indicates that Platform Power Management feature is supported */
165 	PHM_PlatformCaps_SurpriseRemoval,                       /* indicates that surprise removal feature is requested */
166 	PHM_PlatformCaps_NewCACVoltage,                         /* indicates new CAC voltage table support */
167 	PHM_PlatformCaps_DiDtSupport,                           /* for dI/dT feature */
168 	PHM_PlatformCaps_DBRamping,                             /* for dI/dT feature */
169 	PHM_PlatformCaps_TDRamping,                             /* for dI/dT feature */
170 	PHM_PlatformCaps_TCPRamping,                            /* for dI/dT feature */
171 	PHM_PlatformCaps_DBRRamping,                            /* for dI/dT feature */
172 	PHM_PlatformCaps_DiDtEDCEnable,                         /* for dI/dT feature */
173 	PHM_PlatformCaps_GCEDC,                                 /* for dI/dT feature */
174 	PHM_PlatformCaps_PSM,                                   /* for dI/dT feature */
175 	PHM_PlatformCaps_EnableSMU7ThermalManagement,           /* SMC will manage thermal events */
176 	PHM_PlatformCaps_FPS,                                   /* FPS support */
177 	PHM_PlatformCaps_ACP,                                   /* ACP support */
178 	PHM_PlatformCaps_SclkThrottleLowNotification,           /* SCLK Throttle Low Notification */
179 	PHM_PlatformCaps_XDMAEnabled,                           /* XDMA engine is enabled */
180 	PHM_PlatformCaps_UseDummyBackEnd,                       /* use dummy back end */
181 	PHM_PlatformCaps_EnableDFSBypass,                       /* Enable DFS bypass */
182 	PHM_PlatformCaps_VddNBDirectRequest,
183 	PHM_PlatformCaps_PauseMMSessions,
184 	PHM_PlatformCaps_UnTabledHardwareInterface,             /* Tableless/direct call hardware interface for CI and newer ASICs */
185 	PHM_PlatformCaps_SMU7,                                  /* indicates that vpuRecoveryBegin without SMU shutdown */
186 	PHM_PlatformCaps_RevertGPIO5Polarity,                   /* indicates revert GPIO5 plarity table support */
187 	PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
188 	PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
189 	PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
190 	PHM_PlatformCaps_ForceMclkHigh,                         /* Disable memory clock switching by forcing memory clock high */
191 	PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
192 	PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
193 	PHM_PlatformCaps_IOIC3,
194 	PHM_PlatformCaps_ConnectedStandby,
195 	PHM_PlatformCaps_EVV,
196 	PHM_PlatformCaps_EnableLongIdleBACOSupport,
197 	PHM_PlatformCaps_CombinePCCWithThermalSignal,
198 	PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
199 	PHM_PlatformCaps_StablePState,
200 	PHM_PlatformCaps_OD6PlusinACSupport,
201 	PHM_PlatformCaps_OD6PlusinDCSupport,
202 	PHM_PlatformCaps_ODThermalLimitUnlock,
203 	PHM_PlatformCaps_ReducePowerLimit,
204 	PHM_PlatformCaps_ODFuzzyFanControlSupport,
205 	PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
206 	PHM_PlatformCaps_ControlVDDGFX,
207 	PHM_PlatformCaps_BBBSupported,
208 	PHM_PlatformCaps_DisableVoltageIsland,
209 	PHM_PlatformCaps_FanSpeedInTableIsRPM,
210 	PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
211 	PHM_PlatformCaps_IcelandULPSSWWorkAround,
212 	PHM_PlatformCaps_FPSEnhancement,
213 	PHM_PlatformCaps_LoadPostProductionFirmware,
214 	PHM_PlatformCaps_VpuRecoveryInProgress,
215 	PHM_PlatformCaps_Falcon_QuickTransition,
216 	PHM_PlatformCaps_AVFS,
217 	PHM_PlatformCaps_ClockStretcher,
218 	PHM_PlatformCaps_TablelessHardwareInterface,
219 	PHM_PlatformCaps_EnableDriverEVV,
220 	PHM_PlatformCaps_SPLLShutdownSupport,
221 	PHM_PlatformCaps_VirtualBatteryState,
222 	PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
223 	PHM_PlatformCaps_DisableMclkSwitchForVR,
224 	PHM_PlatformCaps_SMU8,
225 	PHM_PlatformCaps_VRHotPolarityHigh,
226 	PHM_PlatformCaps_IPS_UlpsExclusive,
227 	PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
228 	PHM_PlatformCaps_GeminiAsymmetricPower,
229 	PHM_PlatformCaps_OCLPowerOptimization,
230 	PHM_PlatformCaps_MaxPCIEBandWidth,
231 	PHM_PlatformCaps_PerfPerWattOptimizationSupport,
232 	PHM_PlatformCaps_UVDClientMCTuning,
233 	PHM_PlatformCaps_ODNinACSupport,
234 	PHM_PlatformCaps_ODNinDCSupport,
235 	PHM_PlatformCaps_OD8inACSupport,
236 	PHM_PlatformCaps_OD8inDCSupport,
237 	PHM_PlatformCaps_UMDPState,
238 	PHM_PlatformCaps_AutoWattmanSupport,
239 	PHM_PlatformCaps_AutoWattmanEnable_CCCState,
240 	PHM_PlatformCaps_FreeSyncActive,
241 	PHM_PlatformCaps_EnableShadowPstate,
242 	PHM_PlatformCaps_customThermalManagement,
243 	PHM_PlatformCaps_staticFanControl,
244 	PHM_PlatformCaps_Virtual_System,
245 	PHM_PlatformCaps_LowestUclkReservedForUlv,
246 	PHM_PlatformCaps_EnableBoostState,
247 	PHM_PlatformCaps_AVFSSupport,
248 	PHM_PlatformCaps_ThermalPolicyDelay,
249 	PHM_PlatformCaps_CustomFanControlSupport,
250 	PHM_PlatformCaps_BAMACO,
251 	PHM_PlatformCaps_Max
252 };
253 
254 #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
255 
256 /* Number of uint32_t entries used by CAPS table */
257 #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
258 	((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
259 
260 struct pp_hw_descriptor {
261 	uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
262 };
263 
264 enum PHM_PerformanceLevelDesignation {
265 	PHM_PerformanceLevelDesignation_Activity,
266 	PHM_PerformanceLevelDesignation_PowerContainment
267 };
268 
269 typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
270 
271 struct PHM_PerformanceLevel {
272     uint32_t    coreClock;
273     uint32_t    memory_clock;
274     uint32_t  vddc;
275     uint32_t  vddci;
276     uint32_t    nonLocalMemoryFreq;
277     uint32_t nonLocalMemoryWidth;
278 };
279 
280 typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
281 
282 /* Function for setting a platform cap */
phm_cap_set(uint32_t * caps,enum phm_platform_caps c)283 static inline void phm_cap_set(uint32_t *caps,
284 			enum phm_platform_caps c)
285 {
286 	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
287 			     (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
288 }
289 
phm_cap_unset(uint32_t * caps,enum phm_platform_caps c)290 static inline void phm_cap_unset(uint32_t *caps,
291 			enum phm_platform_caps c)
292 {
293 	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
294 }
295 
phm_cap_enabled(const uint32_t * caps,enum phm_platform_caps c)296 static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
297 {
298 	return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
299 		  (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
300 }
301 
302 #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
303 
304 #define PP_PCIEGenInvalid  0xffff
305 enum PP_PCIEGen {
306     PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
307     PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
308     PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
309 };
310 
311 typedef enum PP_PCIEGen PP_PCIEGen;
312 
313 #define PP_Min_PCIEGen     PP_PCIEGen1
314 #define PP_Max_PCIEGen     PP_PCIEGen3
315 #define PP_Min_PCIELane    1
316 #define PP_Max_PCIELane    16
317 
318 enum phm_clock_Type {
319 	PHM_DispClock = 1,
320 	PHM_SClock,
321 	PHM_MemClock
322 };
323 
324 #define MAX_NUM_CLOCKS 16
325 
326 struct PP_Clocks {
327 	uint32_t engineClock;
328 	uint32_t memoryClock;
329 	uint32_t BusBandwidth;
330 	uint32_t engineClockInSR;
331 	uint32_t dcefClock;
332 	uint32_t dcefClockInSR;
333 };
334 
335 struct pp_clock_info {
336 	uint32_t min_mem_clk;
337 	uint32_t max_mem_clk;
338 	uint32_t min_eng_clk;
339 	uint32_t max_eng_clk;
340 	uint32_t min_bus_bandwidth;
341 	uint32_t max_bus_bandwidth;
342 };
343 
344 struct phm_platform_descriptor {
345 	uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
346 	uint32_t vbiosInterruptId;
347 	struct PP_Clocks overdriveLimit;
348 	struct PP_Clocks clockStep;
349 	uint32_t hardwareActivityPerformanceLevels;
350 	uint32_t minimumClocksReductionPercentage;
351 	uint32_t minOverdriveVDDC;
352 	uint32_t maxOverdriveVDDC;
353 	uint32_t overdriveVDDCStep;
354 	uint32_t hardwarePerformanceLevels;
355 	uint16_t powerBudget;
356 	uint32_t TDPLimit;
357 	uint32_t nearTDPLimit;
358 	uint32_t nearTDPLimitAdjusted;
359 	uint32_t SQRampingThreshold;
360 	uint32_t CACLeakage;
361 	uint16_t TDPODLimit;
362 	uint32_t TDPAdjustment;
363 	bool TDPAdjustmentPolarity;
364 	uint16_t LoadLineSlope;
365 	uint32_t  VidMinLimit;
366 	uint32_t  VidMaxLimit;
367 	uint32_t  VidStep;
368 	uint32_t  VidAdjustment;
369 	bool VidAdjustmentPolarity;
370 };
371 
372 struct phm_clocks {
373 	uint32_t num_of_entries;
374 	uint32_t clock[MAX_NUM_CLOCKS];
375 };
376 
377 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
378 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
379 #define DPMTABLE_UPDATE_SCLK        0x00000004
380 #define DPMTABLE_UPDATE_MCLK        0x00000008
381 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
382 #define DPMTABLE_UPDATE_SOCCLK      0x00000020
383 
384 struct phm_odn_performance_level {
385 	uint32_t clock;
386 	uint32_t vddc;
387 	bool enabled;
388 };
389 
390 struct phm_odn_clock_levels {
391 	uint32_t size;
392 	uint32_t options;
393 	uint32_t flags;
394 	uint32_t num_of_pl;
395 	/* variable-sized array, specify by num_of_pl. */
396 	struct phm_odn_performance_level entries[8];
397 };
398 
399 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
400 extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
401 extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
402 extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
403 extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
404 extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
405 extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
406 extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
407 		    const struct pp_hw_power_state *pcurrent_state,
408 		 const struct pp_hw_power_state *pnew_power_state);
409 
410 extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
411 				   struct pp_power_state *adjusted_ps,
412 			     const struct pp_power_state *current_ps);
413 
414 extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
415 
416 extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
417 extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
418 extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
419 extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
420 extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
421 extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
422 extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
423 extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
424 
425 extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
426 				 const struct pp_hw_power_state *pstate1,
427 				 const struct pp_hw_power_state *pstate2,
428 				 bool *equal);
429 
430 extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
431 		const struct amd_pp_display_configuration *display_config);
432 
433 extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
434 		struct amd_pp_simple_clock_info *info);
435 
436 extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
437 
438 extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
439 
440 extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
441 				PHM_PerformanceLevelDesignation designation, uint32_t index,
442 				PHM_PerformanceLevel *level);
443 
444 extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
445 			struct pp_clock_info *pclock_info,
446 			PHM_PerformanceLevelDesignation designation);
447 
448 extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
449 
450 extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
451 
452 extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
453 		enum amd_pp_clock_type type,
454 		struct pp_clock_levels_with_latency *clocks);
455 extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
456 		enum amd_pp_clock_type type,
457 		struct pp_clock_levels_with_voltage *clocks);
458 extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
459 						void *clock_ranges);
460 extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
461 		struct pp_display_clock_request *clock);
462 
463 extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
464 extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
465 
466 extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);
467 
468 #endif /* _HARDWARE_MANAGER_H_ */
469 
470