1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef SMU7_DISCRETE_H
25 #define SMU7_DISCRETE_H
26 
27 #include "smu7.h"
28 
29 #pragma pack(push, 1)
30 
31 #define SMU7_DTE_ITERATIONS 5
32 #define SMU7_DTE_SOURCES 3
33 #define SMU7_DTE_SINKS 1
34 #define SMU7_NUM_CPU_TES 0
35 #define SMU7_NUM_GPU_TES 1
36 #define SMU7_NUM_NON_TES 2
37 
38 struct SMU7_SoftRegisters
39 {
40     uint32_t        RefClockFrequency;
41     uint32_t        PmTimerP;
42     uint32_t        FeatureEnables;
43     uint32_t        PreVBlankGap;
44     uint32_t        VBlankTimeout;
45     uint32_t        TrainTimeGap;
46 
47     uint32_t        MvddSwitchTime;
48     uint32_t        LongestAcpiTrainTime;
49     uint32_t        AcpiDelay;
50     uint32_t        G5TrainTime;
51     uint32_t        DelayMpllPwron;
52     uint32_t        VoltageChangeTimeout;
53     uint32_t        HandshakeDisables;
54 
55     uint8_t         DisplayPhy1Config;
56     uint8_t         DisplayPhy2Config;
57     uint8_t         DisplayPhy3Config;
58     uint8_t         DisplayPhy4Config;
59 
60     uint8_t         DisplayPhy5Config;
61     uint8_t         DisplayPhy6Config;
62     uint8_t         DisplayPhy7Config;
63     uint8_t         DisplayPhy8Config;
64 
65     uint32_t        AverageGraphicsA;
66     uint32_t        AverageMemoryA;
67     uint32_t        AverageGioA;
68 
69     uint8_t         SClkDpmEnabledLevels;
70     uint8_t         MClkDpmEnabledLevels;
71     uint8_t         LClkDpmEnabledLevels;
72     uint8_t         PCIeDpmEnabledLevels;
73 
74     uint8_t         UVDDpmEnabledLevels;
75     uint8_t         SAMUDpmEnabledLevels;
76     uint8_t         ACPDpmEnabledLevels;
77     uint8_t         VCEDpmEnabledLevels;
78 
79     uint32_t        DRAM_LOG_ADDR_H;
80     uint32_t        DRAM_LOG_ADDR_L;
81     uint32_t        DRAM_LOG_PHY_ADDR_H;
82     uint32_t        DRAM_LOG_PHY_ADDR_L;
83     uint32_t        DRAM_LOG_BUFF_SIZE;
84     uint32_t        UlvEnterC;
85     uint32_t        UlvTime;
86     uint32_t        Reserved[3];
87 
88 };
89 
90 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
91 
92 struct SMU7_Discrete_VoltageLevel
93 {
94     uint16_t    Voltage;
95     uint16_t    StdVoltageHiSidd;
96     uint16_t    StdVoltageLoSidd;
97     uint8_t     Smio;
98     uint8_t     padding;
99 };
100 
101 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
102 
103 struct SMU7_Discrete_GraphicsLevel
104 {
105     uint32_t    Flags;
106     uint32_t    MinVddc;
107     uint32_t    MinVddcPhases;
108 
109     uint32_t    SclkFrequency;
110 
111     uint8_t     padding1[2];
112     uint16_t    ActivityLevel;
113 
114     uint32_t    CgSpllFuncCntl3;
115     uint32_t    CgSpllFuncCntl4;
116     uint32_t    SpllSpreadSpectrum;
117     uint32_t    SpllSpreadSpectrum2;
118     uint32_t    CcPwrDynRm;
119     uint32_t    CcPwrDynRm1;
120     uint8_t     SclkDid;
121     uint8_t     DisplayWatermark;
122     uint8_t     EnabledForActivity;
123     uint8_t     EnabledForThrottle;
124     uint8_t     UpH;
125     uint8_t     DownH;
126     uint8_t     VoltageDownH;
127     uint8_t     PowerThrottle;
128     uint8_t     DeepSleepDivId;
129     uint8_t     padding[3];
130 };
131 
132 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
133 
134 struct SMU7_Discrete_ACPILevel
135 {
136     uint32_t    Flags;
137     uint32_t    MinVddc;
138     uint32_t    MinVddcPhases;
139     uint32_t    SclkFrequency;
140     uint8_t     SclkDid;
141     uint8_t     DisplayWatermark;
142     uint8_t     DeepSleepDivId;
143     uint8_t     padding;
144     uint32_t    CgSpllFuncCntl;
145     uint32_t    CgSpllFuncCntl2;
146     uint32_t    CgSpllFuncCntl3;
147     uint32_t    CgSpllFuncCntl4;
148     uint32_t    SpllSpreadSpectrum;
149     uint32_t    SpllSpreadSpectrum2;
150     uint32_t    CcPwrDynRm;
151     uint32_t    CcPwrDynRm1;
152 };
153 
154 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
155 
156 struct SMU7_Discrete_Ulv
157 {
158     uint32_t    CcPwrDynRm;
159     uint32_t    CcPwrDynRm1;
160     uint16_t    VddcOffset;
161     uint8_t     VddcOffsetVid;
162     uint8_t     VddcPhase;
163     uint32_t    Reserved;
164 };
165 
166 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
167 
168 struct SMU7_Discrete_MemoryLevel
169 {
170     uint32_t    MinVddc;
171     uint32_t    MinVddcPhases;
172     uint32_t    MinVddci;
173     uint32_t    MinMvdd;
174 
175     uint32_t    MclkFrequency;
176 
177     uint8_t     EdcReadEnable;
178     uint8_t     EdcWriteEnable;
179     uint8_t     RttEnable;
180     uint8_t     StutterEnable;
181 
182     uint8_t     StrobeEnable;
183     uint8_t     StrobeRatio;
184     uint8_t     EnabledForThrottle;
185     uint8_t     EnabledForActivity;
186 
187     uint8_t     UpH;
188     uint8_t     DownH;
189     uint8_t     VoltageDownH;
190     uint8_t     padding;
191 
192     uint16_t    ActivityLevel;
193     uint8_t     DisplayWatermark;
194     uint8_t     padding1;
195 
196     uint32_t    MpllFuncCntl;
197     uint32_t    MpllFuncCntl_1;
198     uint32_t    MpllFuncCntl_2;
199     uint32_t    MpllAdFuncCntl;
200     uint32_t    MpllDqFuncCntl;
201     uint32_t    MclkPwrmgtCntl;
202     uint32_t    DllCntl;
203     uint32_t    MpllSs1;
204     uint32_t    MpllSs2;
205 };
206 
207 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
208 
209 struct SMU7_Discrete_LinkLevel
210 {
211     uint8_t     PcieGenSpeed;
212     uint8_t     PcieLaneCount;
213     uint8_t     EnabledForActivity;
214     uint8_t     Padding;
215     uint32_t    DownT;
216     uint32_t    UpT;
217     uint32_t    Reserved;
218 };
219 
220 typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
221 
222 
223 struct SMU7_Discrete_MCArbDramTimingTableEntry
224 {
225     uint32_t McArbDramTiming;
226     uint32_t McArbDramTiming2;
227     uint8_t  McArbBurstTime;
228     uint8_t  padding[3];
229 };
230 
231 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
232 
233 struct SMU7_Discrete_MCArbDramTimingTable
234 {
235     SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
236 };
237 
238 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
239 
240 struct SMU7_Discrete_UvdLevel
241 {
242     uint32_t VclkFrequency;
243     uint32_t DclkFrequency;
244     uint16_t MinVddc;
245     uint8_t  MinVddcPhases;
246     uint8_t  VclkDivider;
247     uint8_t  DclkDivider;
248     uint8_t  padding[3];
249 };
250 
251 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
252 
253 struct SMU7_Discrete_ExtClkLevel
254 {
255     uint32_t Frequency;
256     uint16_t MinVoltage;
257     uint8_t  MinPhases;
258     uint8_t  Divider;
259 };
260 
261 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
262 
263 struct SMU7_Discrete_StateInfo
264 {
265     uint32_t SclkFrequency;
266     uint32_t MclkFrequency;
267     uint32_t VclkFrequency;
268     uint32_t DclkFrequency;
269     uint32_t SamclkFrequency;
270     uint32_t AclkFrequency;
271     uint32_t EclkFrequency;
272     uint16_t MvddVoltage;
273     uint16_t padding16;
274     uint8_t  DisplayWatermark;
275     uint8_t  McArbIndex;
276     uint8_t  McRegIndex;
277     uint8_t  SeqIndex;
278     uint8_t  SclkDid;
279     int8_t   SclkIndex;
280     int8_t   MclkIndex;
281     uint8_t  PCIeGen;
282 
283 };
284 
285 typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
286 
287 
288 struct SMU7_Discrete_DpmTable
289 {
290     SMU7_PIDController                  GraphicsPIDController;
291     SMU7_PIDController                  MemoryPIDController;
292     SMU7_PIDController                  LinkPIDController;
293 
294     uint32_t                            SystemFlags;
295 
296 
297     uint32_t                            SmioMaskVddcVid;
298     uint32_t                            SmioMaskVddcPhase;
299     uint32_t                            SmioMaskVddciVid;
300     uint32_t                            SmioMaskMvddVid;
301 
302     uint32_t                            VddcLevelCount;
303     uint32_t                            VddciLevelCount;
304     uint32_t                            MvddLevelCount;
305 
306     SMU7_Discrete_VoltageLevel          VddcLevel               [SMU7_MAX_LEVELS_VDDC];
307 //    SMU7_Discrete_VoltageLevel          VddcStandardReference   [SMU7_MAX_LEVELS_VDDC];
308     SMU7_Discrete_VoltageLevel          VddciLevel              [SMU7_MAX_LEVELS_VDDCI];
309     SMU7_Discrete_VoltageLevel          MvddLevel               [SMU7_MAX_LEVELS_MVDD];
310 
311     uint8_t                             GraphicsDpmLevelCount;
312     uint8_t                             MemoryDpmLevelCount;
313     uint8_t                             LinkLevelCount;
314     uint8_t                             UvdLevelCount;
315     uint8_t                             VceLevelCount;
316     uint8_t                             AcpLevelCount;
317     uint8_t                             SamuLevelCount;
318     uint8_t                             MasterDeepSleepControl;
319     uint32_t                            Reserved[5];
320 //    uint32_t                            SamuDefaultLevel;
321 
322     SMU7_Discrete_GraphicsLevel         GraphicsLevel           [SMU7_MAX_LEVELS_GRAPHICS];
323     SMU7_Discrete_MemoryLevel           MemoryACPILevel;
324     SMU7_Discrete_MemoryLevel           MemoryLevel             [SMU7_MAX_LEVELS_MEMORY];
325     SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
326     SMU7_Discrete_ACPILevel             ACPILevel;
327     SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
328     SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
329     SMU7_Discrete_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
330     SMU7_Discrete_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
331     SMU7_Discrete_Ulv                   Ulv;
332 
333     uint32_t                            SclkStepSize;
334     uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
335 
336     uint8_t                             UvdBootLevel;
337     uint8_t                             VceBootLevel;
338     uint8_t                             AcpBootLevel;
339     uint8_t                             SamuBootLevel;
340 
341     uint8_t                             UVDInterval;
342     uint8_t                             VCEInterval;
343     uint8_t                             ACPInterval;
344     uint8_t                             SAMUInterval;
345 
346     uint8_t                             GraphicsBootLevel;
347     uint8_t                             GraphicsVoltageChangeEnable;
348     uint8_t                             GraphicsThermThrottleEnable;
349     uint8_t                             GraphicsInterval;
350 
351     uint8_t                             VoltageInterval;
352     uint8_t                             ThermalInterval;
353     uint16_t                            TemperatureLimitHigh;
354 
355     uint16_t                            TemperatureLimitLow;
356     uint8_t                             MemoryBootLevel;
357     uint8_t                             MemoryVoltageChangeEnable;
358 
359     uint8_t                             MemoryInterval;
360     uint8_t                             MemoryThermThrottleEnable;
361     uint16_t                            VddcVddciDelta;
362 
363     uint16_t                            VoltageResponseTime;
364     uint16_t                            PhaseResponseTime;
365 
366     uint8_t                             PCIeBootLinkLevel;
367     uint8_t                             PCIeGenInterval;
368     uint8_t                             DTEInterval;
369     uint8_t                             DTEMode;
370 
371     uint8_t                             SVI2Enable;
372     uint8_t                             VRHotGpio;
373     uint8_t                             AcDcGpio;
374     uint8_t                             ThermGpio;
375 
376     uint16_t                            PPM_PkgPwrLimit;
377     uint16_t                            PPM_TemperatureLimit;
378 
379     uint16_t                            DefaultTdp;
380     uint16_t                            TargetTdp;
381 
382     uint16_t                            FpsHighT;
383     uint16_t                            FpsLowT;
384 
385     uint16_t                            BAPMTI_R  [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
386     uint16_t                            BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
387 
388     uint8_t                             DTEAmbientTempBase;
389     uint8_t                             DTETjOffset;
390     uint8_t                             GpuTjMax;
391     uint8_t                             GpuTjHyst;
392 
393     uint16_t                            BootVddc;
394     uint16_t                            BootVddci;
395 
396     uint16_t                            BootMVdd;
397     uint16_t                            padding;
398 
399     uint32_t                            BAPM_TEMP_GRADIENT;
400 
401     uint32_t                            LowSclkInterruptT;
402 };
403 
404 typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
405 
406 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
407 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
408 
409 struct SMU7_Discrete_MCRegisterAddress
410 {
411     uint16_t s0;
412     uint16_t s1;
413 };
414 
415 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
416 
417 struct SMU7_Discrete_MCRegisterSet
418 {
419     uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
420 };
421 
422 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
423 
424 struct SMU7_Discrete_MCRegisters
425 {
426     uint8_t                             last;
427     uint8_t                             reserved[3];
428     SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
429     SMU7_Discrete_MCRegisterSet         data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
430 };
431 
432 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
433 
434 struct SMU7_Discrete_FanTable
435 {
436 	uint16_t FdoMode;
437 	int16_t  TempMin;
438 	int16_t  TempMed;
439 	int16_t  TempMax;
440 	int16_t  Slope1;
441 	int16_t  Slope2;
442 	int16_t  FdoMin;
443 	int16_t  HystUp;
444 	int16_t  HystDown;
445 	int16_t  HystSlope;
446 	int16_t  TempRespLim;
447 	int16_t  TempCurr;
448 	int16_t  SlopeCurr;
449 	int16_t  PwmCurr;
450 	uint32_t RefreshPeriod;
451 	int16_t  FdoMax;
452 	uint8_t  TempSrc;
453 	int8_t   Padding;
454 };
455 
456 typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
457 
458 
459 struct SMU7_Discrete_PmFuses {
460   // dw0-dw1
461   uint8_t BapmVddCVidHiSidd[8];
462 
463   // dw2-dw3
464   uint8_t BapmVddCVidLoSidd[8];
465 
466   // dw4-dw5
467   uint8_t VddCVid[8];
468 
469   // dw6
470   uint8_t SviLoadLineEn;
471   uint8_t SviLoadLineVddC;
472   uint8_t SviLoadLineTrimVddC;
473   uint8_t SviLoadLineOffsetVddC;
474 
475   // dw7
476   uint16_t TDC_VDDC_PkgLimit;
477   uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
478   uint8_t TDC_MAWt;
479 
480   // dw8
481   uint8_t TdcWaterfallCtl;
482   uint8_t LPMLTemperatureMin;
483   uint8_t LPMLTemperatureMax;
484   uint8_t Reserved;
485 
486   // dw9-dw10
487   uint8_t BapmVddCVidHiSidd2[8];
488 
489   // dw11-dw12
490   int16_t FuzzyFan_ErrorSetDelta;
491   int16_t FuzzyFan_ErrorRateSetDelta;
492   int16_t FuzzyFan_PwmSetDelta;
493   uint16_t CalcMeasPowerBlend;
494 
495   // dw13-dw16
496   uint8_t GnbLPML[16];
497 
498   // dw17
499   uint8_t GnbLPMLMaxVid;
500   uint8_t GnbLPMLMinVid;
501   uint8_t Reserved1[2];
502 
503   // dw18
504   uint16_t BapmVddCBaseLeakageHiSidd;
505   uint16_t BapmVddCBaseLeakageLoSidd;
506 };
507 
508 typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
509 
510 
511 #pragma pack(pop)
512 
513 #endif
514 
515