1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _AV7110_HW_H_
3 #define _AV7110_HW_H_
4
5 #include "av7110.h"
6
7 /* DEBI transfer mode defs */
8
9 #define DEBINOSWAP 0x000e0000
10 #define DEBISWAB 0x001e0000
11 #define DEBISWAP 0x002e0000
12
13 #define ARM_WAIT_FREE (HZ)
14 #define ARM_WAIT_SHAKE (HZ/5)
15 #define ARM_WAIT_OSD (HZ)
16
17
18 enum av7110_bootstate
19 {
20 BOOTSTATE_BUFFER_EMPTY = 0,
21 BOOTSTATE_BUFFER_FULL = 1,
22 BOOTSTATE_AV7110_BOOT_COMPLETE = 2
23 };
24
25 enum av7110_type_rec_play_format
26 { RP_None,
27 AudioPES,
28 AudioMp2,
29 AudioPCM,
30 VideoPES,
31 AV_PES
32 };
33
34 enum av7110_osd_palette_type
35 {
36 NoPalet = 0, /* No palette */
37 Pal1Bit = 2, /* 2 colors for 1 Bit Palette */
38 Pal2Bit = 4, /* 4 colors for 2 bit palette */
39 Pal4Bit = 16, /* 16 colors for 4 bit palette */
40 Pal8Bit = 256 /* 256 colors for 16 bit palette */
41 };
42
43 /* switch defines */
44 #define SB_GPIO 3
45 #define SB_OFF SAA7146_GPIO_OUTLO /* SlowBlank off (TV-Mode) */
46 #define SB_ON SAA7146_GPIO_INPUT /* SlowBlank on (AV-Mode) */
47 #define SB_WIDE SAA7146_GPIO_OUTHI /* SlowBlank 6V (16/9-Mode) (not implemented) */
48
49 #define FB_GPIO 1
50 #define FB_OFF SAA7146_GPIO_LO /* FastBlank off (CVBS-Mode) */
51 #define FB_ON SAA7146_GPIO_OUTHI /* FastBlank on (RGB-Mode) */
52 #define FB_LOOP SAA7146_GPIO_INPUT /* FastBlank loop-through (PC graphics ???) */
53
54 enum av7110_video_output_mode
55 {
56 NO_OUT = 0, /* disable analog output */
57 CVBS_RGB_OUT = 1,
58 CVBS_YC_OUT = 2,
59 YC_OUT = 3
60 };
61
62 /* firmware internal msg q status: */
63 #define GPMQFull 0x0001 /* Main Message Queue Full */
64 #define GPMQOver 0x0002 /* Main Message Queue Overflow */
65 #define HPQFull 0x0004 /* High Priority Msg Queue Full */
66 #define HPQOver 0x0008
67 #define OSDQFull 0x0010 /* OSD Queue Full */
68 #define OSDQOver 0x0020
69 #define GPMQBusy 0x0040 /* Queue not empty, FW >= 261d */
70 #define HPQBusy 0x0080
71 #define OSDQBusy 0x0100
72
73 /* hw section filter flags */
74 #define SECTION_EIT 0x01
75 #define SECTION_SINGLE 0x00
76 #define SECTION_CYCLE 0x02
77 #define SECTION_CONTINUOS 0x04
78 #define SECTION_MODE 0x06
79 #define SECTION_IPMPE 0x0C /* size up to 4k */
80 #define SECTION_HIGH_SPEED 0x1C /* larger buffer */
81 #define DATA_PIPING_FLAG 0x20 /* for Data Piping Filter */
82
83 #define PBUFSIZE_NONE 0x0000
84 #define PBUFSIZE_1P 0x0100
85 #define PBUFSIZE_2P 0x0200
86 #define PBUFSIZE_1K 0x0300
87 #define PBUFSIZE_2K 0x0400
88 #define PBUFSIZE_4K 0x0500
89 #define PBUFSIZE_8K 0x0600
90 #define PBUFSIZE_16K 0x0700
91 #define PBUFSIZE_32K 0x0800
92
93
94 /* firmware command codes */
95 enum av7110_osd_command {
96 WCreate,
97 WDestroy,
98 WMoveD,
99 WMoveA,
100 WHide,
101 WTop,
102 DBox,
103 DLine,
104 DText,
105 Set_Font,
106 SetColor,
107 SetBlend,
108 SetWBlend,
109 SetCBlend,
110 SetNonBlend,
111 LoadBmp,
112 BlitBmp,
113 ReleaseBmp,
114 SetWTrans,
115 SetWNoTrans,
116 Set_Palette
117 };
118
119 enum av7110_pid_command {
120 MultiPID,
121 VideoPID,
122 AudioPID,
123 InitFilt,
124 FiltError,
125 NewVersion,
126 CacheError,
127 AddPIDFilter,
128 DelPIDFilter,
129 Scan,
130 SetDescr,
131 SetIR,
132 FlushTSQueue
133 };
134
135 enum av7110_mpeg_command {
136 SelAudChannels
137 };
138
139 enum av7110_audio_command {
140 AudioDAC,
141 CabADAC,
142 ON22K,
143 OFF22K,
144 MainSwitch,
145 ADSwitch,
146 SendDiSEqC,
147 SetRegister,
148 SpdifSwitch
149 };
150
151 enum av7110_request_command {
152 AudioState,
153 AudioBuffState,
154 VideoState1,
155 VideoState2,
156 VideoState3,
157 CrashCounter,
158 ReqVersion,
159 ReqVCXO,
160 ReqRegister,
161 ReqSecFilterError,
162 ReqSTC
163 };
164
165 enum av7110_encoder_command {
166 SetVidMode,
167 SetTestMode,
168 LoadVidCode,
169 SetMonitorType,
170 SetPanScanType,
171 SetFreezeMode,
172 SetWSSConfig
173 };
174
175 enum av7110_rec_play_state {
176 __Record,
177 __Stop,
178 __Play,
179 __Pause,
180 __Slow,
181 __FF_IP,
182 __Scan_I,
183 __Continue
184 };
185
186 enum av7110_fw_cmd_misc {
187 AV7110_FW_VIDEO_ZOOM = 1,
188 AV7110_FW_VIDEO_COMMAND,
189 AV7110_FW_AUDIO_COMMAND
190 };
191
192 enum av7110_command_type {
193 COMTYPE_NOCOM,
194 COMTYPE_PIDFILTER,
195 COMTYPE_MPEGDECODER,
196 COMTYPE_OSD,
197 COMTYPE_BMP,
198 COMTYPE_ENCODER,
199 COMTYPE_AUDIODAC,
200 COMTYPE_REQUEST,
201 COMTYPE_SYSTEM,
202 COMTYPE_REC_PLAY,
203 COMTYPE_COMMON_IF,
204 COMTYPE_PID_FILTER,
205 COMTYPE_PES,
206 COMTYPE_TS,
207 COMTYPE_VIDEO,
208 COMTYPE_AUDIO,
209 COMTYPE_CI_LL,
210 COMTYPE_MISC = 0x80
211 };
212
213 #define VID_NONE_PREF 0x00 /* No aspect ration processing preferred */
214 #define VID_PAN_SCAN_PREF 0x01 /* Pan and Scan Display preferred */
215 #define VID_VERT_COMP_PREF 0x02 /* Vertical compression display preferred */
216 #define VID_VC_AND_PS_PREF 0x03 /* PanScan and vertical Compression if allowed */
217 #define VID_CENTRE_CUT_PREF 0x05 /* PanScan with zero vector */
218
219 /* MPEG video decoder commands */
220 #define AV_VIDEO_CMD_STOP 0x000e
221 #define AV_VIDEO_CMD_PLAY 0x000d
222 #define AV_VIDEO_CMD_FREEZE 0x0102
223 #define AV_VIDEO_CMD_FFWD 0x0016
224 #define AV_VIDEO_CMD_SLOW 0x0022
225
226 /* MPEG audio decoder commands */
227 #define AUDIO_CMD_MUTE 0x0001
228 #define AUDIO_CMD_UNMUTE 0x0002
229 #define AUDIO_CMD_PCM16 0x0010
230 #define AUDIO_CMD_STEREO 0x0080
231 #define AUDIO_CMD_MONO_L 0x0100
232 #define AUDIO_CMD_MONO_R 0x0200
233 #define AUDIO_CMD_SYNC_OFF 0x000e
234 #define AUDIO_CMD_SYNC_ON 0x000f
235
236 /* firmware data interface codes */
237 #define DATA_NONE 0x00
238 #define DATA_FSECTION 0x01
239 #define DATA_IPMPE 0x02
240 #define DATA_MPEG_RECORD 0x03
241 #define DATA_DEBUG_MESSAGE 0x04
242 #define DATA_COMMON_INTERFACE 0x05
243 #define DATA_MPEG_PLAY 0x06
244 #define DATA_BMP_LOAD 0x07
245 #define DATA_IRCOMMAND 0x08
246 #define DATA_PIPING 0x09
247 #define DATA_STREAMING 0x0a
248 #define DATA_CI_GET 0x0b
249 #define DATA_CI_PUT 0x0c
250 #define DATA_MPEG_VIDEO_EVENT 0x0d
251
252 #define DATA_PES_RECORD 0x10
253 #define DATA_PES_PLAY 0x11
254 #define DATA_TS_RECORD 0x12
255 #define DATA_TS_PLAY 0x13
256
257 /* ancient CI command codes, only two are actually still used
258 * by the link level CI firmware */
259 #define CI_CMD_ERROR 0x00
260 #define CI_CMD_ACK 0x01
261 #define CI_CMD_SYSTEM_READY 0x02
262 #define CI_CMD_KEYPRESS 0x03
263 #define CI_CMD_ON_TUNED 0x04
264 #define CI_CMD_ON_SWITCH_PROGRAM 0x05
265 #define CI_CMD_SECTION_ARRIVED 0x06
266 #define CI_CMD_SECTION_TIMEOUT 0x07
267 #define CI_CMD_TIME 0x08
268 #define CI_CMD_ENTER_MENU 0x09
269 #define CI_CMD_FAST_PSI 0x0a
270 #define CI_CMD_GET_SLOT_INFO 0x0b
271
272 #define CI_MSG_NONE 0x00
273 #define CI_MSG_CI_INFO 0x01
274 #define CI_MSG_MENU 0x02
275 #define CI_MSG_LIST 0x03
276 #define CI_MSG_TEXT 0x04
277 #define CI_MSG_REQUEST_INPUT 0x05
278 #define CI_MSG_INPUT_COMPLETE 0x06
279 #define CI_MSG_LIST_MORE 0x07
280 #define CI_MSG_MENU_MORE 0x08
281 #define CI_MSG_CLOSE_MMI_IMM 0x09
282 #define CI_MSG_SECTION_REQUEST 0x0a
283 #define CI_MSG_CLOSE_FILTER 0x0b
284 #define CI_PSI_COMPLETE 0x0c
285 #define CI_MODULE_READY 0x0d
286 #define CI_SWITCH_PRG_REPLY 0x0e
287 #define CI_MSG_TEXT_MORE 0x0f
288
289 #define CI_MSG_CA_PMT 0xe0
290 #define CI_MSG_ERROR 0xf0
291
292
293 /* base address of the dual ported RAM which serves as communication
294 * area between PCI bus and av7110,
295 * as seen by the DEBI bus of the saa7146 */
296 #define DPRAM_BASE 0x4000
297
298 /* boot protocol area */
299 #define AV7110_BOOT_STATE (DPRAM_BASE + 0x3F8)
300 #define AV7110_BOOT_SIZE (DPRAM_BASE + 0x3FA)
301 #define AV7110_BOOT_BASE (DPRAM_BASE + 0x3FC)
302 #define AV7110_BOOT_BLOCK (DPRAM_BASE + 0x400)
303 #define AV7110_BOOT_MAX_SIZE 0xc00
304
305 /* firmware command protocol area */
306 #define IRQ_STATE (DPRAM_BASE + 0x0F4)
307 #define IRQ_STATE_EXT (DPRAM_BASE + 0x0F6)
308 #define MSGSTATE (DPRAM_BASE + 0x0F8)
309 #define COMMAND (DPRAM_BASE + 0x0FC)
310 #define COM_BUFF (DPRAM_BASE + 0x100)
311 #define COM_BUFF_SIZE 0x20
312
313 /* various data buffers */
314 #define BUFF1_BASE (DPRAM_BASE + 0x120)
315 #define BUFF1_SIZE 0xE0
316
317 #define DATA_BUFF0_BASE (DPRAM_BASE + 0x200)
318 #define DATA_BUFF0_SIZE 0x0800
319
320 #define DATA_BUFF1_BASE (DATA_BUFF0_BASE+DATA_BUFF0_SIZE)
321 #define DATA_BUFF1_SIZE 0x0800
322
323 #define DATA_BUFF2_BASE (DATA_BUFF1_BASE+DATA_BUFF1_SIZE)
324 #define DATA_BUFF2_SIZE 0x0800
325
326 #define DATA_BUFF3_BASE (DATA_BUFF2_BASE+DATA_BUFF2_SIZE)
327 #define DATA_BUFF3_SIZE 0x0400
328
329 #define Reserved (DPRAM_BASE + 0x1E00)
330 #define Reserved_SIZE 0x1C0
331
332
333 /* firmware status area */
334 #define STATUS_BASE (DPRAM_BASE + 0x1FC0)
335 #define STATUS_LOOPS (STATUS_BASE + 0x08)
336
337 #define STATUS_MPEG_WIDTH (STATUS_BASE + 0x0C)
338 /* ((aspect_ratio & 0xf) << 12) | (height & 0xfff) */
339 #define STATUS_MPEG_HEIGHT_AR (STATUS_BASE + 0x0E)
340
341 /* firmware data protocol area */
342 #define RX_TYPE (DPRAM_BASE + 0x1FE8)
343 #define RX_LEN (DPRAM_BASE + 0x1FEA)
344 #define TX_TYPE (DPRAM_BASE + 0x1FEC)
345 #define TX_LEN (DPRAM_BASE + 0x1FEE)
346
347 #define RX_BUFF (DPRAM_BASE + 0x1FF4)
348 #define TX_BUFF (DPRAM_BASE + 0x1FF6)
349
350 #define HANDSHAKE_REG (DPRAM_BASE + 0x1FF8)
351 #define COM_IF_LOCK (DPRAM_BASE + 0x1FFA)
352
353 #define IRQ_RX (DPRAM_BASE + 0x1FFC)
354 #define IRQ_TX (DPRAM_BASE + 0x1FFE)
355
356 /* used by boot protocol to load firmware into av7110 DRAM */
357 #define DRAM_START_CODE 0x2e000404
358 #define DRAM_MAX_CODE_SIZE 0x00100000
359
360 /* saa7146 gpio lines */
361 #define RESET_LINE 2
362 #define DEBI_DONE_LINE 1
363 #define ARM_IRQ_LINE 0
364
365
366
367 extern int av7110_bootarm(struct av7110 *av7110);
368 extern int av7110_firmversion(struct av7110 *av7110);
369 #define FW_CI_LL_SUPPORT(arm_app) ((arm_app) & 0x80000000)
370 #define FW_4M_SDRAM(arm_app) ((arm_app) & 0x40000000)
371 #define FW_VERSION(arm_app) ((arm_app) & 0x0000FFFF)
372
373 extern int av7110_wait_msgstate(struct av7110 *av7110, u16 flags);
374 extern int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...);
375 extern int av7110_fw_request(struct av7110 *av7110, u16 *request_buf,
376 int request_buf_len, u16 *reply_buf, int reply_buf_len);
377
378
379 /* DEBI (saa7146 data extension bus interface) access */
380 extern int av7110_debiwrite(struct av7110 *av7110, u32 config,
381 int addr, u32 val, unsigned int count);
382 extern u32 av7110_debiread(struct av7110 *av7110, u32 config,
383 int addr, unsigned int count);
384
385
386 /* DEBI during interrupt */
387 /* single word writes */
iwdebi(struct av7110 * av7110,u32 config,int addr,u32 val,unsigned int count)388 static inline void iwdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count)
389 {
390 av7110_debiwrite(av7110, config, addr, val, count);
391 }
392
393 /* buffer writes */
mwdebi(struct av7110 * av7110,u32 config,int addr,const u8 * val,int count)394 static inline void mwdebi(struct av7110 *av7110, u32 config, int addr,
395 const u8 *val, int count)
396 {
397 memcpy(av7110->debi_virt, val, count);
398 av7110_debiwrite(av7110, config, addr, 0, count);
399 }
400
irdebi(struct av7110 * av7110,u32 config,int addr,u32 val,unsigned int count)401 static inline u32 irdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count)
402 {
403 u32 res;
404
405 res=av7110_debiread(av7110, config, addr, count);
406 if (count<=4)
407 memcpy(av7110->debi_virt, (char *) &res, count);
408 return res;
409 }
410
411 /* DEBI outside interrupts, only for count <= 4! */
wdebi(struct av7110 * av7110,u32 config,int addr,u32 val,unsigned int count)412 static inline void wdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count)
413 {
414 unsigned long flags;
415
416 spin_lock_irqsave(&av7110->debilock, flags);
417 av7110_debiwrite(av7110, config, addr, val, count);
418 spin_unlock_irqrestore(&av7110->debilock, flags);
419 }
420
rdebi(struct av7110 * av7110,u32 config,int addr,u32 val,unsigned int count)421 static inline u32 rdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count)
422 {
423 unsigned long flags;
424 u32 res;
425
426 spin_lock_irqsave(&av7110->debilock, flags);
427 res=av7110_debiread(av7110, config, addr, count);
428 spin_unlock_irqrestore(&av7110->debilock, flags);
429 return res;
430 }
431
432 /* handle mailbox registers of the dual ported RAM */
ARM_ResetMailBox(struct av7110 * av7110)433 static inline void ARM_ResetMailBox(struct av7110 *av7110)
434 {
435 unsigned long flags;
436
437 spin_lock_irqsave(&av7110->debilock, flags);
438 av7110_debiread(av7110, DEBINOSWAP, IRQ_RX, 2);
439 av7110_debiwrite(av7110, DEBINOSWAP, IRQ_RX, 0, 2);
440 spin_unlock_irqrestore(&av7110->debilock, flags);
441 }
442
ARM_ClearMailBox(struct av7110 * av7110)443 static inline void ARM_ClearMailBox(struct av7110 *av7110)
444 {
445 iwdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2);
446 }
447
ARM_ClearIrq(struct av7110 * av7110)448 static inline void ARM_ClearIrq(struct av7110 *av7110)
449 {
450 irdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2);
451 }
452
453 /****************************************************************************
454 * Firmware commands
455 ****************************************************************************/
456
SendDAC(struct av7110 * av7110,u8 addr,u8 data)457 static inline int SendDAC(struct av7110 *av7110, u8 addr, u8 data)
458 {
459 return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, AudioDAC, 2, addr, data);
460 }
461
av7710_set_video_mode(struct av7110 * av7110,int mode)462 static inline int av7710_set_video_mode(struct av7110 *av7110, int mode)
463 {
464 return av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetVidMode, 1, mode);
465 }
466
vidcom(struct av7110 * av7110,u32 com,u32 arg)467 static inline int vidcom(struct av7110 *av7110, u32 com, u32 arg)
468 {
469 return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_VIDEO_COMMAND, 4,
470 (com>>16), (com&0xffff),
471 (arg>>16), (arg&0xffff));
472 }
473
audcom(struct av7110 * av7110,u32 com)474 static inline int audcom(struct av7110 *av7110, u32 com)
475 {
476 return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_AUDIO_COMMAND, 2,
477 (com>>16), (com&0xffff));
478 }
479
Set22K(struct av7110 * av7110,int state)480 static inline int Set22K(struct av7110 *av7110, int state)
481 {
482 return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, (state ? ON22K : OFF22K), 0);
483 }
484
485
486 extern int av7110_diseqc_send(struct av7110 *av7110, int len, u8 *msg, unsigned long burst);
487
488
489 #ifdef CONFIG_DVB_AV7110_OSD
490 extern int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc);
491 extern int av7110_osd_capability(struct av7110 *av7110, osd_cap_t *cap);
492 #endif /* CONFIG_DVB_AV7110_OSD */
493
494
495
496 #endif /* _AV7110_HW_H_ */
497