1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
4  *
5  * Header file for Host Controller registers and I/O accessors.
6  *
7  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
8  */
9 #ifndef __SDHCI_HW_H
10 #define __SDHCI_HW_H
11 
12 #include <linux/bits.h>
13 #include <linux/scatterlist.h>
14 #include <linux/compiler.h>
15 #include <linux/types.h>
16 #include <linux/io.h>
17 #include <linux/leds.h>
18 #include <linux/interrupt.h>
19 
20 #include <linux/mmc/host.h>
21 
22 /*
23  * Controller registers
24  */
25 
26 #define SDHCI_DMA_ADDRESS	0x00
27 #define SDHCI_ARGUMENT2		SDHCI_DMA_ADDRESS
28 #define SDHCI_32BIT_BLK_CNT	SDHCI_DMA_ADDRESS
29 
30 #define SDHCI_BLOCK_SIZE	0x04
31 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
32 
33 #define SDHCI_BLOCK_COUNT	0x06
34 
35 #define SDHCI_ARGUMENT		0x08
36 
37 #define SDHCI_TRANSFER_MODE	0x0C
38 #define  SDHCI_TRNS_DMA		0x01
39 #define  SDHCI_TRNS_BLK_CNT_EN	0x02
40 #define  SDHCI_TRNS_AUTO_CMD12	0x04
41 #define  SDHCI_TRNS_AUTO_CMD23	0x08
42 #define  SDHCI_TRNS_AUTO_SEL	0x0C
43 #define  SDHCI_TRNS_READ	0x10
44 #define  SDHCI_TRNS_MULTI	0x20
45 
46 #define SDHCI_COMMAND		0x0E
47 #define  SDHCI_CMD_RESP_MASK	0x03
48 #define  SDHCI_CMD_CRC		0x08
49 #define  SDHCI_CMD_INDEX	0x10
50 #define  SDHCI_CMD_DATA		0x20
51 #define  SDHCI_CMD_ABORTCMD	0xC0
52 
53 #define  SDHCI_CMD_RESP_NONE	0x00
54 #define  SDHCI_CMD_RESP_LONG	0x01
55 #define  SDHCI_CMD_RESP_SHORT	0x02
56 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
57 
58 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
59 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
60 
61 #define SDHCI_RESPONSE		0x10
62 
63 #define SDHCI_BUFFER		0x20
64 
65 #define SDHCI_PRESENT_STATE	0x24
66 #define  SDHCI_CMD_INHIBIT	0x00000001
67 #define  SDHCI_DATA_INHIBIT	0x00000002
68 #define  SDHCI_DOING_WRITE	0x00000100
69 #define  SDHCI_DOING_READ	0x00000200
70 #define  SDHCI_SPACE_AVAILABLE	0x00000400
71 #define  SDHCI_DATA_AVAILABLE	0x00000800
72 #define  SDHCI_CARD_PRESENT	0x00010000
73 #define   SDHCI_CARD_PRES_SHIFT	16
74 #define  SDHCI_CD_STABLE	0x00020000
75 #define  SDHCI_CD_LVL		0x00040000
76 #define   SDHCI_CD_LVL_SHIFT	18
77 #define  SDHCI_WRITE_PROTECT	0x00080000
78 #define  SDHCI_DATA_LVL_MASK	0x00F00000
79 #define   SDHCI_DATA_LVL_SHIFT	20
80 #define   SDHCI_DATA_0_LVL_MASK	0x00100000
81 #define  SDHCI_CMD_LVL		0x01000000
82 
83 #define SDHCI_HOST_CONTROL	0x28
84 #define  SDHCI_CTRL_LED		0x01
85 #define  SDHCI_CTRL_4BITBUS	0x02
86 #define  SDHCI_CTRL_HISPD	0x04
87 #define  SDHCI_CTRL_DMA_MASK	0x18
88 #define   SDHCI_CTRL_SDMA	0x00
89 #define   SDHCI_CTRL_ADMA1	0x08
90 #define   SDHCI_CTRL_ADMA32	0x10
91 #define   SDHCI_CTRL_ADMA64	0x18
92 #define   SDHCI_CTRL_ADMA3	0x18
93 #define  SDHCI_CTRL_8BITBUS	0x20
94 #define  SDHCI_CTRL_CDTEST_INS	0x40
95 #define  SDHCI_CTRL_CDTEST_EN	0x80
96 
97 #define SDHCI_POWER_CONTROL	0x29
98 #define  SDHCI_POWER_ON		0x01
99 #define  SDHCI_POWER_180	0x0A
100 #define  SDHCI_POWER_300	0x0C
101 #define  SDHCI_POWER_330	0x0E
102 
103 #define SDHCI_BLOCK_GAP_CONTROL	0x2A
104 
105 #define SDHCI_WAKE_UP_CONTROL	0x2B
106 #define  SDHCI_WAKE_ON_INT	0x01
107 #define  SDHCI_WAKE_ON_INSERT	0x02
108 #define  SDHCI_WAKE_ON_REMOVE	0x04
109 
110 #define SDHCI_CLOCK_CONTROL	0x2C
111 #define  SDHCI_DIVIDER_SHIFT	8
112 #define  SDHCI_DIVIDER_HI_SHIFT	6
113 #define  SDHCI_DIV_MASK	0xFF
114 #define  SDHCI_DIV_MASK_LEN	8
115 #define  SDHCI_DIV_HI_MASK	0x300
116 #define  SDHCI_PROG_CLOCK_MODE	0x0020
117 #define  SDHCI_CLOCK_CARD_EN	0x0004
118 #define  SDHCI_CLOCK_PLL_EN	0x0008
119 #define  SDHCI_CLOCK_INT_STABLE	0x0002
120 #define  SDHCI_CLOCK_INT_EN	0x0001
121 
122 #define SDHCI_TIMEOUT_CONTROL	0x2E
123 
124 #define SDHCI_SOFTWARE_RESET	0x2F
125 #define  SDHCI_RESET_ALL	0x01
126 #define  SDHCI_RESET_CMD	0x02
127 #define  SDHCI_RESET_DATA	0x04
128 
129 #define SDHCI_INT_STATUS	0x30
130 #define SDHCI_INT_ENABLE	0x34
131 #define SDHCI_SIGNAL_ENABLE	0x38
132 #define  SDHCI_INT_RESPONSE	0x00000001
133 #define  SDHCI_INT_DATA_END	0x00000002
134 #define  SDHCI_INT_BLK_GAP	0x00000004
135 #define  SDHCI_INT_DMA_END	0x00000008
136 #define  SDHCI_INT_SPACE_AVAIL	0x00000010
137 #define  SDHCI_INT_DATA_AVAIL	0x00000020
138 #define  SDHCI_INT_CARD_INSERT	0x00000040
139 #define  SDHCI_INT_CARD_REMOVE	0x00000080
140 #define  SDHCI_INT_CARD_INT	0x00000100
141 #define  SDHCI_INT_RETUNE	0x00001000
142 #define  SDHCI_INT_CQE		0x00004000
143 #define  SDHCI_INT_ERROR	0x00008000
144 #define  SDHCI_INT_TIMEOUT	0x00010000
145 #define  SDHCI_INT_CRC		0x00020000
146 #define  SDHCI_INT_END_BIT	0x00040000
147 #define  SDHCI_INT_INDEX	0x00080000
148 #define  SDHCI_INT_DATA_TIMEOUT	0x00100000
149 #define  SDHCI_INT_DATA_CRC	0x00200000
150 #define  SDHCI_INT_DATA_END_BIT	0x00400000
151 #define  SDHCI_INT_BUS_POWER	0x00800000
152 #define  SDHCI_INT_AUTO_CMD_ERR	0x01000000
153 #define  SDHCI_INT_ADMA_ERROR	0x02000000
154 
155 #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
156 #define  SDHCI_INT_ERROR_MASK	0xFFFF8000
157 
158 #define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
159 		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
160 		SDHCI_INT_AUTO_CMD_ERR)
161 #define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
162 		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
163 		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
164 		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
165 		SDHCI_INT_BLK_GAP)
166 #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
167 
168 #define SDHCI_CQE_INT_ERR_MASK ( \
169 	SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
170 	SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
171 	SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
172 
173 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
174 
175 #define SDHCI_AUTO_CMD_STATUS	0x3C
176 #define  SDHCI_AUTO_CMD_TIMEOUT	0x00000002
177 #define  SDHCI_AUTO_CMD_CRC	0x00000004
178 #define  SDHCI_AUTO_CMD_END_BIT	0x00000008
179 #define  SDHCI_AUTO_CMD_INDEX	0x00000010
180 
181 #define SDHCI_HOST_CONTROL2		0x3E
182 #define  SDHCI_CTRL_UHS_MASK		0x0007
183 #define   SDHCI_CTRL_UHS_SDR12		0x0000
184 #define   SDHCI_CTRL_UHS_SDR25		0x0001
185 #define   SDHCI_CTRL_UHS_SDR50		0x0002
186 #define   SDHCI_CTRL_UHS_SDR104		0x0003
187 #define   SDHCI_CTRL_UHS_DDR50		0x0004
188 #define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
189 #define  SDHCI_CTRL_VDD_180		0x0008
190 #define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
191 #define   SDHCI_CTRL_DRV_TYPE_B		0x0000
192 #define   SDHCI_CTRL_DRV_TYPE_A		0x0010
193 #define   SDHCI_CTRL_DRV_TYPE_C		0x0020
194 #define   SDHCI_CTRL_DRV_TYPE_D		0x0030
195 #define  SDHCI_CTRL_EXEC_TUNING		0x0040
196 #define  SDHCI_CTRL_TUNED_CLK		0x0080
197 #define  SDHCI_CMD23_ENABLE		0x0800
198 #define  SDHCI_CTRL_V4_MODE		0x1000
199 #define  SDHCI_CTRL_64BIT_ADDR		0x2000
200 #define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000
201 
202 #define SDHCI_CAPABILITIES	0x40
203 #define  SDHCI_TIMEOUT_CLK_MASK		GENMASK(5, 0)
204 #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
205 #define  SDHCI_CLOCK_BASE_MASK		GENMASK(13, 8)
206 #define  SDHCI_CLOCK_V3_BASE_MASK	GENMASK(15, 8)
207 #define  SDHCI_MAX_BLOCK_MASK	0x00030000
208 #define  SDHCI_MAX_BLOCK_SHIFT  16
209 #define  SDHCI_CAN_DO_8BIT	0x00040000
210 #define  SDHCI_CAN_DO_ADMA2	0x00080000
211 #define  SDHCI_CAN_DO_ADMA1	0x00100000
212 #define  SDHCI_CAN_DO_HISPD	0x00200000
213 #define  SDHCI_CAN_DO_SDMA	0x00400000
214 #define  SDHCI_CAN_DO_SUSPEND	0x00800000
215 #define  SDHCI_CAN_VDD_330	0x01000000
216 #define  SDHCI_CAN_VDD_300	0x02000000
217 #define  SDHCI_CAN_VDD_180	0x04000000
218 #define  SDHCI_CAN_64BIT_V4	0x08000000
219 #define  SDHCI_CAN_64BIT	0x10000000
220 
221 #define SDHCI_CAPABILITIES_1	0x44
222 #define  SDHCI_SUPPORT_SDR50	0x00000001
223 #define  SDHCI_SUPPORT_SDR104	0x00000002
224 #define  SDHCI_SUPPORT_DDR50	0x00000004
225 #define  SDHCI_DRIVER_TYPE_A	0x00000010
226 #define  SDHCI_DRIVER_TYPE_C	0x00000020
227 #define  SDHCI_DRIVER_TYPE_D	0x00000040
228 #define  SDHCI_RETUNING_TIMER_COUNT_MASK	GENMASK(11, 8)
229 #define  SDHCI_USE_SDR50_TUNING			0x00002000
230 #define  SDHCI_RETUNING_MODE_MASK		GENMASK(15, 14)
231 #define  SDHCI_CLOCK_MUL_MASK			GENMASK(23, 16)
232 #define  SDHCI_CAN_DO_ADMA3	0x08000000
233 #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
234 
235 #define SDHCI_MAX_CURRENT		0x48
236 #define  SDHCI_MAX_CURRENT_LIMIT	GENMASK(7, 0)
237 #define  SDHCI_MAX_CURRENT_330_MASK	GENMASK(7, 0)
238 #define  SDHCI_MAX_CURRENT_300_MASK	GENMASK(15, 8)
239 #define  SDHCI_MAX_CURRENT_180_MASK	GENMASK(23, 16)
240 #define   SDHCI_MAX_CURRENT_MULTIPLIER	4
241 
242 /* 4C-4F reserved for more max current */
243 
244 #define SDHCI_SET_ACMD12_ERROR	0x50
245 #define SDHCI_SET_INT_ERROR	0x52
246 
247 #define SDHCI_ADMA_ERROR	0x54
248 
249 /* 55-57 reserved */
250 
251 #define SDHCI_ADMA_ADDRESS	0x58
252 #define SDHCI_ADMA_ADDRESS_HI	0x5C
253 
254 /* 60-FB reserved */
255 
256 #define SDHCI_PRESET_FOR_SDR12 0x66
257 #define SDHCI_PRESET_FOR_SDR25 0x68
258 #define SDHCI_PRESET_FOR_SDR50 0x6A
259 #define SDHCI_PRESET_FOR_SDR104        0x6C
260 #define SDHCI_PRESET_FOR_DDR50 0x6E
261 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
262 #define SDHCI_PRESET_DRV_MASK		GENMASK(15, 14)
263 #define SDHCI_PRESET_CLKGEN_SEL		BIT(10)
264 #define SDHCI_PRESET_SDCLK_FREQ_MASK	GENMASK(9, 0)
265 
266 #define SDHCI_SLOT_INT_STATUS	0xFC
267 
268 #define SDHCI_HOST_VERSION	0xFE
269 #define  SDHCI_VENDOR_VER_MASK	0xFF00
270 #define  SDHCI_VENDOR_VER_SHIFT	8
271 #define  SDHCI_SPEC_VER_MASK	0x00FF
272 #define  SDHCI_SPEC_VER_SHIFT	0
273 #define   SDHCI_SPEC_100	0
274 #define   SDHCI_SPEC_200	1
275 #define   SDHCI_SPEC_300	2
276 #define   SDHCI_SPEC_400	3
277 #define   SDHCI_SPEC_410	4
278 #define   SDHCI_SPEC_420	5
279 
280 /*
281  * End of controller registers.
282  */
283 
284 #define SDHCI_MAX_DIV_SPEC_200	256
285 #define SDHCI_MAX_DIV_SPEC_300	2046
286 
287 /*
288  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
289  */
290 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
291 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
292 
293 /* ADMA2 32-bit DMA descriptor size */
294 #define SDHCI_ADMA2_32_DESC_SZ	8
295 
296 /* ADMA2 32-bit descriptor */
297 struct sdhci_adma2_32_desc {
298 	__le16	cmd;
299 	__le16	len;
300 	__le32	addr;
301 }  __packed __aligned(4);
302 
303 /* ADMA2 data alignment */
304 #define SDHCI_ADMA2_ALIGN	4
305 #define SDHCI_ADMA2_MASK	(SDHCI_ADMA2_ALIGN - 1)
306 
307 /*
308  * ADMA2 descriptor alignment.  Some controllers (e.g. Intel) require 8 byte
309  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
310  * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
311  */
312 #define SDHCI_ADMA2_DESC_ALIGN	8
313 
314 /*
315  * ADMA2 64-bit DMA descriptor size
316  * According to SD Host Controller spec v4.10, there are two kinds of
317  * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
318  * Descriptor, if Host Version 4 Enable is set in the Host Control 2
319  * register, 128-bit Descriptor will be selected.
320  */
321 #define SDHCI_ADMA2_64_DESC_SZ(host)	((host)->v4_mode ? 16 : 12)
322 
323 /*
324  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
325  * aligned.
326  */
327 struct sdhci_adma2_64_desc {
328 	__le16	cmd;
329 	__le16	len;
330 	__le32	addr_lo;
331 	__le32	addr_hi;
332 }  __packed __aligned(4);
333 
334 #define ADMA2_TRAN_VALID	0x21
335 #define ADMA2_NOP_END_VALID	0x3
336 #define ADMA2_END		0x2
337 
338 /*
339  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
340  * 4KiB page size.
341  */
342 #define SDHCI_MAX_SEGS		128
343 
344 /* Allow for a a command request and a data request at the same time */
345 #define SDHCI_MAX_MRQS		2
346 
347 /*
348  * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
349  * However since the start time of the command, the time between
350  * command and response, and the time between response and start of data is
351  * not known, set the command transfer time to 10ms.
352  */
353 #define MMC_CMD_TRANSFER_TIME	(10 * NSEC_PER_MSEC) /* max 10 ms */
354 
355 enum sdhci_cookie {
356 	COOKIE_UNMAPPED,
357 	COOKIE_PRE_MAPPED,	/* mapped by sdhci_pre_req() */
358 	COOKIE_MAPPED,		/* mapped by sdhci_prepare_data() */
359 };
360 
361 struct sdhci_host {
362 	/* Data set by hardware interface driver */
363 	const char *hw_name;	/* Hardware bus name */
364 
365 	unsigned int quirks;	/* Deviations from spec. */
366 
367 /* Controller doesn't honor resets unless we touch the clock register */
368 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
369 /* Controller has bad caps bits, but really supports DMA */
370 #define SDHCI_QUIRK_FORCE_DMA				(1<<1)
371 /* Controller doesn't like to be reset when there is no card inserted. */
372 #define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
373 /* Controller doesn't like clearing the power reg before a change */
374 #define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
375 /* Controller has flaky internal state so reset it on each ios change */
376 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
377 /* Controller has an unusable DMA engine */
378 #define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
379 /* Controller has an unusable ADMA engine */
380 #define SDHCI_QUIRK_BROKEN_ADMA				(1<<6)
381 /* Controller can only DMA from 32-bit aligned addresses */
382 #define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<7)
383 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
384 #define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<8)
385 /* Controller can only ADMA chunks that are a multiple of 32 bits */
386 #define SDHCI_QUIRK_32BIT_ADMA_SIZE			(1<<9)
387 /* Controller needs to be reset after each request to stay stable */
388 #define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<10)
389 /* Controller needs voltage and power writes to happen separately */
390 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<11)
391 /* Controller provides an incorrect timeout value for transfers */
392 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1<<12)
393 /* Controller has an issue with buffer bits for small transfers */
394 #define SDHCI_QUIRK_BROKEN_SMALL_PIO			(1<<13)
395 /* Controller does not provide transfer-complete interrupt when not busy */
396 #define SDHCI_QUIRK_NO_BUSY_IRQ				(1<<14)
397 /* Controller has unreliable card detection */
398 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION		(1<<15)
399 /* Controller reports inverted write-protect state */
400 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT		(1<<16)
401 /* Controller has unusable command queue engine */
402 #define SDHCI_QUIRK_BROKEN_CQE				(1<<17)
403 /* Controller does not like fast PIO transfers */
404 #define SDHCI_QUIRK_PIO_NEEDS_DELAY			(1<<18)
405 /* Controller does not have a LED */
406 #define SDHCI_QUIRK_NO_LED				(1<<19)
407 /* Controller has to be forced to use block size of 2048 bytes */
408 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048			(1<<20)
409 /* Controller cannot do multi-block transfers */
410 #define SDHCI_QUIRK_NO_MULTIBLOCK			(1<<21)
411 /* Controller can only handle 1-bit data transfers */
412 #define SDHCI_QUIRK_FORCE_1_BIT_DATA			(1<<22)
413 /* Controller needs 10ms delay between applying power and clock */
414 #define SDHCI_QUIRK_DELAY_AFTER_POWER			(1<<23)
415 /* Controller uses SDCLK instead of TMCLK for data timeouts */
416 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK		(1<<24)
417 /* Controller reports wrong base clock capability */
418 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
419 /* Controller cannot support End Attribute in NOP ADMA descriptor */
420 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
421 /* Controller is missing device caps. Use caps provided by host */
422 #define SDHCI_QUIRK_MISSING_CAPS			(1<<27)
423 /* Controller uses Auto CMD12 command to stop the transfer */
424 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12		(1<<28)
425 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
426 #define SDHCI_QUIRK_NO_HISPD_BIT			(1<<29)
427 /* Controller treats ADMA descriptors with length 0000h incorrectly */
428 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC		(1<<30)
429 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
430 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1<<31)
431 
432 	unsigned int quirks2;	/* More deviations from spec. */
433 
434 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON			(1<<0)
435 #define SDHCI_QUIRK2_HOST_NO_CMD23			(1<<1)
436 /* The system physically doesn't support 1.8v, even if the host does */
437 #define SDHCI_QUIRK2_NO_1_8_V				(1<<2)
438 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN		(1<<3)
439 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON		(1<<4)
440 /* Controller has a non-standard host control register */
441 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL		(1<<5)
442 /* Controller does not support HS200 */
443 #define SDHCI_QUIRK2_BROKEN_HS200			(1<<6)
444 /* Controller does not support DDR50 */
445 #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
446 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
447 #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
448 /* Controller does not support 64-bit DMA */
449 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA			(1<<9)
450 /* need clear transfer mode register before send cmd */
451 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
452 /* Capability register bit-63 indicates HS400 support */
453 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<11)
454 /* forced tuned clock */
455 #define SDHCI_QUIRK2_TUNING_WORK_AROUND			(1<<12)
456 /* disable the block count for single block transactions */
457 #define SDHCI_QUIRK2_SUPPORT_SINGLE			(1<<13)
458 /* Controller broken with using ACMD23 */
459 #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
460 /* Broken Clock divider zero in controller */
461 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
462 /* Controller has CRC in 136 bit Command Response */
463 #define SDHCI_QUIRK2_RSP_136_HAS_CRC			(1<<16)
464 /*
465  * Disable HW timeout if the requested timeout is more than the maximum
466  * obtainable timeout.
467  */
468 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT			(1<<17)
469 /*
470  * 32-bit block count may not support eMMC where upper bits of CMD23 are used
471  * for other purposes.  Consequently we support 16-bit block count by default.
472  * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
473  * block count.
474  */
475 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT			(1<<18)
476 
477 	int irq;		/* Device IRQ */
478 	void __iomem *ioaddr;	/* Mapped address */
479 	phys_addr_t mapbase;	/* physical address base */
480 	char *bounce_buffer;	/* For packing SDMA reads/writes */
481 	dma_addr_t bounce_addr;
482 	unsigned int bounce_buffer_size;
483 
484 	const struct sdhci_ops *ops;	/* Low level hw interface */
485 
486 	/* Internal data */
487 	struct mmc_host *mmc;	/* MMC structure */
488 	struct mmc_host_ops mmc_host_ops;	/* MMC host ops */
489 	u64 dma_mask;		/* custom DMA mask */
490 
491 #if IS_ENABLED(CONFIG_LEDS_CLASS)
492 	struct led_classdev led;	/* LED control */
493 	char led_name[32];
494 #endif
495 
496 	spinlock_t lock;	/* Mutex */
497 
498 	int flags;		/* Host attributes */
499 #define SDHCI_USE_SDMA		(1<<0)	/* Host is SDMA capable */
500 #define SDHCI_USE_ADMA		(1<<1)	/* Host is ADMA capable */
501 #define SDHCI_REQ_USE_DMA	(1<<2)	/* Use DMA for this req. */
502 #define SDHCI_DEVICE_DEAD	(1<<3)	/* Device unresponsive */
503 #define SDHCI_SDR50_NEEDS_TUNING (1<<4)	/* SDR50 needs tuning */
504 #define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
505 #define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
506 #define SDHCI_PV_ENABLED	(1<<8)	/* Preset value enabled */
507 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
508 #define SDHCI_HS400_TUNING	(1<<13)	/* Tuning for HS400 */
509 #define SDHCI_SIGNALING_330	(1<<14)	/* Host is capable of 3.3V signaling */
510 #define SDHCI_SIGNALING_180	(1<<15)	/* Host is capable of 1.8V signaling */
511 #define SDHCI_SIGNALING_120	(1<<16)	/* Host is capable of 1.2V signaling */
512 
513 	unsigned int version;	/* SDHCI spec. version */
514 
515 	unsigned int max_clk;	/* Max possible freq (MHz) */
516 	unsigned int timeout_clk;	/* Timeout freq (KHz) */
517 	unsigned int clk_mul;	/* Clock Muliplier value */
518 
519 	unsigned int clock;	/* Current clock (MHz) */
520 	u8 pwr;			/* Current voltage */
521 
522 	bool runtime_suspended;	/* Host is runtime suspended */
523 	bool bus_on;		/* Bus power prevents runtime suspend */
524 	bool preset_enabled;	/* Preset is enabled */
525 	bool pending_reset;	/* Cmd/data reset is pending */
526 	bool irq_wake_enabled;	/* IRQ wakeup is enabled */
527 	bool v4_mode;		/* Host Version 4 Enable */
528 	bool use_external_dma;	/* Host selects to use external DMA */
529 	bool always_defer_done;	/* Always defer to complete requests */
530 
531 	struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];	/* Requests done */
532 	struct mmc_command *cmd;	/* Current command */
533 	struct mmc_command *data_cmd;	/* Current data command */
534 	struct mmc_command *deferred_cmd;	/* Deferred command */
535 	struct mmc_data *data;	/* Current data request */
536 	unsigned int data_early:1;	/* Data finished before cmd */
537 
538 	struct sg_mapping_iter sg_miter;	/* SG state for PIO */
539 	unsigned int blocks;	/* remaining PIO blocks */
540 
541 	int sg_count;		/* Mapped sg entries */
542 
543 	void *adma_table;	/* ADMA descriptor table */
544 	void *align_buffer;	/* Bounce buffer */
545 
546 	size_t adma_table_sz;	/* ADMA descriptor table size */
547 	size_t align_buffer_sz;	/* Bounce buffer size */
548 
549 	dma_addr_t adma_addr;	/* Mapped ADMA descr. table */
550 	dma_addr_t align_addr;	/* Mapped bounce buffer */
551 
552 	unsigned int desc_sz;	/* ADMA current descriptor size */
553 	unsigned int alloc_desc_sz;	/* ADMA descr. max size host supports */
554 
555 	struct workqueue_struct *complete_wq;	/* Request completion wq */
556 	struct work_struct	complete_work;	/* Request completion work */
557 
558 	struct timer_list timer;	/* Timer for timeouts */
559 	struct timer_list data_timer;	/* Timer for data timeouts */
560 
561 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
562 	struct dma_chan *rx_chan;
563 	struct dma_chan *tx_chan;
564 #endif
565 
566 	u32 caps;		/* CAPABILITY_0 */
567 	u32 caps1;		/* CAPABILITY_1 */
568 	bool read_caps;		/* Capability flags have been read */
569 
570 	bool sdhci_core_to_disable_vqmmc;  /* sdhci core can disable vqmmc */
571 	unsigned int            ocr_avail_sdio;	/* OCR bit masks */
572 	unsigned int            ocr_avail_sd;
573 	unsigned int            ocr_avail_mmc;
574 	u32 ocr_mask;		/* available voltages */
575 
576 	unsigned		timing;		/* Current timing */
577 
578 	u32			thread_isr;
579 
580 	/* cached registers */
581 	u32			ier;
582 
583 	bool			cqe_on;		/* CQE is operating */
584 	u32			cqe_ier;	/* CQE interrupt mask */
585 	u32			cqe_err_ier;	/* CQE error interrupt mask */
586 
587 	wait_queue_head_t	buf_ready_int;	/* Waitqueue for Buffer Read Ready interrupt */
588 	unsigned int		tuning_done;	/* Condition flag set when CMD19 succeeds */
589 
590 	unsigned int		tuning_count;	/* Timer count for re-tuning */
591 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
592 	unsigned int		tuning_err;	/* Error code for re-tuning */
593 #define SDHCI_TUNING_MODE_1	0
594 #define SDHCI_TUNING_MODE_2	1
595 #define SDHCI_TUNING_MODE_3	2
596 	/* Delay (ms) between tuning commands */
597 	int			tuning_delay;
598 	int			tuning_loop_count;
599 
600 	/* Host SDMA buffer boundary. */
601 	u32			sdma_boundary;
602 
603 	/* Host ADMA table count */
604 	u32			adma_table_cnt;
605 
606 	u64			data_timeout;
607 
608 	unsigned long private[] ____cacheline_aligned;
609 };
610 
611 struct sdhci_ops {
612 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
613 	u32		(*read_l)(struct sdhci_host *host, int reg);
614 	u16		(*read_w)(struct sdhci_host *host, int reg);
615 	u8		(*read_b)(struct sdhci_host *host, int reg);
616 	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
617 	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
618 	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
619 #endif
620 
621 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);
622 	void	(*set_power)(struct sdhci_host *host, unsigned char mode,
623 			     unsigned short vdd);
624 
625 	u32		(*irq)(struct sdhci_host *host, u32 intmask);
626 
627 	int		(*set_dma_mask)(struct sdhci_host *host);
628 	int		(*enable_dma)(struct sdhci_host *host);
629 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
630 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
631 	/* get_timeout_clock should return clk rate in unit of Hz */
632 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
633 	unsigned int	(*get_max_timeout_count)(struct sdhci_host *host);
634 	void		(*set_timeout)(struct sdhci_host *host,
635 				       struct mmc_command *cmd);
636 	void		(*set_bus_width)(struct sdhci_host *host, int width);
637 	void (*platform_send_init_74_clocks)(struct sdhci_host *host,
638 					     u8 power_mode);
639 	unsigned int    (*get_ro)(struct sdhci_host *host);
640 	void		(*reset)(struct sdhci_host *host, u8 mask);
641 	int	(*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
642 	void	(*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
643 	void	(*hw_reset)(struct sdhci_host *host);
644 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
645 	void    (*card_event)(struct sdhci_host *host);
646 	void	(*voltage_switch)(struct sdhci_host *host);
647 	void	(*adma_write_desc)(struct sdhci_host *host, void **desc,
648 				   dma_addr_t addr, int len, unsigned int cmd);
649 	void	(*copy_to_bounce_buffer)(struct sdhci_host *host,
650 					 struct mmc_data *data,
651 					 unsigned int length);
652 	void	(*request_done)(struct sdhci_host *host,
653 				struct mmc_request *mrq);
654 	void    (*dump_vendor_regs)(struct sdhci_host *host);
655 };
656 
657 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
658 
sdhci_writel(struct sdhci_host * host,u32 val,int reg)659 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
660 {
661 	if (unlikely(host->ops->write_l))
662 		host->ops->write_l(host, val, reg);
663 	else
664 		writel(val, host->ioaddr + reg);
665 }
666 
sdhci_writew(struct sdhci_host * host,u16 val,int reg)667 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
668 {
669 	if (unlikely(host->ops->write_w))
670 		host->ops->write_w(host, val, reg);
671 	else
672 		writew(val, host->ioaddr + reg);
673 }
674 
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)675 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
676 {
677 	if (unlikely(host->ops->write_b))
678 		host->ops->write_b(host, val, reg);
679 	else
680 		writeb(val, host->ioaddr + reg);
681 }
682 
sdhci_readl(struct sdhci_host * host,int reg)683 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
684 {
685 	if (unlikely(host->ops->read_l))
686 		return host->ops->read_l(host, reg);
687 	else
688 		return readl(host->ioaddr + reg);
689 }
690 
sdhci_readw(struct sdhci_host * host,int reg)691 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
692 {
693 	if (unlikely(host->ops->read_w))
694 		return host->ops->read_w(host, reg);
695 	else
696 		return readw(host->ioaddr + reg);
697 }
698 
sdhci_readb(struct sdhci_host * host,int reg)699 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
700 {
701 	if (unlikely(host->ops->read_b))
702 		return host->ops->read_b(host, reg);
703 	else
704 		return readb(host->ioaddr + reg);
705 }
706 
707 #else
708 
sdhci_writel(struct sdhci_host * host,u32 val,int reg)709 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
710 {
711 	writel(val, host->ioaddr + reg);
712 }
713 
sdhci_writew(struct sdhci_host * host,u16 val,int reg)714 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
715 {
716 	writew(val, host->ioaddr + reg);
717 }
718 
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)719 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
720 {
721 	writeb(val, host->ioaddr + reg);
722 }
723 
sdhci_readl(struct sdhci_host * host,int reg)724 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
725 {
726 	return readl(host->ioaddr + reg);
727 }
728 
sdhci_readw(struct sdhci_host * host,int reg)729 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
730 {
731 	return readw(host->ioaddr + reg);
732 }
733 
sdhci_readb(struct sdhci_host * host,int reg)734 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
735 {
736 	return readb(host->ioaddr + reg);
737 }
738 
739 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
740 
741 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
742 void sdhci_free_host(struct sdhci_host *host);
743 
sdhci_priv(struct sdhci_host * host)744 static inline void *sdhci_priv(struct sdhci_host *host)
745 {
746 	return host->private;
747 }
748 
749 void sdhci_card_detect(struct sdhci_host *host);
750 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
751 		       const u32 *caps, const u32 *caps1);
752 int sdhci_setup_host(struct sdhci_host *host);
753 void sdhci_cleanup_host(struct sdhci_host *host);
754 int __sdhci_add_host(struct sdhci_host *host);
755 int sdhci_add_host(struct sdhci_host *host);
756 void sdhci_remove_host(struct sdhci_host *host, int dead);
757 
sdhci_read_caps(struct sdhci_host * host)758 static inline void sdhci_read_caps(struct sdhci_host *host)
759 {
760 	__sdhci_read_caps(host, NULL, NULL, NULL);
761 }
762 
763 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
764 		   unsigned int *actual_clock);
765 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
766 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
767 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
768 		     unsigned short vdd);
769 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
770 				     unsigned char mode,
771 				     unsigned short vdd);
772 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
773 			   unsigned short vdd);
774 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
775 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
776 void sdhci_set_bus_width(struct sdhci_host *host, int width);
777 void sdhci_reset(struct sdhci_host *host, u8 mask);
778 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
779 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
780 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
781 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
782 				      struct mmc_ios *ios);
783 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
784 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
785 			   dma_addr_t addr, int len, unsigned int cmd);
786 
787 #ifdef CONFIG_PM
788 int sdhci_suspend_host(struct sdhci_host *host);
789 int sdhci_resume_host(struct sdhci_host *host);
790 int sdhci_runtime_suspend_host(struct sdhci_host *host);
791 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
792 #endif
793 
794 void sdhci_cqe_enable(struct mmc_host *mmc);
795 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
796 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
797 		   int *data_error);
798 
799 void sdhci_dumpregs(struct sdhci_host *host);
800 void sdhci_enable_v4_mode(struct sdhci_host *host);
801 
802 void sdhci_start_tuning(struct sdhci_host *host);
803 void sdhci_end_tuning(struct sdhci_host *host);
804 void sdhci_reset_tuning(struct sdhci_host *host);
805 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
806 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
807 void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
808 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
809 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
810 
811 #endif /* __SDHCI_HW_H */
812