1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "fpga/core.h"
64 #include "fpga/ipsec.h"
65 #include "accel/ipsec.h"
66 #include "accel/tls.h"
67 #include "lib/clock.h"
68 #include "lib/vxlan.h"
69 #include "lib/geneve.h"
70 #include "lib/devcom.h"
71 #include "lib/pci_vsc.h"
72 #include "diag/fw_tracer.h"
73 #include "ecpf.h"
74 #include "lib/hv_vhca.h"
75 #include "diag/rsc_dump.h"
76 #include "sf/vhca_event.h"
77 #include "sf/dev/dev.h"
78 #include "sf/sf.h"
79
80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
82 MODULE_LICENSE("Dual BSD/GPL");
83
84 unsigned int mlx5_core_debug_mask;
85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
87
88 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
89 module_param_named(prof_sel, prof_sel, uint, 0444);
90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
91
92 static u32 sw_owner_id[4];
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 static struct mlx5_profile profile[] = {
100 [0] = {
101 .mask = 0,
102 },
103 [1] = {
104 .mask = MLX5_PROF_MASK_QP_SIZE,
105 .log_max_qp = 12,
106 },
107 [2] = {
108 .mask = MLX5_PROF_MASK_QP_SIZE |
109 MLX5_PROF_MASK_MR_CACHE,
110 .log_max_qp = 18,
111 .mr_cache[0] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[1] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[2] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[3] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[4] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[5] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[6] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[7] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[8] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[9] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[10] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[11] = {
156 .size = 500,
157 .limit = 250
158 },
159 .mr_cache[12] = {
160 .size = 64,
161 .limit = 32
162 },
163 .mr_cache[13] = {
164 .size = 32,
165 .limit = 16
166 },
167 .mr_cache[14] = {
168 .size = 16,
169 .limit = 8
170 },
171 .mr_cache[15] = {
172 .size = 8,
173 .limit = 4
174 },
175 },
176 };
177
178 #define FW_INIT_TIMEOUT_MILI 2000
179 #define FW_INIT_WAIT_MS 2
180 #define FW_PRE_INIT_TIMEOUT_MILI 120000
181 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
182
fw_initializing(struct mlx5_core_dev * dev)183 static int fw_initializing(struct mlx5_core_dev *dev)
184 {
185 return ioread32be(&dev->iseg->initializing) >> 31;
186 }
187
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)188 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
189 u32 warn_time_mili)
190 {
191 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
192 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
193 int err = 0;
194
195 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
196
197 while (fw_initializing(dev)) {
198 if (time_after(jiffies, end)) {
199 err = -EBUSY;
200 break;
201 }
202 if (warn_time_mili && time_after(jiffies, warn)) {
203 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
204 jiffies_to_msecs(end - warn) / 1000);
205 warn = jiffies + msecs_to_jiffies(warn_time_mili);
206 }
207 msleep(FW_INIT_WAIT_MS);
208 }
209
210 return err;
211 }
212
mlx5_set_driver_version(struct mlx5_core_dev * dev)213 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
214 {
215 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
216 driver_version);
217 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
218 int remaining_size = driver_ver_sz;
219 char *string;
220
221 if (!MLX5_CAP_GEN(dev, driver_version))
222 return;
223
224 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
225
226 strncpy(string, "Linux", remaining_size);
227
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, ",", remaining_size);
230
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, KBUILD_MODNAME, remaining_size);
233
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235 strncat(string, ",", remaining_size);
236
237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
238
239 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
240 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
241 LINUX_VERSION_SUBLEVEL);
242
243 /*Send the command*/
244 MLX5_SET(set_driver_version_in, in, opcode,
245 MLX5_CMD_OP_SET_DRIVER_VERSION);
246
247 mlx5_cmd_exec_in(dev, set_driver_version, in);
248 }
249
set_dma_caps(struct pci_dev * pdev)250 static int set_dma_caps(struct pci_dev *pdev)
251 {
252 int err;
253
254 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
255 if (err) {
256 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
257 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
258 if (err) {
259 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
260 return err;
261 }
262 }
263
264 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
265 if (err) {
266 dev_warn(&pdev->dev,
267 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
268 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
269 if (err) {
270 dev_err(&pdev->dev,
271 "Can't set consistent PCI DMA mask, aborting\n");
272 return err;
273 }
274 }
275
276 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
277 return err;
278 }
279
mlx5_pci_enable_device(struct mlx5_core_dev * dev)280 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
281 {
282 struct pci_dev *pdev = dev->pdev;
283 int err = 0;
284
285 mutex_lock(&dev->pci_status_mutex);
286 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
287 err = pci_enable_device(pdev);
288 if (!err)
289 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
290 }
291 mutex_unlock(&dev->pci_status_mutex);
292
293 return err;
294 }
295
mlx5_pci_disable_device(struct mlx5_core_dev * dev)296 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
297 {
298 struct pci_dev *pdev = dev->pdev;
299
300 mutex_lock(&dev->pci_status_mutex);
301 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
302 pci_disable_device(pdev);
303 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
304 }
305 mutex_unlock(&dev->pci_status_mutex);
306 }
307
request_bar(struct pci_dev * pdev)308 static int request_bar(struct pci_dev *pdev)
309 {
310 int err = 0;
311
312 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
313 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
314 return -ENODEV;
315 }
316
317 err = pci_request_regions(pdev, KBUILD_MODNAME);
318 if (err)
319 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
320
321 return err;
322 }
323
release_bar(struct pci_dev * pdev)324 static void release_bar(struct pci_dev *pdev)
325 {
326 pci_release_regions(pdev);
327 }
328
329 struct mlx5_reg_host_endianness {
330 u8 he;
331 u8 rsvd[15];
332 };
333
334 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
335
336 enum {
337 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
338 MLX5_DEV_CAP_FLAG_DCT,
339 };
340
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)341 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
342 {
343 switch (size) {
344 case 128:
345 return 0;
346 case 256:
347 return 1;
348 case 512:
349 return 2;
350 case 1024:
351 return 3;
352 case 2048:
353 return 4;
354 case 4096:
355 return 5;
356 default:
357 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
358 return 0;
359 }
360 }
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
363 enum mlx5_cap_type cap_type,
364 enum mlx5_cap_mode cap_mode)
365 {
366 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
367 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
368 void *out, *hca_caps;
369 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
370 int err;
371
372 memset(in, 0, sizeof(in));
373 out = kzalloc(out_sz, GFP_KERNEL);
374 if (!out)
375 return -ENOMEM;
376
377 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
378 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
379 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
380 if (err) {
381 mlx5_core_warn(dev,
382 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
383 cap_type, cap_mode, err);
384 goto query_ex;
385 }
386
387 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
388
389 switch (cap_mode) {
390 case HCA_CAP_OPMOD_GET_MAX:
391 memcpy(dev->caps.hca_max[cap_type], hca_caps,
392 MLX5_UN_SZ_BYTES(hca_cap_union));
393 break;
394 case HCA_CAP_OPMOD_GET_CUR:
395 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
396 MLX5_UN_SZ_BYTES(hca_cap_union));
397 break;
398 default:
399 mlx5_core_warn(dev,
400 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
401 cap_type, cap_mode);
402 err = -EINVAL;
403 break;
404 }
405 query_ex:
406 kfree(out);
407 return err;
408 }
409
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)410 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
411 {
412 int ret;
413
414 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
415 if (ret)
416 return ret;
417 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
418 }
419
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)420 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
421 {
422 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
423 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
424 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
425 }
426
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)427 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
428 {
429 void *set_hca_cap;
430 int req_endianness;
431 int err;
432
433 if (!MLX5_CAP_GEN(dev, atomic))
434 return 0;
435
436 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
437 if (err)
438 return err;
439
440 req_endianness =
441 MLX5_CAP_ATOMIC(dev,
442 supported_atomic_req_8B_endianness_mode_1);
443
444 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
445 return 0;
446
447 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
448
449 /* Set requestor to host endianness */
450 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
451 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
452
453 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
454 }
455
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)456 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
457 {
458 void *set_hca_cap;
459 bool do_set = false;
460 int err;
461
462 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
463 !MLX5_CAP_GEN(dev, pg))
464 return 0;
465
466 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
467 if (err)
468 return err;
469
470 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
471 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
472 MLX5_ST_SZ_BYTES(odp_cap));
473
474 #define ODP_CAP_SET_MAX(dev, field) \
475 do { \
476 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
477 if (_res) { \
478 do_set = true; \
479 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
480 } \
481 } while (0)
482
483 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
484 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
490 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
492 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
495 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
496 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
497
498 if (!do_set)
499 return 0;
500
501 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
502 }
503
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)504 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
505 {
506 struct mlx5_profile *prof = dev->profile;
507 void *set_hca_cap;
508 int err;
509
510 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
511 if (err)
512 return err;
513
514 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
515 capability);
516 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
517 MLX5_ST_SZ_BYTES(cmd_hca_cap));
518
519 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
520 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
521 128);
522 /* we limit the size of the pkey table to 128 entries for now */
523 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
524 to_fw_pkey_sz(dev, 128));
525
526 /* Check log_max_qp from HCA caps to set in current profile */
527 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
528 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
529 profile[prof_sel].log_max_qp,
530 MLX5_CAP_GEN_MAX(dev, log_max_qp));
531 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
532 }
533 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
534 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
535 prof->log_max_qp);
536
537 /* disable cmdif checksum */
538 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
539
540 /* Enable 4K UAR only when HCA supports it and page size is bigger
541 * than 4K.
542 */
543 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
544 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
545
546 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
547
548 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
549 MLX5_SET(cmd_hca_cap,
550 set_hca_cap,
551 cache_line_128byte,
552 cache_line_size() >= 128 ? 1 : 0);
553
554 if (MLX5_CAP_GEN_MAX(dev, dct))
555 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
556
557 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
559
560 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
561 MLX5_SET(cmd_hca_cap,
562 set_hca_cap,
563 num_vhca_ports,
564 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
565
566 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
567 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
568
569 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
570 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
571
572 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
573
574 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
575 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
576 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
577
578 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
579 }
580
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)581 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
582 {
583 void *set_hca_cap;
584 int err;
585
586 if (!MLX5_CAP_GEN(dev, roce))
587 return 0;
588
589 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
590 if (err)
591 return err;
592
593 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
594 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
595 return 0;
596
597 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
598 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
599 MLX5_ST_SZ_BYTES(roce_cap));
600 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
601
602 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
603 return err;
604 }
605
set_hca_cap(struct mlx5_core_dev * dev)606 static int set_hca_cap(struct mlx5_core_dev *dev)
607 {
608 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
609 void *set_ctx;
610 int err;
611
612 set_ctx = kzalloc(set_sz, GFP_KERNEL);
613 if (!set_ctx)
614 return -ENOMEM;
615
616 err = handle_hca_cap(dev, set_ctx);
617 if (err) {
618 mlx5_core_err(dev, "handle_hca_cap failed\n");
619 goto out;
620 }
621
622 memset(set_ctx, 0, set_sz);
623 err = handle_hca_cap_atomic(dev, set_ctx);
624 if (err) {
625 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
626 goto out;
627 }
628
629 memset(set_ctx, 0, set_sz);
630 err = handle_hca_cap_odp(dev, set_ctx);
631 if (err) {
632 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
633 goto out;
634 }
635
636 memset(set_ctx, 0, set_sz);
637 err = handle_hca_cap_roce(dev, set_ctx);
638 if (err) {
639 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
640 goto out;
641 }
642
643 out:
644 kfree(set_ctx);
645 return err;
646 }
647
set_hca_ctrl(struct mlx5_core_dev * dev)648 static int set_hca_ctrl(struct mlx5_core_dev *dev)
649 {
650 struct mlx5_reg_host_endianness he_in;
651 struct mlx5_reg_host_endianness he_out;
652 int err;
653
654 if (!mlx5_core_is_pf(dev))
655 return 0;
656
657 memset(&he_in, 0, sizeof(he_in));
658 he_in.he = MLX5_SET_HOST_ENDIANNESS;
659 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
660 &he_out, sizeof(he_out),
661 MLX5_REG_HOST_ENDIANNESS, 0, 1);
662 return err;
663 }
664
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)665 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
666 {
667 int ret = 0;
668
669 /* Disable local_lb by default */
670 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
671 ret = mlx5_nic_vport_update_local_lb(dev, false);
672
673 return ret;
674 }
675
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)676 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
677 {
678 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
679
680 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
681 MLX5_SET(enable_hca_in, in, function_id, func_id);
682 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
683 dev->caps.embedded_cpu);
684 return mlx5_cmd_exec_in(dev, enable_hca, in);
685 }
686
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)687 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
688 {
689 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
690
691 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
692 MLX5_SET(disable_hca_in, in, function_id, func_id);
693 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
694 dev->caps.embedded_cpu);
695 return mlx5_cmd_exec_in(dev, disable_hca, in);
696 }
697
mlx5_core_set_issi(struct mlx5_core_dev * dev)698 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
699 {
700 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
701 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
702 u32 sup_issi;
703 int err;
704
705 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
706 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
707 if (err) {
708 u32 syndrome;
709 u8 status;
710
711 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
712 if (!status || syndrome == MLX5_DRIVER_SYND) {
713 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
714 err, status, syndrome);
715 return err;
716 }
717
718 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
719 dev->issi = 0;
720 return 0;
721 }
722
723 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
724
725 if (sup_issi & (1 << 1)) {
726 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
727
728 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
729 MLX5_SET(set_issi_in, set_in, current_issi, 1);
730 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
731 if (err) {
732 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
733 err);
734 return err;
735 }
736
737 dev->issi = 1;
738
739 return 0;
740 } else if (sup_issi & (1 << 0) || !sup_issi) {
741 return 0;
742 }
743
744 return -EOPNOTSUPP;
745 }
746
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)747 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
748 const struct pci_device_id *id)
749 {
750 struct mlx5_priv *priv = &dev->priv;
751 int err = 0;
752
753 mutex_init(&dev->pci_status_mutex);
754 pci_set_drvdata(dev->pdev, dev);
755
756 dev->bar_addr = pci_resource_start(pdev, 0);
757 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
758
759 err = mlx5_pci_enable_device(dev);
760 if (err) {
761 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
762 return err;
763 }
764
765 err = request_bar(pdev);
766 if (err) {
767 mlx5_core_err(dev, "error requesting BARs, aborting\n");
768 goto err_disable;
769 }
770
771 pci_set_master(pdev);
772
773 err = set_dma_caps(pdev);
774 if (err) {
775 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
776 goto err_clr_master;
777 }
778
779 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
780 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
781 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
782 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
783
784 dev->iseg_base = dev->bar_addr;
785 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
786 if (!dev->iseg) {
787 err = -ENOMEM;
788 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
789 goto err_clr_master;
790 }
791
792 mlx5_pci_vsc_init(dev);
793 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
794 return 0;
795
796 err_clr_master:
797 pci_clear_master(dev->pdev);
798 release_bar(dev->pdev);
799 err_disable:
800 mlx5_pci_disable_device(dev);
801 return err;
802 }
803
mlx5_pci_close(struct mlx5_core_dev * dev)804 static void mlx5_pci_close(struct mlx5_core_dev *dev)
805 {
806 /* health work might still be active, and it needs pci bar in
807 * order to know the NIC state. Therefore, drain the health WQ
808 * before removing the pci bars
809 */
810 mlx5_drain_health_wq(dev);
811 iounmap(dev->iseg);
812 pci_clear_master(dev->pdev);
813 release_bar(dev->pdev);
814 mlx5_pci_disable_device(dev);
815 }
816
mlx5_init_once(struct mlx5_core_dev * dev)817 static int mlx5_init_once(struct mlx5_core_dev *dev)
818 {
819 int err;
820
821 dev->priv.devcom = mlx5_devcom_register_device(dev);
822 if (IS_ERR(dev->priv.devcom))
823 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
824 dev->priv.devcom);
825
826 err = mlx5_query_board_id(dev);
827 if (err) {
828 mlx5_core_err(dev, "query board id failed\n");
829 goto err_devcom;
830 }
831
832 err = mlx5_irq_table_init(dev);
833 if (err) {
834 mlx5_core_err(dev, "failed to initialize irq table\n");
835 goto err_devcom;
836 }
837
838 err = mlx5_eq_table_init(dev);
839 if (err) {
840 mlx5_core_err(dev, "failed to initialize eq\n");
841 goto err_irq_cleanup;
842 }
843
844 err = mlx5_events_init(dev);
845 if (err) {
846 mlx5_core_err(dev, "failed to initialize events\n");
847 goto err_eq_cleanup;
848 }
849
850 err = mlx5_fw_reset_init(dev);
851 if (err) {
852 mlx5_core_err(dev, "failed to initialize fw reset events\n");
853 goto err_events_cleanup;
854 }
855
856 mlx5_cq_debugfs_init(dev);
857
858 mlx5_init_reserved_gids(dev);
859
860 mlx5_init_clock(dev);
861
862 dev->vxlan = mlx5_vxlan_create(dev);
863 dev->geneve = mlx5_geneve_create(dev);
864
865 err = mlx5_init_rl_table(dev);
866 if (err) {
867 mlx5_core_err(dev, "Failed to init rate limiting\n");
868 goto err_tables_cleanup;
869 }
870
871 err = mlx5_mpfs_init(dev);
872 if (err) {
873 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
874 goto err_rl_cleanup;
875 }
876
877 err = mlx5_sriov_init(dev);
878 if (err) {
879 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
880 goto err_mpfs_cleanup;
881 }
882
883 err = mlx5_eswitch_init(dev);
884 if (err) {
885 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
886 goto err_sriov_cleanup;
887 }
888
889 err = mlx5_fpga_init(dev);
890 if (err) {
891 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
892 goto err_eswitch_cleanup;
893 }
894
895 err = mlx5_vhca_event_init(dev);
896 if (err) {
897 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
898 goto err_fpga_cleanup;
899 }
900
901 err = mlx5_sf_hw_table_init(dev);
902 if (err) {
903 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
904 goto err_sf_hw_table_cleanup;
905 }
906
907 err = mlx5_sf_table_init(dev);
908 if (err) {
909 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
910 goto err_sf_table_cleanup;
911 }
912
913 dev->dm = mlx5_dm_create(dev);
914 if (IS_ERR(dev->dm))
915 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
916
917 dev->tracer = mlx5_fw_tracer_create(dev);
918 dev->hv_vhca = mlx5_hv_vhca_create(dev);
919 dev->rsc_dump = mlx5_rsc_dump_create(dev);
920
921 return 0;
922
923 err_sf_table_cleanup:
924 mlx5_sf_hw_table_cleanup(dev);
925 err_sf_hw_table_cleanup:
926 mlx5_vhca_event_cleanup(dev);
927 err_fpga_cleanup:
928 mlx5_fpga_cleanup(dev);
929 err_eswitch_cleanup:
930 mlx5_eswitch_cleanup(dev->priv.eswitch);
931 err_sriov_cleanup:
932 mlx5_sriov_cleanup(dev);
933 err_mpfs_cleanup:
934 mlx5_mpfs_cleanup(dev);
935 err_rl_cleanup:
936 mlx5_cleanup_rl_table(dev);
937 err_tables_cleanup:
938 mlx5_geneve_destroy(dev->geneve);
939 mlx5_vxlan_destroy(dev->vxlan);
940 mlx5_cq_debugfs_cleanup(dev);
941 mlx5_fw_reset_cleanup(dev);
942 err_events_cleanup:
943 mlx5_events_cleanup(dev);
944 err_eq_cleanup:
945 mlx5_eq_table_cleanup(dev);
946 err_irq_cleanup:
947 mlx5_irq_table_cleanup(dev);
948 err_devcom:
949 mlx5_devcom_unregister_device(dev->priv.devcom);
950
951 return err;
952 }
953
mlx5_cleanup_once(struct mlx5_core_dev * dev)954 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
955 {
956 mlx5_rsc_dump_destroy(dev);
957 mlx5_hv_vhca_destroy(dev->hv_vhca);
958 mlx5_fw_tracer_destroy(dev->tracer);
959 mlx5_dm_cleanup(dev);
960 mlx5_sf_table_cleanup(dev);
961 mlx5_sf_hw_table_cleanup(dev);
962 mlx5_vhca_event_cleanup(dev);
963 mlx5_fpga_cleanup(dev);
964 mlx5_eswitch_cleanup(dev->priv.eswitch);
965 mlx5_sriov_cleanup(dev);
966 mlx5_mpfs_cleanup(dev);
967 mlx5_cleanup_rl_table(dev);
968 mlx5_geneve_destroy(dev->geneve);
969 mlx5_vxlan_destroy(dev->vxlan);
970 mlx5_cleanup_clock(dev);
971 mlx5_cleanup_reserved_gids(dev);
972 mlx5_cq_debugfs_cleanup(dev);
973 mlx5_fw_reset_cleanup(dev);
974 mlx5_events_cleanup(dev);
975 mlx5_eq_table_cleanup(dev);
976 mlx5_irq_table_cleanup(dev);
977 mlx5_devcom_unregister_device(dev->priv.devcom);
978 }
979
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)980 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
981 {
982 int err;
983
984 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
985 fw_rev_min(dev), fw_rev_sub(dev));
986
987 /* Only PFs hold the relevant PCIe information for this query */
988 if (mlx5_core_is_pf(dev))
989 pcie_print_link_status(dev->pdev);
990
991 /* wait for firmware to accept initialization segments configurations
992 */
993 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
994 if (err) {
995 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
996 FW_PRE_INIT_TIMEOUT_MILI);
997 return err;
998 }
999
1000 err = mlx5_cmd_init(dev);
1001 if (err) {
1002 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1003 return err;
1004 }
1005
1006 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1007 if (err) {
1008 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
1009 FW_INIT_TIMEOUT_MILI);
1010 goto err_cmd_cleanup;
1011 }
1012
1013 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1014
1015 err = mlx5_core_enable_hca(dev, 0);
1016 if (err) {
1017 mlx5_core_err(dev, "enable hca failed\n");
1018 goto err_cmd_cleanup;
1019 }
1020
1021 err = mlx5_core_set_issi(dev);
1022 if (err) {
1023 mlx5_core_err(dev, "failed to set issi\n");
1024 goto err_disable_hca;
1025 }
1026
1027 err = mlx5_satisfy_startup_pages(dev, 1);
1028 if (err) {
1029 mlx5_core_err(dev, "failed to allocate boot pages\n");
1030 goto err_disable_hca;
1031 }
1032
1033 err = set_hca_ctrl(dev);
1034 if (err) {
1035 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1036 goto reclaim_boot_pages;
1037 }
1038
1039 err = set_hca_cap(dev);
1040 if (err) {
1041 mlx5_core_err(dev, "set_hca_cap failed\n");
1042 goto reclaim_boot_pages;
1043 }
1044
1045 err = mlx5_satisfy_startup_pages(dev, 0);
1046 if (err) {
1047 mlx5_core_err(dev, "failed to allocate init pages\n");
1048 goto reclaim_boot_pages;
1049 }
1050
1051 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1052 if (err) {
1053 mlx5_core_err(dev, "init hca failed\n");
1054 goto reclaim_boot_pages;
1055 }
1056
1057 mlx5_set_driver_version(dev);
1058
1059 mlx5_start_health_poll(dev);
1060
1061 err = mlx5_query_hca_caps(dev);
1062 if (err) {
1063 mlx5_core_err(dev, "query hca failed\n");
1064 goto stop_health;
1065 }
1066
1067 return 0;
1068
1069 stop_health:
1070 mlx5_stop_health_poll(dev, boot);
1071 reclaim_boot_pages:
1072 mlx5_reclaim_startup_pages(dev);
1073 err_disable_hca:
1074 mlx5_core_disable_hca(dev, 0);
1075 err_cmd_cleanup:
1076 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1077 mlx5_cmd_cleanup(dev);
1078
1079 return err;
1080 }
1081
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1082 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1083 {
1084 int err;
1085
1086 mlx5_stop_health_poll(dev, boot);
1087 err = mlx5_cmd_teardown_hca(dev);
1088 if (err) {
1089 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1090 return err;
1091 }
1092 mlx5_reclaim_startup_pages(dev);
1093 mlx5_core_disable_hca(dev, 0);
1094 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1095 mlx5_cmd_cleanup(dev);
1096
1097 return 0;
1098 }
1099
mlx5_load(struct mlx5_core_dev * dev)1100 static int mlx5_load(struct mlx5_core_dev *dev)
1101 {
1102 int err;
1103
1104 dev->priv.uar = mlx5_get_uars_page(dev);
1105 if (IS_ERR(dev->priv.uar)) {
1106 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1107 err = PTR_ERR(dev->priv.uar);
1108 return err;
1109 }
1110
1111 mlx5_events_start(dev);
1112 mlx5_pagealloc_start(dev);
1113
1114 err = mlx5_irq_table_create(dev);
1115 if (err) {
1116 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1117 goto err_irq_table;
1118 }
1119
1120 err = mlx5_eq_table_create(dev);
1121 if (err) {
1122 mlx5_core_err(dev, "Failed to create EQs\n");
1123 goto err_eq_table;
1124 }
1125
1126 err = mlx5_fw_tracer_init(dev->tracer);
1127 if (err) {
1128 mlx5_core_err(dev, "Failed to init FW tracer\n");
1129 goto err_fw_tracer;
1130 }
1131
1132 mlx5_fw_reset_events_start(dev);
1133 mlx5_hv_vhca_init(dev->hv_vhca);
1134
1135 err = mlx5_rsc_dump_init(dev);
1136 if (err) {
1137 mlx5_core_err(dev, "Failed to init Resource dump\n");
1138 goto err_rsc_dump;
1139 }
1140
1141 err = mlx5_fpga_device_start(dev);
1142 if (err) {
1143 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1144 goto err_fpga_start;
1145 }
1146
1147 mlx5_accel_ipsec_init(dev);
1148
1149 err = mlx5_accel_tls_init(dev);
1150 if (err) {
1151 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1152 goto err_tls_start;
1153 }
1154
1155 err = mlx5_init_fs(dev);
1156 if (err) {
1157 mlx5_core_err(dev, "Failed to init flow steering\n");
1158 goto err_fs;
1159 }
1160
1161 err = mlx5_core_set_hca_defaults(dev);
1162 if (err) {
1163 mlx5_core_err(dev, "Failed to set hca defaults\n");
1164 goto err_sriov;
1165 }
1166
1167 mlx5_vhca_event_start(dev);
1168
1169 err = mlx5_sf_hw_table_create(dev);
1170 if (err) {
1171 mlx5_core_err(dev, "sf table create failed %d\n", err);
1172 goto err_vhca;
1173 }
1174
1175 err = mlx5_ec_init(dev);
1176 if (err) {
1177 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1178 goto err_ec;
1179 }
1180
1181 err = mlx5_sriov_attach(dev);
1182 if (err) {
1183 mlx5_core_err(dev, "sriov init failed %d\n", err);
1184 goto err_sriov;
1185 }
1186
1187 mlx5_sf_dev_table_create(dev);
1188
1189 return 0;
1190
1191 err_sriov:
1192 mlx5_ec_cleanup(dev);
1193 err_ec:
1194 mlx5_sf_hw_table_destroy(dev);
1195 err_vhca:
1196 mlx5_vhca_event_stop(dev);
1197 mlx5_cleanup_fs(dev);
1198 err_fs:
1199 mlx5_accel_tls_cleanup(dev);
1200 err_tls_start:
1201 mlx5_accel_ipsec_cleanup(dev);
1202 mlx5_fpga_device_stop(dev);
1203 err_fpga_start:
1204 mlx5_rsc_dump_cleanup(dev);
1205 err_rsc_dump:
1206 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1207 mlx5_fw_reset_events_stop(dev);
1208 mlx5_fw_tracer_cleanup(dev->tracer);
1209 err_fw_tracer:
1210 mlx5_eq_table_destroy(dev);
1211 err_eq_table:
1212 mlx5_irq_table_destroy(dev);
1213 err_irq_table:
1214 mlx5_pagealloc_stop(dev);
1215 mlx5_events_stop(dev);
1216 mlx5_put_uars_page(dev, dev->priv.uar);
1217 return err;
1218 }
1219
mlx5_unload(struct mlx5_core_dev * dev)1220 static void mlx5_unload(struct mlx5_core_dev *dev)
1221 {
1222 mlx5_sf_dev_table_destroy(dev);
1223 mlx5_sriov_detach(dev);
1224 mlx5_ec_cleanup(dev);
1225 mlx5_sf_hw_table_destroy(dev);
1226 mlx5_vhca_event_stop(dev);
1227 mlx5_cleanup_fs(dev);
1228 mlx5_accel_ipsec_cleanup(dev);
1229 mlx5_accel_tls_cleanup(dev);
1230 mlx5_fpga_device_stop(dev);
1231 mlx5_rsc_dump_cleanup(dev);
1232 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1233 mlx5_fw_reset_events_stop(dev);
1234 mlx5_fw_tracer_cleanup(dev->tracer);
1235 mlx5_eq_table_destroy(dev);
1236 mlx5_irq_table_destroy(dev);
1237 mlx5_pagealloc_stop(dev);
1238 mlx5_events_stop(dev);
1239 mlx5_put_uars_page(dev, dev->priv.uar);
1240 }
1241
mlx5_init_one(struct mlx5_core_dev * dev)1242 int mlx5_init_one(struct mlx5_core_dev *dev)
1243 {
1244 int err = 0;
1245
1246 mutex_lock(&dev->intf_state_mutex);
1247 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1248 mlx5_core_warn(dev, "interface is up, NOP\n");
1249 goto out;
1250 }
1251 /* remove any previous indication of internal error */
1252 dev->state = MLX5_DEVICE_STATE_UP;
1253
1254 err = mlx5_function_setup(dev, true);
1255 if (err)
1256 goto err_function;
1257
1258 err = mlx5_init_once(dev);
1259 if (err) {
1260 mlx5_core_err(dev, "sw objs init failed\n");
1261 goto function_teardown;
1262 }
1263
1264 err = mlx5_load(dev);
1265 if (err)
1266 goto err_load;
1267
1268 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1269
1270 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1271 if (err)
1272 goto err_devlink_reg;
1273
1274 err = mlx5_register_device(dev);
1275 if (err)
1276 goto err_register;
1277
1278 mutex_unlock(&dev->intf_state_mutex);
1279 return 0;
1280
1281 err_register:
1282 mlx5_devlink_unregister(priv_to_devlink(dev));
1283 err_devlink_reg:
1284 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1285 mlx5_unload(dev);
1286 err_load:
1287 mlx5_cleanup_once(dev);
1288 function_teardown:
1289 mlx5_function_teardown(dev, true);
1290 err_function:
1291 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1292 out:
1293 mutex_unlock(&dev->intf_state_mutex);
1294 return err;
1295 }
1296
mlx5_uninit_one(struct mlx5_core_dev * dev)1297 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1298 {
1299 mutex_lock(&dev->intf_state_mutex);
1300
1301 mlx5_unregister_device(dev);
1302 mlx5_devlink_unregister(priv_to_devlink(dev));
1303
1304 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1305 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1306 __func__);
1307 mlx5_cleanup_once(dev);
1308 goto out;
1309 }
1310
1311 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1312 mlx5_unload(dev);
1313 mlx5_cleanup_once(dev);
1314 mlx5_function_teardown(dev, true);
1315 out:
1316 mutex_unlock(&dev->intf_state_mutex);
1317 }
1318
mlx5_load_one(struct mlx5_core_dev * dev)1319 int mlx5_load_one(struct mlx5_core_dev *dev)
1320 {
1321 int err = 0;
1322
1323 mutex_lock(&dev->intf_state_mutex);
1324 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1325 mlx5_core_warn(dev, "interface is up, NOP\n");
1326 goto out;
1327 }
1328 /* remove any previous indication of internal error */
1329 dev->state = MLX5_DEVICE_STATE_UP;
1330
1331 err = mlx5_function_setup(dev, false);
1332 if (err)
1333 goto err_function;
1334
1335 err = mlx5_load(dev);
1336 if (err)
1337 goto err_load;
1338
1339 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1340
1341 err = mlx5_attach_device(dev);
1342 if (err)
1343 goto err_attach;
1344
1345 mutex_unlock(&dev->intf_state_mutex);
1346 return 0;
1347
1348 err_attach:
1349 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1350 mlx5_unload(dev);
1351 err_load:
1352 mlx5_function_teardown(dev, false);
1353 err_function:
1354 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1355 out:
1356 mutex_unlock(&dev->intf_state_mutex);
1357 return err;
1358 }
1359
mlx5_unload_one(struct mlx5_core_dev * dev)1360 void mlx5_unload_one(struct mlx5_core_dev *dev)
1361 {
1362 mutex_lock(&dev->intf_state_mutex);
1363
1364 mlx5_detach_device(dev);
1365
1366 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1367 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1368 __func__);
1369 goto out;
1370 }
1371
1372 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1373 mlx5_unload(dev);
1374 mlx5_function_teardown(dev, false);
1375 out:
1376 mutex_unlock(&dev->intf_state_mutex);
1377 }
1378
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1379 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1380 {
1381 struct mlx5_priv *priv = &dev->priv;
1382 int err;
1383
1384 dev->profile = &profile[profile_idx];
1385
1386 INIT_LIST_HEAD(&priv->ctx_list);
1387 spin_lock_init(&priv->ctx_lock);
1388 mutex_init(&dev->intf_state_mutex);
1389
1390 mutex_init(&priv->bfregs.reg_head.lock);
1391 mutex_init(&priv->bfregs.wc_head.lock);
1392 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1393 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1394
1395 mutex_init(&priv->alloc_mutex);
1396 mutex_init(&priv->pgdir_mutex);
1397 INIT_LIST_HEAD(&priv->pgdir_list);
1398
1399 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1400 mlx5_debugfs_root);
1401 INIT_LIST_HEAD(&priv->traps);
1402
1403 err = mlx5_health_init(dev);
1404 if (err)
1405 goto err_health_init;
1406
1407 err = mlx5_pagealloc_init(dev);
1408 if (err)
1409 goto err_pagealloc_init;
1410
1411 err = mlx5_adev_init(dev);
1412 if (err)
1413 goto err_adev_init;
1414
1415 return 0;
1416
1417 err_adev_init:
1418 mlx5_pagealloc_cleanup(dev);
1419 err_pagealloc_init:
1420 mlx5_health_cleanup(dev);
1421 err_health_init:
1422 debugfs_remove(dev->priv.dbg_root);
1423 mutex_destroy(&priv->pgdir_mutex);
1424 mutex_destroy(&priv->alloc_mutex);
1425 mutex_destroy(&priv->bfregs.wc_head.lock);
1426 mutex_destroy(&priv->bfregs.reg_head.lock);
1427 mutex_destroy(&dev->intf_state_mutex);
1428 return err;
1429 }
1430
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1431 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1432 {
1433 struct mlx5_priv *priv = &dev->priv;
1434
1435 mlx5_adev_cleanup(dev);
1436 mlx5_pagealloc_cleanup(dev);
1437 mlx5_health_cleanup(dev);
1438 debugfs_remove_recursive(dev->priv.dbg_root);
1439 mutex_destroy(&priv->pgdir_mutex);
1440 mutex_destroy(&priv->alloc_mutex);
1441 mutex_destroy(&priv->bfregs.wc_head.lock);
1442 mutex_destroy(&priv->bfregs.reg_head.lock);
1443 mutex_destroy(&dev->intf_state_mutex);
1444 }
1445
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1446 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1447 {
1448 struct mlx5_core_dev *dev;
1449 struct devlink *devlink;
1450 int err;
1451
1452 devlink = mlx5_devlink_alloc();
1453 if (!devlink) {
1454 dev_err(&pdev->dev, "devlink alloc failed\n");
1455 return -ENOMEM;
1456 }
1457
1458 dev = devlink_priv(devlink);
1459 dev->device = &pdev->dev;
1460 dev->pdev = pdev;
1461
1462 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1463 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1464
1465 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1466 if (dev->priv.adev_idx < 0) {
1467 err = dev->priv.adev_idx;
1468 goto adev_init_err;
1469 }
1470
1471 err = mlx5_mdev_init(dev, prof_sel);
1472 if (err)
1473 goto mdev_init_err;
1474
1475 err = mlx5_pci_init(dev, pdev, id);
1476 if (err) {
1477 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1478 err);
1479 goto pci_init_err;
1480 }
1481
1482 err = mlx5_init_one(dev);
1483 if (err) {
1484 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1485 err);
1486 goto err_init_one;
1487 }
1488
1489 err = mlx5_crdump_enable(dev);
1490 if (err)
1491 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1492
1493 pci_save_state(pdev);
1494 if (!mlx5_core_is_mp_slave(dev))
1495 devlink_reload_enable(devlink);
1496 return 0;
1497
1498 err_init_one:
1499 mlx5_pci_close(dev);
1500 pci_init_err:
1501 mlx5_mdev_uninit(dev);
1502 mdev_init_err:
1503 mlx5_adev_idx_free(dev->priv.adev_idx);
1504 adev_init_err:
1505 mlx5_devlink_free(devlink);
1506
1507 return err;
1508 }
1509
remove_one(struct pci_dev * pdev)1510 static void remove_one(struct pci_dev *pdev)
1511 {
1512 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1513 struct devlink *devlink = priv_to_devlink(dev);
1514
1515 devlink_reload_disable(devlink);
1516 mlx5_crdump_disable(dev);
1517 mlx5_drain_health_wq(dev);
1518 mlx5_uninit_one(dev);
1519 mlx5_pci_close(dev);
1520 mlx5_mdev_uninit(dev);
1521 mlx5_adev_idx_free(dev->priv.adev_idx);
1522 mlx5_devlink_free(devlink);
1523 }
1524
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1525 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1526 pci_channel_state_t state)
1527 {
1528 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1529
1530 mlx5_core_info(dev, "%s was called\n", __func__);
1531
1532 mlx5_enter_error_state(dev, false);
1533 mlx5_error_sw_reset(dev);
1534 mlx5_unload_one(dev);
1535 mlx5_drain_health_wq(dev);
1536 mlx5_pci_disable_device(dev);
1537
1538 return state == pci_channel_io_perm_failure ?
1539 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1540 }
1541
1542 /* wait for the device to show vital signs by waiting
1543 * for the health counter to start counting.
1544 */
wait_vital(struct pci_dev * pdev)1545 static int wait_vital(struct pci_dev *pdev)
1546 {
1547 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1548 struct mlx5_core_health *health = &dev->priv.health;
1549 const int niter = 100;
1550 u32 last_count = 0;
1551 u32 count;
1552 int i;
1553
1554 for (i = 0; i < niter; i++) {
1555 count = ioread32be(health->health_counter);
1556 if (count && count != 0xffffffff) {
1557 if (last_count && last_count != count) {
1558 mlx5_core_info(dev,
1559 "wait vital counter value 0x%x after %d iterations\n",
1560 count, i);
1561 return 0;
1562 }
1563 last_count = count;
1564 }
1565 msleep(50);
1566 }
1567
1568 return -ETIMEDOUT;
1569 }
1570
mlx5_pci_slot_reset(struct pci_dev * pdev)1571 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1572 {
1573 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1574 int err;
1575
1576 mlx5_core_info(dev, "%s was called\n", __func__);
1577
1578 err = mlx5_pci_enable_device(dev);
1579 if (err) {
1580 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1581 __func__, err);
1582 return PCI_ERS_RESULT_DISCONNECT;
1583 }
1584
1585 pci_set_master(pdev);
1586 pci_restore_state(pdev);
1587 pci_save_state(pdev);
1588
1589 if (wait_vital(pdev)) {
1590 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1591 return PCI_ERS_RESULT_DISCONNECT;
1592 }
1593
1594 return PCI_ERS_RESULT_RECOVERED;
1595 }
1596
mlx5_pci_resume(struct pci_dev * pdev)1597 static void mlx5_pci_resume(struct pci_dev *pdev)
1598 {
1599 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1600 int err;
1601
1602 mlx5_core_info(dev, "%s was called\n", __func__);
1603
1604 err = mlx5_load_one(dev);
1605 if (err)
1606 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1607 __func__, err);
1608 else
1609 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1610 }
1611
1612 static const struct pci_error_handlers mlx5_err_handler = {
1613 .error_detected = mlx5_pci_err_detected,
1614 .slot_reset = mlx5_pci_slot_reset,
1615 .resume = mlx5_pci_resume
1616 };
1617
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1618 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1619 {
1620 bool fast_teardown = false, force_teardown = false;
1621 int ret = 1;
1622
1623 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1624 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1625
1626 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1627 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1628
1629 if (!fast_teardown && !force_teardown)
1630 return -EOPNOTSUPP;
1631
1632 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1633 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1634 return -EAGAIN;
1635 }
1636
1637 /* Panic tear down fw command will stop the PCI bus communication
1638 * with the HCA, so the health polll is no longer needed.
1639 */
1640 mlx5_drain_health_wq(dev);
1641 mlx5_stop_health_poll(dev, false);
1642
1643 ret = mlx5_cmd_fast_teardown_hca(dev);
1644 if (!ret)
1645 goto succeed;
1646
1647 ret = mlx5_cmd_force_teardown_hca(dev);
1648 if (!ret)
1649 goto succeed;
1650
1651 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1652 mlx5_start_health_poll(dev);
1653 return ret;
1654
1655 succeed:
1656 mlx5_enter_error_state(dev, true);
1657
1658 /* Some platforms requiring freeing the IRQ's in the shutdown
1659 * flow. If they aren't freed they can't be allocated after
1660 * kexec. There is no need to cleanup the mlx5_core software
1661 * contexts.
1662 */
1663 mlx5_core_eq_free_irqs(dev);
1664
1665 return 0;
1666 }
1667
shutdown(struct pci_dev * pdev)1668 static void shutdown(struct pci_dev *pdev)
1669 {
1670 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1671 int err;
1672
1673 mlx5_core_info(dev, "Shutdown was called\n");
1674 err = mlx5_try_fast_unload(dev);
1675 if (err)
1676 mlx5_unload_one(dev);
1677 mlx5_pci_disable_device(dev);
1678 }
1679
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1680 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1681 {
1682 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1683
1684 mlx5_unload_one(dev);
1685
1686 return 0;
1687 }
1688
mlx5_resume(struct pci_dev * pdev)1689 static int mlx5_resume(struct pci_dev *pdev)
1690 {
1691 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1692
1693 return mlx5_load_one(dev);
1694 }
1695
1696 static const struct pci_device_id mlx5_core_pci_table[] = {
1697 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1698 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1699 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1700 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1701 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1702 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1703 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1704 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1705 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1706 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1707 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1708 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1709 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1710 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1711 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1712 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1713 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1714 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1715 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1716 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1717 { 0, }
1718 };
1719
1720 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1721
mlx5_disable_device(struct mlx5_core_dev * dev)1722 void mlx5_disable_device(struct mlx5_core_dev *dev)
1723 {
1724 mlx5_error_sw_reset(dev);
1725 mlx5_unload_one(dev);
1726 }
1727
mlx5_recover_device(struct mlx5_core_dev * dev)1728 int mlx5_recover_device(struct mlx5_core_dev *dev)
1729 {
1730 int ret = -EIO;
1731
1732 mlx5_pci_disable_device(dev);
1733 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1734 ret = mlx5_load_one(dev);
1735 return ret;
1736 }
1737
1738 static struct pci_driver mlx5_core_driver = {
1739 .name = KBUILD_MODNAME,
1740 .id_table = mlx5_core_pci_table,
1741 .probe = probe_one,
1742 .remove = remove_one,
1743 .suspend = mlx5_suspend,
1744 .resume = mlx5_resume,
1745 .shutdown = shutdown,
1746 .err_handler = &mlx5_err_handler,
1747 .sriov_configure = mlx5_core_sriov_configure,
1748 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1749 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1750 };
1751
mlx5_core_verify_params(void)1752 static void mlx5_core_verify_params(void)
1753 {
1754 if (prof_sel >= ARRAY_SIZE(profile)) {
1755 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1756 prof_sel,
1757 ARRAY_SIZE(profile) - 1,
1758 MLX5_DEFAULT_PROF);
1759 prof_sel = MLX5_DEFAULT_PROF;
1760 }
1761 }
1762
init(void)1763 static int __init init(void)
1764 {
1765 int err;
1766
1767 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1768 "mlx5_core name not in sync with kernel module name");
1769
1770 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1771
1772 mlx5_core_verify_params();
1773 mlx5_fpga_ipsec_build_fs_cmds();
1774 mlx5_register_debugfs();
1775
1776 err = pci_register_driver(&mlx5_core_driver);
1777 if (err)
1778 goto err_debug;
1779
1780 err = mlx5_sf_driver_register();
1781 if (err)
1782 goto err_sf;
1783
1784 #ifdef CONFIG_MLX5_CORE_EN
1785 err = mlx5e_init();
1786 if (err) {
1787 pci_unregister_driver(&mlx5_core_driver);
1788 goto err_debug;
1789 }
1790 #endif
1791
1792 return 0;
1793
1794 err_sf:
1795 pci_unregister_driver(&mlx5_core_driver);
1796 err_debug:
1797 mlx5_unregister_debugfs();
1798 return err;
1799 }
1800
cleanup(void)1801 static void __exit cleanup(void)
1802 {
1803 #ifdef CONFIG_MLX5_CORE_EN
1804 mlx5e_cleanup();
1805 #endif
1806 mlx5_sf_driver_unregister();
1807 pci_unregister_driver(&mlx5_core_driver);
1808 mlx5_unregister_debugfs();
1809 }
1810
1811 module_init(init);
1812 module_exit(cleanup);
1813