1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/fs.h>
43 #include <linux/mlx5/driver.h>
44
45 extern uint mlx5_core_debug_mask;
46
47 #define mlx5_core_dbg(__dev, format, ...) \
48 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
49 __func__, __LINE__, current->pid, \
50 ##__VA_ARGS__)
51
52 #define mlx5_core_dbg_once(__dev, format, ...) \
53 dev_dbg_once((__dev)->device, \
54 "%s:%d:(pid %d): " format, \
55 __func__, __LINE__, current->pid, \
56 ##__VA_ARGS__)
57
58 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
59 do { \
60 if ((mask) & mlx5_core_debug_mask) \
61 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
62 } while (0)
63
64 #define mlx5_core_err(__dev, format, ...) \
65 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
66 __func__, __LINE__, current->pid, \
67 ##__VA_ARGS__)
68
69 #define mlx5_core_err_rl(__dev, format, ...) \
70 dev_err_ratelimited((__dev)->device, \
71 "%s:%d:(pid %d): " format, \
72 __func__, __LINE__, current->pid, \
73 ##__VA_ARGS__)
74
75 #define mlx5_core_warn(__dev, format, ...) \
76 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
77 __func__, __LINE__, current->pid, \
78 ##__VA_ARGS__)
79
80 #define mlx5_core_warn_once(__dev, format, ...) \
81 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
82 __func__, __LINE__, current->pid, \
83 ##__VA_ARGS__)
84
85 #define mlx5_core_warn_rl(__dev, format, ...) \
86 dev_warn_ratelimited((__dev)->device, \
87 "%s:%d:(pid %d): " format, \
88 __func__, __LINE__, current->pid, \
89 ##__VA_ARGS__)
90
91 #define mlx5_core_info(__dev, format, ...) \
92 dev_info((__dev)->device, format, ##__VA_ARGS__)
93
94 #define mlx5_core_info_rl(__dev, format, ...) \
95 dev_info_ratelimited((__dev)->device, \
96 "%s:%d:(pid %d): " format, \
97 __func__, __LINE__, current->pid, \
98 ##__VA_ARGS__)
99
mlx5_core_dma_dev(struct mlx5_core_dev * dev)100 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
101 {
102 return &dev->pdev->dev;
103 }
104
105 enum {
106 MLX5_CMD_DATA, /* print command payload only */
107 MLX5_CMD_TIME, /* print command execution time */
108 };
109
110 enum {
111 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
112 MLX5_DRIVER_SYND = 0xbadd00de,
113 };
114
115 enum mlx5_semaphore_space_address {
116 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
117 MLX5_SEMAPHORE_SW_RESET = 0x20,
118 };
119
120 #define MLX5_DEFAULT_PROF 2
121
122 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
123 int mlx5_query_board_id(struct mlx5_core_dev *dev);
124 int mlx5_cmd_init(struct mlx5_core_dev *dev);
125 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
126 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
127 enum mlx5_cmdif_state cmdif_state);
128 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
129 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
130 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
131 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
132 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
133 void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
134 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
135 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
136 void mlx5_disable_device(struct mlx5_core_dev *dev);
137 int mlx5_recover_device(struct mlx5_core_dev *dev);
138 int mlx5_sriov_init(struct mlx5_core_dev *dev);
139 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
140 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
141 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
142 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
143 int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);
144 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
145 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
146 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
147 void *context, u32 *element_id);
148 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
149 void *context, u32 element_id,
150 u32 modify_bitmask);
151 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
152 u32 element_id);
153 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
154
155 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
156 void mlx5_cmd_flush(struct mlx5_core_dev *dev);
157 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
158 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
159
160 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
161 u8 access_reg_group);
162 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
163 u8 access_reg_group);
164 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
165 u8 feature_group, u8 access_reg_group);
166
167 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
168 void mlx5_lag_remove(struct mlx5_core_dev *dev);
169
170 int mlx5_irq_table_init(struct mlx5_core_dev *dev);
171 void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);
172 int mlx5_irq_table_create(struct mlx5_core_dev *dev);
173 void mlx5_irq_table_destroy(struct mlx5_core_dev *dev);
174 int mlx5_irq_attach_nb(struct mlx5_irq_table *irq_table, int vecidx,
175 struct notifier_block *nb);
176 int mlx5_irq_detach_nb(struct mlx5_irq_table *irq_table, int vecidx,
177 struct notifier_block *nb);
178
179 int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, int devfn,
180 int msix_vec_count);
181 int mlx5_get_default_msix_vec_count(struct mlx5_core_dev *dev, int num_vfs);
182
183 struct cpumask *
184 mlx5_irq_get_affinity_mask(struct mlx5_irq_table *irq_table, int vecidx);
185 struct cpu_rmap *mlx5_irq_get_rmap(struct mlx5_irq_table *table);
186 int mlx5_irq_get_num_comp(struct mlx5_irq_table *table);
187 struct mlx5_irq_table *mlx5_irq_table_get(struct mlx5_core_dev *dev);
188
189 int mlx5_events_init(struct mlx5_core_dev *dev);
190 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
191 void mlx5_events_start(struct mlx5_core_dev *dev);
192 void mlx5_events_stop(struct mlx5_core_dev *dev);
193
194 int mlx5_adev_idx_alloc(void);
195 void mlx5_adev_idx_free(int idx);
196 void mlx5_adev_cleanup(struct mlx5_core_dev *dev);
197 int mlx5_adev_init(struct mlx5_core_dev *dev);
198
199 int mlx5_attach_device(struct mlx5_core_dev *dev);
200 void mlx5_detach_device(struct mlx5_core_dev *dev);
201 int mlx5_register_device(struct mlx5_core_dev *dev);
202 void mlx5_unregister_device(struct mlx5_core_dev *dev);
203 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
204 void mlx5_dev_list_lock(void);
205 void mlx5_dev_list_unlock(void);
206 int mlx5_dev_list_trylock(void);
207
208 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
209 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
210 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
211 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
212
213 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
214 void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
215
216 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
217 MLX5_CAP_GEN((mdev), pps_modify) && \
218 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
219 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
220
221 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
222 struct netlink_ext_ack *extack);
223 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
224 u32 *running_ver, u32 *stored_ver);
225
226 int mlx5e_init(void);
227 void mlx5e_cleanup(void);
228
mlx5_sriov_is_enabled(struct mlx5_core_dev * dev)229 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
230 {
231 return pci_num_vf(dev->pdev) ? true : false;
232 }
233
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)234 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
235 {
236 /* LACP owner conditions:
237 * 1) Function is physical.
238 * 2) LAG is supported by FW.
239 * 3) LAG is managed by driver (currently the only option).
240 */
241 return MLX5_CAP_GEN(dev, vport_group_manager) &&
242 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
243 MLX5_CAP_GEN(dev, lag_master);
244 }
245
246 int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev);
mlx5_rescan_drivers(struct mlx5_core_dev * dev)247 static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev)
248 {
249 int ret;
250
251 mlx5_dev_list_lock();
252 ret = mlx5_rescan_drivers_locked(dev);
253 mlx5_dev_list_unlock();
254 return ret;
255 }
256
257 void mlx5_lag_update(struct mlx5_core_dev *dev);
258
259 enum {
260 MLX5_NIC_IFC_FULL = 0,
261 MLX5_NIC_IFC_DISABLED = 1,
262 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
263 MLX5_NIC_IFC_SW_RESET = 7
264 };
265
266 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
267 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
268
mlx5_core_is_sf(const struct mlx5_core_dev * dev)269 static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev)
270 {
271 return dev->coredev_type == MLX5_COREDEV_SF;
272 }
273
274 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx);
275 void mlx5_mdev_uninit(struct mlx5_core_dev *dev);
276 int mlx5_init_one(struct mlx5_core_dev *dev);
277 void mlx5_uninit_one(struct mlx5_core_dev *dev);
278 void mlx5_unload_one(struct mlx5_core_dev *dev);
279 int mlx5_load_one(struct mlx5_core_dev *dev);
280
281 int mlx5_vport_get_other_func_cap(struct mlx5_core_dev *dev, u16 function_id, void *out);
282
283 void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work);
mlx5_sriov_get_vf_total_msix(struct pci_dev * pdev)284 static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev)
285 {
286 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
287
288 return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
289 }
290 #endif /* __MLX5_CORE_H__ */
291