1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020 Linaro Ltd.
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include "../core.h"
22 #include "../pinctrl-utils.h"
23
24 #define LPI_SLEW_RATE_CTL_REG 0xa000
25 #define LPI_TLMM_REG_OFFSET 0x1000
26 #define LPI_SLEW_RATE_MAX 0x03
27 #define LPI_SLEW_BITS_SIZE 0x02
28 #define LPI_SLEW_RATE_MASK GENMASK(1, 0)
29 #define LPI_GPIO_CFG_REG 0x00
30 #define LPI_GPIO_PULL_MASK GENMASK(1, 0)
31 #define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
32 #define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
33 #define LPI_GPIO_OE_MASK BIT(9)
34 #define LPI_GPIO_VALUE_REG 0x04
35 #define LPI_GPIO_VALUE_IN_MASK BIT(0)
36 #define LPI_GPIO_VALUE_OUT_MASK BIT(1)
37
38 #define LPI_GPIO_BIAS_DISABLE 0x0
39 #define LPI_GPIO_PULL_DOWN 0x1
40 #define LPI_GPIO_KEEPER 0x2
41 #define LPI_GPIO_PULL_UP 0x3
42 #define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
43 #define NO_SLEW -1
44
45 #define LPI_FUNCTION(fname) \
46 [LPI_MUX_##fname] = { \
47 .name = #fname, \
48 .groups = fname##_groups, \
49 .ngroups = ARRAY_SIZE(fname##_groups), \
50 }
51
52 #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
53 { \
54 .name = "gpio" #id, \
55 .pins = gpio##id##_pins, \
56 .pin = id, \
57 .slew_offset = soff, \
58 .npins = ARRAY_SIZE(gpio##id##_pins), \
59 .funcs = (int[]){ \
60 LPI_MUX_gpio, \
61 LPI_MUX_##f1, \
62 LPI_MUX_##f2, \
63 LPI_MUX_##f3, \
64 LPI_MUX_##f4, \
65 }, \
66 .nfuncs = 5, \
67 }
68
69 struct lpi_pingroup {
70 const char *name;
71 const unsigned int *pins;
72 unsigned int npins;
73 unsigned int pin;
74 /* Bit offset in slew register for SoundWire pins only */
75 int slew_offset;
76 unsigned int *funcs;
77 unsigned int nfuncs;
78 };
79
80 struct lpi_function {
81 const char *name;
82 const char * const *groups;
83 unsigned int ngroups;
84 };
85
86 struct lpi_pinctrl_variant_data {
87 const struct pinctrl_pin_desc *pins;
88 int npins;
89 const struct lpi_pingroup *groups;
90 int ngroups;
91 const struct lpi_function *functions;
92 int nfunctions;
93 };
94
95 #define MAX_LPI_NUM_CLKS 2
96
97 struct lpi_pinctrl {
98 struct device *dev;
99 struct pinctrl_dev *ctrl;
100 struct gpio_chip chip;
101 struct pinctrl_desc desc;
102 char __iomem *tlmm_base;
103 char __iomem *slew_base;
104 struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
105 struct mutex slew_access_lock;
106 const struct lpi_pinctrl_variant_data *data;
107 };
108
109 /* sm8250 variant specific data */
110 static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
111 PINCTRL_PIN(0, "gpio0"),
112 PINCTRL_PIN(1, "gpio1"),
113 PINCTRL_PIN(2, "gpio2"),
114 PINCTRL_PIN(3, "gpio3"),
115 PINCTRL_PIN(4, "gpio4"),
116 PINCTRL_PIN(5, "gpio5"),
117 PINCTRL_PIN(6, "gpio6"),
118 PINCTRL_PIN(7, "gpio7"),
119 PINCTRL_PIN(8, "gpio8"),
120 PINCTRL_PIN(9, "gpio9"),
121 PINCTRL_PIN(10, "gpio10"),
122 PINCTRL_PIN(11, "gpio11"),
123 PINCTRL_PIN(12, "gpio12"),
124 PINCTRL_PIN(13, "gpio13"),
125 };
126
127 enum sm8250_lpi_functions {
128 LPI_MUX_dmic1_clk,
129 LPI_MUX_dmic1_data,
130 LPI_MUX_dmic2_clk,
131 LPI_MUX_dmic2_data,
132 LPI_MUX_dmic3_clk,
133 LPI_MUX_dmic3_data,
134 LPI_MUX_i2s1_clk,
135 LPI_MUX_i2s1_data,
136 LPI_MUX_i2s1_ws,
137 LPI_MUX_i2s2_clk,
138 LPI_MUX_i2s2_data,
139 LPI_MUX_i2s2_ws,
140 LPI_MUX_qua_mi2s_data,
141 LPI_MUX_qua_mi2s_sclk,
142 LPI_MUX_qua_mi2s_ws,
143 LPI_MUX_swr_rx_clk,
144 LPI_MUX_swr_rx_data,
145 LPI_MUX_swr_tx_clk,
146 LPI_MUX_swr_tx_data,
147 LPI_MUX_wsa_swr_clk,
148 LPI_MUX_wsa_swr_data,
149 LPI_MUX_gpio,
150 LPI_MUX__,
151 };
152
153 static const unsigned int gpio0_pins[] = { 0 };
154 static const unsigned int gpio1_pins[] = { 1 };
155 static const unsigned int gpio2_pins[] = { 2 };
156 static const unsigned int gpio3_pins[] = { 3 };
157 static const unsigned int gpio4_pins[] = { 4 };
158 static const unsigned int gpio5_pins[] = { 5 };
159 static const unsigned int gpio6_pins[] = { 6 };
160 static const unsigned int gpio7_pins[] = { 7 };
161 static const unsigned int gpio8_pins[] = { 8 };
162 static const unsigned int gpio9_pins[] = { 9 };
163 static const unsigned int gpio10_pins[] = { 10 };
164 static const unsigned int gpio11_pins[] = { 11 };
165 static const unsigned int gpio12_pins[] = { 12 };
166 static const unsigned int gpio13_pins[] = { 13 };
167 static const char * const swr_tx_clk_groups[] = { "gpio0" };
168 static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
169 static const char * const swr_rx_clk_groups[] = { "gpio3" };
170 static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
171 static const char * const dmic1_clk_groups[] = { "gpio6" };
172 static const char * const dmic1_data_groups[] = { "gpio7" };
173 static const char * const dmic2_clk_groups[] = { "gpio8" };
174 static const char * const dmic2_data_groups[] = { "gpio9" };
175 static const char * const i2s2_clk_groups[] = { "gpio10" };
176 static const char * const i2s2_ws_groups[] = { "gpio11" };
177 static const char * const dmic3_clk_groups[] = { "gpio12" };
178 static const char * const dmic3_data_groups[] = { "gpio13" };
179 static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
180 static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
181 static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
182 static const char * const i2s1_clk_groups[] = { "gpio6" };
183 static const char * const i2s1_ws_groups[] = { "gpio7" };
184 static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
185 static const char * const wsa_swr_clk_groups[] = { "gpio10" };
186 static const char * const wsa_swr_data_groups[] = { "gpio11" };
187 static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
188
189 static const struct lpi_pingroup sm8250_groups[] = {
190 LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
191 LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
192 LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
193 LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
194 LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
195 LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
196 LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
197 LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
198 LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
199 LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
200 LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
201 LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
202 LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
203 LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
204 };
205
206 static const struct lpi_function sm8250_functions[] = {
207 LPI_FUNCTION(dmic1_clk),
208 LPI_FUNCTION(dmic1_data),
209 LPI_FUNCTION(dmic2_clk),
210 LPI_FUNCTION(dmic2_data),
211 LPI_FUNCTION(dmic3_clk),
212 LPI_FUNCTION(dmic3_data),
213 LPI_FUNCTION(i2s1_clk),
214 LPI_FUNCTION(i2s1_data),
215 LPI_FUNCTION(i2s1_ws),
216 LPI_FUNCTION(i2s2_clk),
217 LPI_FUNCTION(i2s2_data),
218 LPI_FUNCTION(i2s2_ws),
219 LPI_FUNCTION(qua_mi2s_data),
220 LPI_FUNCTION(qua_mi2s_sclk),
221 LPI_FUNCTION(qua_mi2s_ws),
222 LPI_FUNCTION(swr_rx_clk),
223 LPI_FUNCTION(swr_rx_data),
224 LPI_FUNCTION(swr_tx_clk),
225 LPI_FUNCTION(swr_tx_data),
226 LPI_FUNCTION(wsa_swr_clk),
227 LPI_FUNCTION(wsa_swr_data),
228 };
229
230 static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
231 .pins = sm8250_lpi_pins,
232 .npins = ARRAY_SIZE(sm8250_lpi_pins),
233 .groups = sm8250_groups,
234 .ngroups = ARRAY_SIZE(sm8250_groups),
235 .functions = sm8250_functions,
236 .nfunctions = ARRAY_SIZE(sm8250_functions),
237 };
238
lpi_gpio_read(struct lpi_pinctrl * state,unsigned int pin,unsigned int addr)239 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
240 unsigned int addr)
241 {
242 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
243 }
244
lpi_gpio_write(struct lpi_pinctrl * state,unsigned int pin,unsigned int addr,unsigned int val)245 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
246 unsigned int addr, unsigned int val)
247 {
248 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
249
250 return 0;
251 }
252
lpi_gpio_get_groups_count(struct pinctrl_dev * pctldev)253 static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev)
254 {
255 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
256
257 return pctrl->data->ngroups;
258 }
259
lpi_gpio_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)260 static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
261 unsigned int group)
262 {
263 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
264
265 return pctrl->data->groups[group].name;
266 }
267
lpi_gpio_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)268 static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
269 unsigned int group,
270 const unsigned int **pins,
271 unsigned int *num_pins)
272 {
273 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
274
275 *pins = pctrl->data->groups[group].pins;
276 *num_pins = pctrl->data->groups[group].npins;
277
278 return 0;
279 }
280
281 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
282 .get_groups_count = lpi_gpio_get_groups_count,
283 .get_group_name = lpi_gpio_get_group_name,
284 .get_group_pins = lpi_gpio_get_group_pins,
285 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
286 .dt_free_map = pinctrl_utils_free_map,
287 };
288
lpi_gpio_get_functions_count(struct pinctrl_dev * pctldev)289 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
290 {
291 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292
293 return pctrl->data->nfunctions;
294 }
295
lpi_gpio_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)296 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
297 unsigned int function)
298 {
299 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
300
301 return pctrl->data->functions[function].name;
302 }
303
lpi_gpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned * const num_qgroups)304 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
305 unsigned int function,
306 const char *const **groups,
307 unsigned *const num_qgroups)
308 {
309 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
310
311 *groups = pctrl->data->functions[function].groups;
312 *num_qgroups = pctrl->data->functions[function].ngroups;
313
314 return 0;
315 }
316
lpi_gpio_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group_num)317 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
318 unsigned int group_num)
319 {
320 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
321 const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
322 u32 val;
323 int i, pin = g->pin;
324
325 for (i = 0; i < g->nfuncs; i++) {
326 if (g->funcs[i] == function)
327 break;
328 }
329
330 if (WARN_ON(i == g->nfuncs))
331 return -EINVAL;
332
333 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
334 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
335 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
336
337 return 0;
338 }
339
340 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
341 .get_functions_count = lpi_gpio_get_functions_count,
342 .get_function_name = lpi_gpio_get_function_name,
343 .get_function_groups = lpi_gpio_get_function_groups,
344 .set_mux = lpi_gpio_set_mux,
345 };
346
lpi_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)347 static int lpi_config_get(struct pinctrl_dev *pctldev,
348 unsigned int pin, unsigned long *config)
349 {
350 unsigned int param = pinconf_to_config_param(*config);
351 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
352 unsigned int arg = 0;
353 int is_out;
354 int pull;
355 u32 ctl_reg;
356
357 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
358 is_out = ctl_reg & LPI_GPIO_OE_MASK;
359 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
360
361 switch (param) {
362 case PIN_CONFIG_BIAS_DISABLE:
363 if (pull == LPI_GPIO_BIAS_DISABLE)
364 arg = 1;
365 break;
366 case PIN_CONFIG_BIAS_PULL_DOWN:
367 if (pull == LPI_GPIO_PULL_DOWN)
368 arg = 1;
369 break;
370 case PIN_CONFIG_BIAS_BUS_HOLD:
371 if (pull == LPI_GPIO_KEEPER)
372 arg = 1;
373 break;
374 case PIN_CONFIG_BIAS_PULL_UP:
375 if (pull == LPI_GPIO_PULL_UP)
376 arg = 1;
377 break;
378 case PIN_CONFIG_INPUT_ENABLE:
379 case PIN_CONFIG_OUTPUT:
380 if (is_out)
381 arg = 1;
382 break;
383 default:
384 return -EINVAL;
385 }
386
387 *config = pinconf_to_config_packed(param, arg);
388 return 0;
389 }
390
lpi_config_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int nconfs)391 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
392 unsigned long *configs, unsigned int nconfs)
393 {
394 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
395 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
396 bool value, output_enabled = false;
397 const struct lpi_pingroup *g;
398 unsigned long sval;
399 int i, slew_offset;
400 u32 val;
401
402 g = &pctrl->data->groups[group];
403 for (i = 0; i < nconfs; i++) {
404 param = pinconf_to_config_param(configs[i]);
405 arg = pinconf_to_config_argument(configs[i]);
406
407 switch (param) {
408 case PIN_CONFIG_BIAS_DISABLE:
409 pullup = LPI_GPIO_BIAS_DISABLE;
410 break;
411 case PIN_CONFIG_BIAS_PULL_DOWN:
412 pullup = LPI_GPIO_PULL_DOWN;
413 break;
414 case PIN_CONFIG_BIAS_BUS_HOLD:
415 pullup = LPI_GPIO_KEEPER;
416 break;
417 case PIN_CONFIG_BIAS_PULL_UP:
418 pullup = LPI_GPIO_PULL_UP;
419 break;
420 case PIN_CONFIG_INPUT_ENABLE:
421 output_enabled = false;
422 break;
423 case PIN_CONFIG_OUTPUT:
424 output_enabled = true;
425 value = arg;
426 break;
427 case PIN_CONFIG_DRIVE_STRENGTH:
428 strength = arg;
429 break;
430 case PIN_CONFIG_SLEW_RATE:
431 if (arg > LPI_SLEW_RATE_MAX) {
432 dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
433 arg, group);
434 return -EINVAL;
435 }
436
437 slew_offset = g->slew_offset;
438 if (slew_offset == NO_SLEW)
439 break;
440
441 mutex_lock(&pctrl->slew_access_lock);
442
443 sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
444 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
445 sval |= arg << slew_offset;
446 iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
447
448 mutex_unlock(&pctrl->slew_access_lock);
449 break;
450 default:
451 return -EINVAL;
452 }
453 }
454
455 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
456
457 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
458 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
459 LPI_GPIO_OUT_STRENGTH_MASK);
460 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
461
462 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
463
464 if (output_enabled) {
465 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
466 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
467 }
468
469 return 0;
470 }
471
472 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
473 .is_generic = true,
474 .pin_config_group_get = lpi_config_get,
475 .pin_config_group_set = lpi_config_set,
476 };
477
lpi_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)478 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
479 {
480 struct lpi_pinctrl *state = gpiochip_get_data(chip);
481 unsigned long config;
482
483 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
484
485 return lpi_config_set(state->ctrl, pin, &config, 1);
486 }
487
lpi_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int val)488 static int lpi_gpio_direction_output(struct gpio_chip *chip,
489 unsigned int pin, int val)
490 {
491 struct lpi_pinctrl *state = gpiochip_get_data(chip);
492 unsigned long config;
493
494 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
495
496 return lpi_config_set(state->ctrl, pin, &config, 1);
497 }
498
lpi_gpio_get(struct gpio_chip * chip,unsigned int pin)499 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
500 {
501 struct lpi_pinctrl *state = gpiochip_get_data(chip);
502
503 return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
504 LPI_GPIO_VALUE_IN_MASK;
505 }
506
lpi_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)507 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
508 {
509 struct lpi_pinctrl *state = gpiochip_get_data(chip);
510 unsigned long config;
511
512 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
513
514 lpi_config_set(state->ctrl, pin, &config, 1);
515 }
516
517 #ifdef CONFIG_DEBUG_FS
518 #include <linux/seq_file.h>
519
lpi_regval_to_drive(u32 val)520 static unsigned int lpi_regval_to_drive(u32 val)
521 {
522 return (val + 1) * 2;
523 }
524
lpi_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned int offset,unsigned int gpio)525 static void lpi_gpio_dbg_show_one(struct seq_file *s,
526 struct pinctrl_dev *pctldev,
527 struct gpio_chip *chip,
528 unsigned int offset,
529 unsigned int gpio)
530 {
531 struct lpi_pinctrl *state = gpiochip_get_data(chip);
532 struct pinctrl_pin_desc pindesc;
533 unsigned int func;
534 int is_out;
535 int drive;
536 int pull;
537 u32 ctl_reg;
538
539 static const char * const pulls[] = {
540 "no pull",
541 "pull down",
542 "keeper",
543 "pull up"
544 };
545
546 pctldev = pctldev ? : state->ctrl;
547 pindesc = pctldev->desc->pins[offset];
548 ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
549 is_out = ctl_reg & LPI_GPIO_OE_MASK;
550
551 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
552 drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
553 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
554
555 seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
556 seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
557 seq_printf(s, " %s", pulls[pull]);
558 }
559
lpi_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)560 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
561 {
562 unsigned int gpio = chip->base;
563 unsigned int i;
564
565 for (i = 0; i < chip->ngpio; i++, gpio++) {
566 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
567 seq_puts(s, "\n");
568 }
569 }
570
571 #else
572 #define lpi_gpio_dbg_show NULL
573 #endif
574
575 static const struct gpio_chip lpi_gpio_template = {
576 .direction_input = lpi_gpio_direction_input,
577 .direction_output = lpi_gpio_direction_output,
578 .get = lpi_gpio_get,
579 .set = lpi_gpio_set,
580 .request = gpiochip_generic_request,
581 .free = gpiochip_generic_free,
582 .dbg_show = lpi_gpio_dbg_show,
583 };
584
lpi_pinctrl_probe(struct platform_device * pdev)585 static int lpi_pinctrl_probe(struct platform_device *pdev)
586 {
587 const struct lpi_pinctrl_variant_data *data;
588 struct device *dev = &pdev->dev;
589 struct lpi_pinctrl *pctrl;
590 int ret;
591
592 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
593 if (!pctrl)
594 return -ENOMEM;
595
596 platform_set_drvdata(pdev, pctrl);
597
598 data = of_device_get_match_data(dev);
599 if (!data)
600 return -EINVAL;
601
602 pctrl->data = data;
603 pctrl->dev = &pdev->dev;
604
605 pctrl->clks[0].id = "core";
606 pctrl->clks[1].id = "audio";
607
608 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
609 if (IS_ERR(pctrl->tlmm_base))
610 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
611 "TLMM resource not provided\n");
612
613 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
614 if (IS_ERR(pctrl->slew_base))
615 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
616 "Slew resource not provided\n");
617
618 ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
619 if (ret)
620 return dev_err_probe(dev, ret, "Can't get clocks\n");
621
622 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
623 if (ret)
624 return dev_err_probe(dev, ret, "Can't enable clocks\n");
625
626 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
627 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
628 pctrl->desc.confops = &lpi_gpio_pinconf_ops;
629 pctrl->desc.owner = THIS_MODULE;
630 pctrl->desc.name = dev_name(dev);
631 pctrl->desc.pins = data->pins;
632 pctrl->desc.npins = data->npins;
633 pctrl->chip = lpi_gpio_template;
634 pctrl->chip.parent = dev;
635 pctrl->chip.base = -1;
636 pctrl->chip.ngpio = data->npins;
637 pctrl->chip.label = dev_name(dev);
638 pctrl->chip.of_gpio_n_cells = 2;
639 pctrl->chip.can_sleep = false;
640
641 mutex_init(&pctrl->slew_access_lock);
642
643 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
644 if (IS_ERR(pctrl->ctrl)) {
645 ret = PTR_ERR(pctrl->ctrl);
646 dev_err(dev, "failed to add pin controller\n");
647 goto err_pinctrl;
648 }
649
650 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
651 if (ret) {
652 dev_err(pctrl->dev, "can't add gpio chip\n");
653 goto err_pinctrl;
654 }
655
656 return 0;
657
658 err_pinctrl:
659 mutex_destroy(&pctrl->slew_access_lock);
660 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
661
662 return ret;
663 }
664
lpi_pinctrl_remove(struct platform_device * pdev)665 static int lpi_pinctrl_remove(struct platform_device *pdev)
666 {
667 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
668
669 mutex_destroy(&pctrl->slew_access_lock);
670 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
671
672 return 0;
673 }
674
675 static const struct of_device_id lpi_pinctrl_of_match[] = {
676 {
677 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
678 .data = &sm8250_lpi_data,
679 },
680 { }
681 };
682 MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
683
684 static struct platform_driver lpi_pinctrl_driver = {
685 .driver = {
686 .name = "qcom-lpass-lpi-pinctrl",
687 .of_match_table = lpi_pinctrl_of_match,
688 },
689 .probe = lpi_pinctrl_probe,
690 .remove = lpi_pinctrl_remove,
691 };
692
693 module_platform_driver(lpi_pinctrl_driver);
694 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
695 MODULE_LICENSE("GPL");
696