1 /* SPDX-License-Identifier: GPL-2.0 */
2 /************************************************************************/
3 /*									*/
4 /*	dc395x.h							*/
5 /*									*/
6 /*	Device Driver for Tekram DC395(U/UW/F), DC315(U)		*/
7 /*	PCI SCSI Bus Master Host Adapter				*/
8 /*	(SCSI chip set used Tekram ASIC TRM-S1040)			*/
9 /*									*/
10 /************************************************************************/
11 #ifndef DC395x_H
12 #define DC395x_H
13 
14 /************************************************************************/
15 /*									*/
16 /*	Initial values							*/
17 /*									*/
18 /************************************************************************/
19 #define DC395x_MAX_CMD_QUEUE		32
20 /* #define DC395x_MAX_QTAGS		32 */
21 #define DC395x_MAX_QTAGS		16
22 #define DC395x_MAX_SCSI_ID		16
23 #define DC395x_MAX_CMD_PER_LUN		DC395x_MAX_QTAGS
24 #define DC395x_MAX_SG_TABLESIZE		64	/* HW limitation			*/
25 #define DC395x_MAX_SG_LISTENTRY		64	/* Must be equal or lower to previous	*/
26 						/* item					*/
27 #define DC395x_MAX_SRB_CNT		63
28 /* #define DC395x_MAX_CAN_QUEUE		7 * DC395x_MAX_QTAGS */
29 #define DC395x_MAX_CAN_QUEUE		DC395x_MAX_SRB_CNT
30 #define DC395x_END_SCAN			2
31 #define DC395x_SEL_TIMEOUT		153	/* 250 ms selection timeout (@ 40 MHz)	*/
32 #define DC395x_MAX_RETRIES		3
33 
34 #if 0
35 #define SYNC_FIRST
36 #endif
37 
38 #define NORM_REC_LVL			0
39 
40 /************************************************************************/
41 /*									*/
42 /*	Various definitions						*/
43 /*									*/
44 /************************************************************************/
45 #define BIT31				0x80000000
46 #define BIT30				0x40000000
47 #define BIT29				0x20000000
48 #define BIT28				0x10000000
49 #define BIT27				0x08000000
50 #define BIT26				0x04000000
51 #define BIT25				0x02000000
52 #define BIT24				0x01000000
53 #define BIT23				0x00800000
54 #define BIT22				0x00400000
55 #define BIT21				0x00200000
56 #define BIT20				0x00100000
57 #define BIT19				0x00080000
58 #define BIT18				0x00040000
59 #define BIT17				0x00020000
60 #define BIT16				0x00010000
61 #define BIT15				0x00008000
62 #define BIT14				0x00004000
63 #define BIT13				0x00002000
64 #define BIT12				0x00001000
65 #define BIT11				0x00000800
66 #define BIT10				0x00000400
67 #define BIT9				0x00000200
68 #define BIT8				0x00000100
69 #define BIT7				0x00000080
70 #define BIT6				0x00000040
71 #define BIT5				0x00000020
72 #define BIT4				0x00000010
73 #define BIT3				0x00000008
74 #define BIT2				0x00000004
75 #define BIT1				0x00000002
76 #define BIT0				0x00000001
77 
78 /* UnitCtrlFlag */
79 #define UNIT_ALLOCATED			BIT0
80 #define UNIT_INFO_CHANGED		BIT1
81 #define FORMATING_MEDIA			BIT2
82 #define UNIT_RETRY			BIT3
83 
84 /* UnitFlags */
85 #define DASD_SUPPORT			BIT0
86 #define SCSI_SUPPORT			BIT1
87 #define ASPI_SUPPORT			BIT2
88 
89 /* SRBState machine definition */
90 #define SRB_FREE			0x0000
91 #define SRB_WAIT			0x0001
92 #define SRB_READY			0x0002
93 #define SRB_MSGOUT			0x0004	/* arbitration+msg_out 1st byte		*/
94 #define SRB_MSGIN			0x0008
95 #define SRB_EXTEND_MSGIN		0x0010
96 #define SRB_COMMAND			0x0020
97 #define SRB_START_			0x0040	/* arbitration+msg_out+command_out	*/
98 #define SRB_DISCONNECT			0x0080
99 #define SRB_DATA_XFER			0x0100
100 #define SRB_XFERPAD			0x0200
101 #define SRB_STATUS			0x0400
102 #define SRB_COMPLETED			0x0800
103 #define SRB_ABORT_SENT			0x1000
104 #define SRB_DO_SYNC_NEGO		0x2000
105 #define SRB_DO_WIDE_NEGO		0x4000
106 #define SRB_UNEXPECT_RESEL		0x8000
107 
108 /************************************************************************/
109 /*									*/
110 /*	ACB Config							*/
111 /*									*/
112 /************************************************************************/
113 #define HCC_WIDE_CARD			0x20
114 #define HCC_SCSI_RESET			0x10
115 #define HCC_PARITY			0x08
116 #define HCC_AUTOTERM			0x04
117 #define HCC_LOW8TERM			0x02
118 #define HCC_UP8TERM			0x01
119 
120 /* ACBFlag */
121 #define RESET_DEV			BIT0
122 #define RESET_DETECT			BIT1
123 #define RESET_DONE			BIT2
124 
125 /* DCBFlag */
126 #define ABORT_DEV_			BIT0
127 
128 /* SRBstatus */
129 #define SRB_OK				BIT0
130 #define ABORTION			BIT1
131 #define OVER_RUN			BIT2
132 #define UNDER_RUN			BIT3
133 #define PARITY_ERROR			BIT4
134 #define SRB_ERROR			BIT5
135 
136 /* SRBFlag */
137 #define DATAOUT				BIT7
138 #define DATAIN				BIT6
139 #define RESIDUAL_VALID			BIT5
140 #define ENABLE_TIMER			BIT4
141 #define RESET_DEV0			BIT2
142 #define ABORT_DEV			BIT1
143 #define AUTO_REQSENSE			BIT0
144 
145 /* Adapter status */
146 #define H_STATUS_GOOD			0
147 #define H_SEL_TIMEOUT			0x11
148 #define H_OVER_UNDER_RUN		0x12
149 #define H_UNEXP_BUS_FREE		0x13
150 #define H_TARGET_PHASE_F		0x14
151 #define H_INVALID_CCB_OP		0x16
152 #define H_LINK_CCB_BAD			0x17
153 #define H_BAD_TARGET_DIR		0x18
154 #define H_DUPLICATE_CCB			0x19
155 #define H_BAD_CCB_OR_SG			0x1A
156 #define H_ABORT				0x0FF
157 
158 /* SCSI BUS Status byte codes */
159 #define SCSI_STAT_UNEXP_BUS_F		0xFD	/* Unexpect Bus Free			*/
160 #define SCSI_STAT_BUS_RST_DETECT	0xFE	/* Scsi Bus Reset detected		*/
161 #define SCSI_STAT_SEL_TIMEOUT		0xFF	/* Selection Time out			*/
162 
163 /* Sync_Mode */
164 #define SYNC_WIDE_TAG_ATNT_DISABLE	0
165 #define SYNC_NEGO_ENABLE		BIT0
166 #define SYNC_NEGO_DONE			BIT1
167 #define WIDE_NEGO_ENABLE		BIT2
168 #define WIDE_NEGO_DONE			BIT3
169 #define WIDE_NEGO_STATE			BIT4
170 #define EN_TAG_QUEUEING			BIT5
171 #define EN_ATN_STOP			BIT6
172 
173 #define SYNC_NEGO_OFFSET		15
174 
175 /* cmd->result */
176 #define STATUS_MASK_			0xFF
177 #define MSG_MASK			0xFF00
178 #define RETURN_MASK			0xFF0000
179 
180 /************************************************************************/
181 /*									*/
182 /*	Inquiry Data format						*/
183 /*									*/
184 /************************************************************************/
185 struct ScsiInqData
186 {						/* INQ					*/
187 	u8 DevType;				/* Periph Qualifier & Periph Dev Type	*/
188 	u8 RMB_TypeMod;				/* rem media bit & Dev Type Modifier	*/
189 	u8 Vers;				/* ISO, ECMA, & ANSI versions		*/
190 	u8 RDF;					/* AEN, TRMIOP, & response data format	*/
191 	u8 AddLen;				/* length of additional data		*/
192 	u8 Res1;				/* reserved				*/
193 	u8 Res2;				/* reserved				*/
194 	u8 Flags;				/* RelADr, Wbus32, Wbus16, Sync, etc.	*/
195 	u8 VendorID[8];				/* Vendor Identification		*/
196 	u8 ProductID[16];			/* Product Identification		*/
197 	u8 ProductRev[4];			/* Product Revision			*/
198 };
199 
200 						/* Inquiry byte 0 masks			*/
201 #define SCSI_DEVTYPE			0x1F	/* Peripheral Device Type		*/
202 #define SCSI_PERIPHQUAL			0xE0	/* Peripheral Qualifier			*/
203 						/* Inquiry byte 1 mask			*/
204 #define SCSI_REMOVABLE_MEDIA		0x80	/* Removable Media bit (1=removable)	*/
205 						/* Peripheral Device Type definitions	*/
206 						/* See include/scsi/scsi.h		*/
207 #define TYPE_NODEV		SCSI_DEVTYPE	/* Unknown or no device type		*/
208 #ifndef TYPE_PRINTER				/*					*/
209 # define TYPE_PRINTER			0x02	/* Printer device			*/
210 #endif						/*					*/
211 #ifndef TYPE_COMM				/*					*/
212 # define TYPE_COMM			0x09	/* Communications device		*/
213 #endif
214 
215 /************************************************************************/
216 /*									*/
217 /*	Inquiry flag definitions (Inq data byte 7)			*/
218 /*									*/
219 /************************************************************************/
220 #define SCSI_INQ_RELADR			0x80	/* device supports relative addressing	*/
221 #define SCSI_INQ_WBUS32			0x40	/* device supports 32 bit data xfers	*/
222 #define SCSI_INQ_WBUS16			0x20	/* device supports 16 bit data xfers	*/
223 #define SCSI_INQ_SYNC			0x10	/* device supports synchronous xfer	*/
224 #define SCSI_INQ_LINKED			0x08	/* device supports linked commands	*/
225 #define SCSI_INQ_CMDQUEUE		0x02	/* device supports command queueing	*/
226 #define SCSI_INQ_SFTRE			0x01	/* device supports soft resets		*/
227 
228 #define ENABLE_CE			1
229 #define DISABLE_CE			0
230 #define EEPROM_READ			0x80
231 
232 /************************************************************************/
233 /*									*/
234 /*	The PCI configuration register offset for TRM_S1040		*/
235 /*									*/
236 /************************************************************************/
237 #define TRM_S1040_ID			0x00	/* Vendor and Device ID			*/
238 #define TRM_S1040_COMMAND		0x04	/* PCI command register			*/
239 #define TRM_S1040_IOBASE		0x10	/* I/O Space base address		*/
240 #define TRM_S1040_ROMBASE		0x30	/* Expansion ROM Base Address		*/
241 #define TRM_S1040_INTLINE		0x3C	/* Interrupt line			*/
242 
243 /************************************************************************/
244 /*									*/
245 /*	The SCSI register offset for TRM_S1040				*/
246 /*									*/
247 /************************************************************************/
248 #define TRM_S1040_SCSI_STATUS		0x80	/* SCSI Status (R)			*/
249 #define COMMANDPHASEDONE		0x2000	/* SCSI command phase done		*/
250 #define SCSIXFERDONE			0x0800	/* SCSI SCSI transfer done		*/
251 #define SCSIXFERCNT_2_ZERO		0x0100	/* SCSI SCSI transfer count to zero	*/
252 #define SCSIINTERRUPT			0x0080	/* SCSI interrupt pending		*/
253 #define COMMANDABORT			0x0040	/* SCSI command abort			*/
254 #define SEQUENCERACTIVE			0x0020	/* SCSI sequencer active		*/
255 #define PHASEMISMATCH			0x0010	/* SCSI phase mismatch			*/
256 #define PARITYERROR			0x0008	/* SCSI parity error			*/
257 
258 #define PHASEMASK			0x0007	/* Phase MSG/CD/IO			*/
259 #define PH_DATA_OUT			0x00	/* Data out phase			*/
260 #define PH_DATA_IN			0x01	/* Data in phase			*/
261 #define PH_COMMAND			0x02	/* Command phase			*/
262 #define PH_STATUS			0x03	/* Status phase				*/
263 #define PH_BUS_FREE			0x05	/* Invalid phase used as bus free	*/
264 #define PH_MSG_OUT			0x06	/* Message out phase			*/
265 #define PH_MSG_IN			0x07	/* Message in phase			*/
266 
267 #define TRM_S1040_SCSI_CONTROL		0x80	/* SCSI Control (W)			*/
268 #define DO_CLRATN			0x0400	/* Clear ATN				*/
269 #define DO_SETATN			0x0200	/* Set ATN				*/
270 #define DO_CMDABORT			0x0100	/* Abort SCSI command			*/
271 #define DO_RSTMODULE			0x0010	/* Reset SCSI chip			*/
272 #define DO_RSTSCSI			0x0008	/* Reset SCSI bus			*/
273 #define DO_CLRFIFO			0x0004	/* Clear SCSI transfer FIFO		*/
274 #define DO_DATALATCH			0x0002	/* Enable SCSI bus data input (latched)	*/
275 /* #define DO_DATALATCH			0x0000 */	/* KG: DISable SCSI bus data latch	*/
276 #define DO_HWRESELECT			0x0001	/* Enable hardware reselection		*/
277 
278 #define TRM_S1040_SCSI_FIFOCNT		0x82	/* SCSI FIFO Counter 5bits(R)		*/
279 #define TRM_S1040_SCSI_SIGNAL		0x83	/* SCSI low level signal (R/W)		*/
280 
281 #define TRM_S1040_SCSI_INTSTATUS	0x84	/* SCSI Interrupt Status (R)		*/
282 #define INT_SCAM			0x80	/* SCAM selection interrupt		*/
283 #define INT_SELECT			0x40	/* Selection interrupt			*/
284 #define INT_SELTIMEOUT			0x20	/* Selection timeout interrupt		*/
285 #define INT_DISCONNECT			0x10	/* Bus disconnected interrupt		*/
286 #define INT_RESELECTED			0x08	/* Reselected interrupt			*/
287 #define INT_SCSIRESET			0x04	/* SCSI reset detected interrupt	*/
288 #define INT_BUSSERVICE			0x02	/* Bus service interrupt		*/
289 #define INT_CMDDONE			0x01	/* SCSI command done interrupt		*/
290 
291 #define TRM_S1040_SCSI_OFFSET		0x84	/* SCSI Offset Count (W)		*/
292 
293 /************************************************************************/
294 /*									*/
295 /*	Bit		Name		Definition			*/
296 /*	---------	-------------	----------------------------	*/
297 /*	07-05	0	RSVD		Reversed. Always 0.		*/
298 /*	04	0	OFFSET4		Reversed for LVDS. Always 0.	*/
299 /*	03-00	0	OFFSET[03:00]	Offset number from 0 to 15	*/
300 /*									*/
301 /************************************************************************/
302 
303 #define TRM_S1040_SCSI_SYNC		0x85	/* SCSI Synchronous Control (R/W)	*/
304 #define LVDS_SYNC			0x20	/* Enable LVDS synchronous		*/
305 #define WIDE_SYNC			0x10	/* Enable WIDE synchronous		*/
306 #define ALT_SYNC			0x08	/* Enable Fast-20 alternate synchronous	*/
307 
308 /************************************************************************/
309 /*									*/
310 /*	SYNCM	7    6    5    4    3       2       1       0		*/
311 /*	Name	RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0	*/
312 /*	Default	0    0    0    0    0       0       0       0		*/
313 /*									*/
314 /*	Bit		Name		Definition			*/
315 /*	---------	-------------	---------------------------	*/
316 /*	07-06	0	RSVD		Reversed. Always read 0		*/
317 /*	05	0	LVDS		Reversed. Always read 0		*/
318 /*	04	0	WIDE/WSCSI	Enable wide (16-bits) SCSI	*/
319 /*					transfer.			*/
320 /*	03	0	ALTPERD/ALTPD	Alternate (Sync./Period) mode.	*/
321 /*									*/
322 /*			@@ When this bit is set,			*/
323 /*			   the synchronous period bits 2:0		*/
324 /*			   in the Synchronous Mode register		*/
325 /*			   are used to transfer data			*/
326 /*			   at the Fast-20 rate.				*/
327 /*			@@ When this bit is unset,			*/
328 /*			   the synchronous period bits 2:0		*/
329 /*			   in the Synchronous Mode Register		*/
330 /*			   are used to transfer data			*/
331 /*			   at the Fast-10 rate (or Fast-40 w/ LVDS).	*/
332 /*									*/
333 /*	02-00	0	PERIOD[2:0]/	Synchronous SCSI Transfer Rate.	*/
334 /*			SXPD[02:00]	These 3 bits specify		*/
335 /*					the Synchronous SCSI Transfer	*/
336 /*					Rate for Fast-20 and Fast-10.	*/
337 /*					These bits are also reset	*/
338 /*					by a SCSI Bus reset.		*/
339 /*									*/
340 /*	For Fast-10 bit ALTPD = 0 and LVDS = 0				*/
341 /*	and bit2,bit1,bit0 is defined as follows :			*/
342 /*									*/
343 /*	000	100ns, 10.0 MHz						*/
344 /*	001	150ns,  6.6 MHz						*/
345 /*	010	200ns,  5.0 MHz						*/
346 /*	011	250ns,  4.0 MHz						*/
347 /*	100	300ns,  3.3 MHz						*/
348 /*	101	350ns,  2.8 MHz						*/
349 /*	110	400ns,  2.5 MHz						*/
350 /*	111	450ns,  2.2 MHz						*/
351 /*									*/
352 /*	For Fast-20 bit ALTPD = 1 and LVDS = 0				*/
353 /*	and bit2,bit1,bit0 is defined as follows :			*/
354 /*									*/
355 /*	000	 50ns, 20.0 MHz						*/
356 /*	001	 75ns, 13.3 MHz						*/
357 /*	010	100ns, 10.0 MHz						*/
358 /*	011	125ns,  8.0 MHz						*/
359 /*	100	150ns,  6.6 MHz						*/
360 /*	101	175ns,  5.7 MHz						*/
361 /*	110	200ns,  5.0 MHz						*/
362 /*	111	250ns,  4.0 MHz   KG: Maybe 225ns, 4.4 MHz		*/
363 /*									*/
364 /*	For Fast-40 bit ALTPD = 0 and LVDS = 1				*/
365 /*	and bit2,bit1,bit0 is defined as follows :			*/
366 /*									*/
367 /*	000	 25ns, 40.0 MHz						*/
368 /*	001	 50ns, 20.0 MHz						*/
369 /*	010	 75ns, 13.3 MHz						*/
370 /*	011	100ns, 10.0 MHz						*/
371 /*	100	125ns,  8.0 MHz						*/
372 /*	101	150ns,  6.6 MHz						*/
373 /*	110	175ns,  5.7 MHz						*/
374 /*	111	200ns,  5.0 MHz						*/
375 /*									*/
376 /************************************************************************/
377 
378 #define TRM_S1040_SCSI_TARGETID		0x86	/* SCSI Target ID (R/W)			*/
379 #define TRM_S1040_SCSI_IDMSG		0x87	/* SCSI Identify Message (R)		*/
380 #define TRM_S1040_SCSI_HOSTID		0x87	/* SCSI Host ID (W)			*/
381 #define TRM_S1040_SCSI_COUNTER		0x88	/* SCSI Transfer Counter 24bits(R/W)	*/
382 
383 #define TRM_S1040_SCSI_INTEN		0x8C	/* SCSI Interrupt Enable (R/W)		*/
384 #define EN_SCAM				0x80	/* Enable SCAM selection interrupt	*/
385 #define EN_SELECT			0x40	/* Enable selection interrupt		*/
386 #define EN_SELTIMEOUT			0x20	/* Enable selection timeout interrupt	*/
387 #define EN_DISCONNECT			0x10	/* Enable bus disconnected interrupt	*/
388 #define EN_RESELECTED			0x08	/* Enable reselected interrupt		*/
389 #define EN_SCSIRESET			0x04	/* Enable SCSI reset detected interrupt	*/
390 #define EN_BUSSERVICE			0x02	/* Enable bus service interrupt		*/
391 #define EN_CMDDONE			0x01	/* Enable SCSI command done interrupt	*/
392 
393 #define TRM_S1040_SCSI_CONFIG0		0x8D	/* SCSI Configuration 0 (R/W)		*/
394 #define PHASELATCH			0x40	/* Enable phase latch			*/
395 #define INITIATOR			0x20	/* Enable initiator mode		*/
396 #define PARITYCHECK			0x10	/* Enable parity check			*/
397 #define BLOCKRST			0x01	/* Disable SCSI reset1			*/
398 
399 #define TRM_S1040_SCSI_CONFIG1		0x8E	/* SCSI Configuration 1 (R/W)		*/
400 #define ACTIVE_NEGPLUS			0x10	/* Enhance active negation		*/
401 #define FILTER_DISABLE			0x08	/* Disable SCSI data filter		*/
402 #define FAST_FILTER			0x04	/* ?					*/
403 #define ACTIVE_NEG			0x02	/* Enable active negation		*/
404 
405 #define TRM_S1040_SCSI_CONFIG2		0x8F	/* SCSI Configuration 2 (R/W)		*/
406 #define CFG2_WIDEFIFO			0x02	/*					*/
407 
408 #define TRM_S1040_SCSI_COMMAND		0x90	/* SCSI Command (R/W)			*/
409 #define SCMD_COMP			0x12	/* Command complete			*/
410 #define SCMD_SEL_ATN			0x60	/* Selection with ATN			*/
411 #define SCMD_SEL_ATN3			0x64	/* Selection with ATN3			*/
412 #define SCMD_SEL_ATNSTOP		0xB8	/* Selection with ATN and Stop		*/
413 #define SCMD_FIFO_OUT			0xC0	/* SCSI FIFO transfer out		*/
414 #define SCMD_DMA_OUT			0xC1	/* SCSI DMA transfer out		*/
415 #define SCMD_FIFO_IN			0xC2	/* SCSI FIFO transfer in		*/
416 #define SCMD_DMA_IN			0xC3	/* SCSI DMA transfer in			*/
417 #define SCMD_MSGACCEPT			0xD8	/* Message accept			*/
418 
419 /************************************************************************/
420 /*									*/
421 /*	Code	Command Description					*/
422 /*	----	----------------------------------------		*/
423 /*	02	Enable reselection with FIFO				*/
424 /*	40	Select without ATN with FIFO				*/
425 /*	60	Select with ATN with FIFO				*/
426 /*	64	Select with ATN3 with FIFO				*/
427 /*	A0	Select with ATN and stop with FIFO			*/
428 /*	C0	Transfer information out with FIFO			*/
429 /*	C1	Transfer information out with DMA			*/
430 /*	C2	Transfer information in with FIFO			*/
431 /*	C3	Transfer information in with DMA			*/
432 /*	12	Initiator command complete with FIFO			*/
433 /*	50	Initiator transfer information out sequence without ATN	*/
434 /*		with FIFO						*/
435 /*	70	Initiator transfer information out sequence with ATN	*/
436 /*		with FIFO						*/
437 /*	74	Initiator transfer information out sequence with ATN3	*/
438 /*		with FIFO						*/
439 /*	52	Initiator transfer information in sequence without ATN	*/
440 /*		with FIFO						*/
441 /*	72	Initiator transfer information in sequence with ATN	*/
442 /*		with FIFO						*/
443 /*	76	Initiator transfer information in sequence with ATN3	*/
444 /*		with FIFO						*/
445 /*	90	Initiator transfer information out command complete	*/
446 /*		with FIFO						*/
447 /*	92	Initiator transfer information in command complete	*/
448 /*		with FIFO						*/
449 /*	D2	Enable selection					*/
450 /*	08	Reselection						*/
451 /*	48	Disconnect command with FIFO				*/
452 /*	88	Terminate command with FIFO				*/
453 /*	C8	Target command complete with FIFO			*/
454 /*	18	SCAM Arbitration/ Selection				*/
455 /*	5A	Enable reselection					*/
456 /*	98	Select without ATN with FIFO				*/
457 /*	B8	Select with ATN with FIFO				*/
458 /*	D8	Message Accepted					*/
459 /*	58	NOP							*/
460 /*									*/
461 /************************************************************************/
462 
463 #define TRM_S1040_SCSI_TIMEOUT		0x91	/* SCSI Time Out Value (R/W)		*/
464 #define TRM_S1040_SCSI_FIFO		0x98	/* SCSI FIFO (R/W)			*/
465 
466 #define TRM_S1040_SCSI_TCR0		0x9C	/* SCSI Target Control 0 (R/W)		*/
467 #define TCR0_WIDE_NEGO_DONE		0x8000	/* Wide nego done			*/
468 #define TCR0_SYNC_NEGO_DONE		0x4000	/* Synchronous nego done		*/
469 #define TCR0_ENABLE_LVDS		0x2000	/* Enable LVDS synchronous		*/
470 #define TCR0_ENABLE_WIDE		0x1000	/* Enable WIDE synchronous		*/
471 #define TCR0_ENABLE_ALT			0x0800	/* Enable alternate synchronous		*/
472 #define TCR0_PERIOD_MASK		0x0700	/* Transfer rate			*/
473 
474 #define TCR0_DO_WIDE_NEGO		0x0080	/* Do wide NEGO				*/
475 #define TCR0_DO_SYNC_NEGO		0x0040	/* Do sync NEGO				*/
476 #define TCR0_DISCONNECT_EN		0x0020	/* Disconnection enable			*/
477 #define TCR0_OFFSET_MASK		0x001F	/* Offset number			*/
478 
479 #define TRM_S1040_SCSI_TCR1		0x9E	/* SCSI Target Control 1 (R/W)		*/
480 #define MAXTAG_MASK			0x7F00	/* Maximum tags (127)			*/
481 #define NON_TAG_BUSY			0x0080	/* Non tag command active		*/
482 #define ACTTAG_MASK			0x007F	/* Active tags				*/
483 
484 /************************************************************************/
485 /*									*/
486 /*	The DMA register offset for TRM_S1040				*/
487 /*									*/
488 /************************************************************************/
489 #define TRM_S1040_DMA_COMMAND		0xA0	/* DMA Command (R/W)			*/
490 #define DMACMD_SG			0x02	/* Enable HW S/G support		*/
491 #define DMACMD_DIR			0x01	/* 1 = read from SCSI write to Host	*/
492 #define XFERDATAIN_SG			0x0103	/* Transfer data in  w/  SG		*/
493 #define XFERDATAOUT_SG			0x0102	/* Transfer data out w/  SG		*/
494 #define XFERDATAIN			0x0101	/* Transfer data in  w/o SG		*/
495 #define XFERDATAOUT			0x0100	/* Transfer data out w/o SG		*/
496 
497 #define TRM_S1040_DMA_FIFOCNT		0xA1	/* DMA FIFO Counter (R)			*/
498 
499 #define TRM_S1040_DMA_CONTROL		0xA1	/* DMA Control (W)			*/
500 #define DMARESETMODULE			0x10	/* Reset PCI/DMA module			*/
501 #define STOPDMAXFER			0x08	/* Stop  DMA transfer			*/
502 #define ABORTXFER			0x04	/* Abort DMA transfer			*/
503 #define CLRXFIFO			0x02	/* Clear DMA transfer FIFO		*/
504 #define STARTDMAXFER			0x01	/* Start DMA transfer			*/
505 
506 #define TRM_S1040_DMA_FIFOSTAT		0xA2	/* DMA FIFO Status (R)			*/
507 
508 #define TRM_S1040_DMA_STATUS		0xA3	/* DMA Interrupt Status (R/W)		*/
509 #define XFERPENDING			0x80	/* Transfer pending			*/
510 #define SCSIBUSY			0x40	/* SCSI busy				*/
511 #define GLOBALINT			0x20	/* DMA_INTEN bit 0-4 set		*/
512 #define FORCEDMACOMP			0x10	/* Force DMA transfer complete		*/
513 #define DMAXFERERROR			0x08	/* DMA transfer error			*/
514 #define DMAXFERABORT			0x04	/* DMA transfer abort			*/
515 #define DMAXFERCOMP			0x02	/* Bus Master XFER Complete status	*/
516 #define SCSICOMP			0x01	/* SCSI complete interrupt		*/
517 
518 #define TRM_S1040_DMA_INTEN		0xA4	/* DMA Interrupt Enable (R/W)		*/
519 #define EN_FORCEDMACOMP			0x10	/* Force DMA transfer complete		*/
520 #define EN_DMAXFERERROR			0x08	/* DMA transfer error			*/
521 #define EN_DMAXFERABORT			0x04	/* DMA transfer abort			*/
522 #define EN_DMAXFERCOMP			0x02	/* Bus Master XFER Complete status	*/
523 #define EN_SCSIINTR			0x01	/* Enable SCSI complete interrupt	*/
524 
525 #define TRM_S1040_DMA_CONFIG		0xA6	/* DMA Configuration (R/W)		*/
526 #define DMA_ENHANCE			0x8000	/* Enable DMA enhance feature (SG?)	*/
527 #define DMA_PCI_DUAL_ADDR		0x4000	/*					*/
528 #define DMA_CFG_RES			0x2000	/* Always 1				*/
529 #define DMA_AUTO_CLR_FIFO		0x1000	/* DISable DMA auto clear FIFO		*/
530 #define DMA_MEM_MULTI_READ		0x0800	/*					*/
531 #define DMA_MEM_WRITE_INVAL		0x0400	/* Memory write and invalidate		*/
532 #define DMA_FIFO_CTRL			0x0300	/* Control FIFO operation with DMA	*/
533 #define DMA_FIFO_HALF_HALF		0x0200	/* Keep half filled on both read/write	*/
534 
535 #define TRM_S1040_DMA_XCNT		0xA8	/* DMA Transfer Counter (R/W), 24bits	*/
536 #define TRM_S1040_DMA_CXCNT		0xAC	/* DMA Current Transfer Counter (R)	*/
537 #define TRM_S1040_DMA_XLOWADDR		0xB0	/* DMA Transfer Physical Low Address	*/
538 #define TRM_S1040_DMA_XHIGHADDR		0xB4	/* DMA Transfer Physical High Address	*/
539 
540 /************************************************************************/
541 /*									*/
542 /*	The general register offset for TRM_S1040			*/
543 /*									*/
544 /************************************************************************/
545 #define TRM_S1040_GEN_CONTROL		0xD4	/* Global Control			*/
546 #define CTRL_LED			0x80	/* Control onboard LED			*/
547 #define EN_EEPROM			0x10	/* Enable EEPROM programming		*/
548 #define DIS_TERM			0x08	/* Disable onboard termination		*/
549 #define AUTOTERM			0x04	/* Enable Auto SCSI terminator		*/
550 #define LOW8TERM			0x02	/* Enable Lower 8 bit SCSI terminator	*/
551 #define UP8TERM				0x01	/* Enable Upper 8 bit SCSI terminator	*/
552 
553 #define TRM_S1040_GEN_STATUS		0xD5	/* Global Status			*/
554 #define GTIMEOUT			0x80	/* Global timer reach 0			*/
555 #define EXT68HIGH			0x40	/* Higher 8 bit connected externally	*/
556 #define INT68HIGH			0x20	/* Higher 8 bit connected internally	*/
557 #define CON5068				0x10	/* External 50/68 pin connected (low)	*/
558 #define CON68				0x08	/* Internal 68 pin connected (low)	*/
559 #define CON50				0x04	/* Internal 50 pin connected (low!)	*/
560 #define WIDESCSI			0x02	/* Wide SCSI card			*/
561 #define STATUS_LOAD_DEFAULT		0x01	/*					*/
562 
563 #define TRM_S1040_GEN_NVRAM		0xD6	/* Serial NON-VOLATILE RAM port		*/
564 #define NVR_BITOUT			0x08	/* Serial data out			*/
565 #define NVR_BITIN			0x04	/* Serial data in			*/
566 #define NVR_CLOCK			0x02	/* Serial clock				*/
567 #define NVR_SELECT			0x01	/* Serial select			*/
568 
569 #define TRM_S1040_GEN_EDATA		0xD7	/* Parallel EEPROM data port		*/
570 #define TRM_S1040_GEN_EADDRESS		0xD8	/* Parallel EEPROM address		*/
571 #define TRM_S1040_GEN_TIMER		0xDB	/* Global timer				*/
572 
573 /************************************************************************/
574 /*									*/
575 /*	NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode	*/
576 /*									*/
577 /************************************************************************/
578 #define NTC_DO_WIDE_NEGO		0x20	/* Wide negotiate			*/
579 #define NTC_DO_TAG_QUEUEING		0x10	/* Enable SCSI tag queuing		*/
580 #define NTC_DO_SEND_START		0x08	/* Send start command SPINUP		*/
581 #define NTC_DO_DISCONNECT		0x04	/* Enable SCSI disconnect		*/
582 #define NTC_DO_SYNC_NEGO		0x02	/* Sync negotiation			*/
583 #define NTC_DO_PARITY_CHK		0x01	/* (it should define at NAC)		*/
584 						/* Parity check enable			*/
585 
586 /************************************************************************/
587 /*									*/
588 /*	Nvram Initiater bits definition					*/
589 /*									*/
590 /************************************************************************/
591 #if 0
592 #define MORE2_DRV			BIT0
593 #define GREATER_1G			BIT1
594 #define RST_SCSI_BUS			BIT2
595 #define ACTIVE_NEGATION			BIT3
596 #define NO_SEEK				BIT4
597 #define LUN_CHECK			BIT5
598 #endif
599 
600 /************************************************************************/
601 /*									*/
602 /*	Nvram Adapter Cfg bits definition				*/
603 /*									*/
604 /************************************************************************/
605 #define NAC_SCANLUN			0x20	/* Include LUN as BIOS device		*/
606 #define NAC_POWERON_SCSI_RESET		0x04	/* Power on reset enable		*/
607 #define NAC_GREATER_1G			0x02	/* > 1G support enable			*/
608 #define NAC_GT2DRIVES			0x01	/* Support more than 2 drives		*/
609 /* #define NAC_DO_PARITY_CHK		0x08 */	/* Parity check enable			*/
610 
611 #endif
612