1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
4 *
5 * Copyright (C) 2019 Linaro Ltd
6 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26
27 #include <media/v4l2-common.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mc.h>
31 #include <media/v4l2-subdev.h>
32
33 #define CSIS_DRIVER_NAME "imx7-mipi-csis"
34 #define CSIS_SUBDEV_NAME CSIS_DRIVER_NAME
35
36 #define CSIS_PAD_SINK 0
37 #define CSIS_PAD_SOURCE 1
38 #define CSIS_PADS_NUM 2
39
40 #define MIPI_CSIS_DEF_PIX_WIDTH 640
41 #define MIPI_CSIS_DEF_PIX_HEIGHT 480
42
43 /* Register map definition */
44
45 /* CSIS common control */
46 #define MIPI_CSIS_CMN_CTRL 0x04
47 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
48 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
49 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
50 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
51 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
52
53 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
54 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
55
56 /* CSIS clock control */
57 #define MIPI_CSIS_CLK_CTRL 0x08
58 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
59 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
60 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
61 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
62 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
63 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
64
65 /* CSIS Interrupt mask */
66 #define MIPI_CSIS_INT_MSK 0x10
67 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31)
68 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30)
69 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29)
70 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28)
71 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24)
72 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20)
73 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16)
74 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12)
75 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8)
76 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4)
77 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3)
78 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2)
79 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1)
80 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0)
81
82 /* CSIS Interrupt source */
83 #define MIPI_CSIS_INT_SRC 0x14
84 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31)
85 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30)
86 #define MIPI_CSIS_INT_SRC_EVEN BIT(30)
87 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29)
88 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28)
89 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28)
90 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28)
91 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24)
92 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20)
93 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16)
94 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12)
95 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8)
96 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4)
97 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3)
98 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2)
99 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1)
100 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0)
101 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff
102
103 /* D-PHY status control */
104 #define MIPI_CSIS_DPHY_STATUS 0x20
105 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8)
106 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4)
107 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1)
108 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0)
109
110 /* D-PHY common control */
111 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24
112 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24)
113 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)
114 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22)
115 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)
116 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6)
117 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5)
118 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1)
119 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0)
120 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0)
121
122 /* D-PHY Master and Slave Control register Low */
123 #define MIPI_CSIS_DPHY_BCTRL_L 0x30
124 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30)
125 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28)
126 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28)
127 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28)
128 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28)
129 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27)
130 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27)
131 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26)
132 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24)
133 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24)
134 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24)
135 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24)
136 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23)
137 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21)
138 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21)
139 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21)
140 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21)
141 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20)
142 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18)
143 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18)
144 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18)
145 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18)
146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17)
147 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15)
148 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15)
149 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15)
150 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14)
151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13)
152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13)
153 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12)
154 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11)
155 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10)
156 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0)
157
158 /* D-PHY Master and Slave Control register High */
159 #define MIPI_CSIS_DPHY_BCTRL_H 0x34
160 /* D-PHY Slave Control register Low */
161 #define MIPI_CSIS_DPHY_SCTRL_L 0x38
162 /* D-PHY Slave Control register High */
163 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c
164
165 /* ISP Configuration register */
166 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10)
167 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
168 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
169 #define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12)
170 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
171 #define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2)
172 #define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2)
173 #define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2)
174 #define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2)
175 #define MIPI_CSIS_ISPCFG_FMT_RAW14 (0x2d << 2)
176 /* User defined formats, x = 1...4 */
177 #define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + (x) - 1) << 2)
178 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
179
180 /* ISP Image Resolution register */
181 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)
182 #define CSIS_MAX_PIX_WIDTH 0xffff
183 #define CSIS_MAX_PIX_HEIGHT 0xffff
184
185 /* ISP SYNC register */
186 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10)
187 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18
188 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
189 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
190
191 /* ISP shadow registers */
192 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10)
193 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10)
194 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10)
195
196 /* Debug control register */
197 #define MIPI_CSIS_DBG_CTRL 0xc0
198
199 /* Non-image packet data buffers */
200 #define MIPI_CSIS_PKTDATA_ODD 0x2000
201 #define MIPI_CSIS_PKTDATA_EVEN 0x3000
202 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K
203
204 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
205
206 enum {
207 ST_POWERED = 1,
208 ST_STREAMING = 2,
209 ST_SUSPENDED = 4,
210 };
211
212 struct mipi_csis_event {
213 u32 mask;
214 const char * const name;
215 unsigned int counter;
216 };
217
218 static const struct mipi_csis_event mipi_csis_events[] = {
219 /* Errors */
220 { MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" },
221 { MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" },
222 { MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" },
223 { MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" },
224 { MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
225 { MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" },
226 { MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" },
227 { MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" },
228 /* Non-image data receive events */
229 { MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" },
230 { MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" },
231 { MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" },
232 { MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" },
233 /* Frame start/end */
234 { MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" },
235 { MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" },
236 };
237
238 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
239
240 enum mipi_csis_clk {
241 MIPI_CSIS_CLK_PCLK,
242 MIPI_CSIS_CLK_WRAP,
243 MIPI_CSIS_CLK_PHY,
244 };
245
246 static const char * const mipi_csis_clk_id[] = {
247 "pclk",
248 "wrap",
249 "phy",
250 };
251
252 struct csis_hw_reset {
253 struct regmap *src;
254 u8 req_src;
255 u8 rst_bit;
256 };
257
258 struct csi_state {
259 /* lock elements below */
260 struct mutex lock;
261 /* lock for event handler */
262 spinlock_t slock;
263 struct device *dev;
264 struct media_pad pads[CSIS_PADS_NUM];
265 struct v4l2_subdev mipi_sd;
266 struct v4l2_async_notifier notifier;
267 struct v4l2_subdev *src_sd;
268
269 u8 index;
270 struct platform_device *pdev;
271 struct phy *phy;
272 void __iomem *regs;
273 int irq;
274 u32 flags;
275
276 struct dentry *debugfs_root;
277 bool debug;
278
279 int num_clks;
280 struct clk_bulk_data *clks;
281
282 u32 clk_frequency;
283 u32 hs_settle;
284
285 struct reset_control *mrst;
286
287 const struct csis_pix_format *csis_fmt;
288 struct v4l2_mbus_framefmt format_mbus;
289
290 struct v4l2_fwnode_bus_mipi_csi2 bus;
291
292 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
293
294 struct csis_hw_reset hw_reset;
295 struct regulator *mipi_phy_regulator;
296 };
297
298 struct csis_pix_format {
299 u32 code;
300 u32 fmt_reg;
301 u8 width;
302 };
303
304 static const struct csis_pix_format mipi_csis_formats[] = {
305 /* YUV formats. */
306 {
307 .code = MEDIA_BUS_FMT_UYVY8_1X16,
308 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
309 .width = 16,
310 },
311 /* RAW (Bayer and greyscale) formats. */
312 {
313 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
314 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
315 .width = 8,
316 }, {
317 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
318 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
319 .width = 8,
320 }, {
321 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
322 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
323 .width = 8,
324 }, {
325 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
326 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
327 .width = 8,
328 }, {
329 .code = MEDIA_BUS_FMT_Y8_1X8,
330 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
331 .width = 8,
332 }, {
333 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
334 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
335 .width = 10,
336 }, {
337 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
338 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
339 .width = 10,
340 }, {
341 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
342 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
343 .width = 10,
344 }, {
345 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
346 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
347 .width = 10,
348 }, {
349 .code = MEDIA_BUS_FMT_Y10_1X10,
350 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
351 .width = 10,
352 }, {
353 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
354 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
355 .width = 12,
356 }, {
357 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
358 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
359 .width = 12,
360 }, {
361 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
362 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
363 .width = 12,
364 }, {
365 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
366 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
367 .width = 12,
368 }, {
369 .code = MEDIA_BUS_FMT_Y12_1X12,
370 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
371 .width = 12,
372 }, {
373 .code = MEDIA_BUS_FMT_SBGGR14_1X14,
374 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
375 .width = 14,
376 }, {
377 .code = MEDIA_BUS_FMT_SGBRG14_1X14,
378 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
379 .width = 14,
380 }, {
381 .code = MEDIA_BUS_FMT_SGRBG14_1X14,
382 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
383 .width = 14,
384 }, {
385 .code = MEDIA_BUS_FMT_SRGGB14_1X14,
386 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
387 .width = 14,
388 }
389 };
390
mipi_csis_write(struct csi_state * state,u32 reg,u32 val)391 static inline void mipi_csis_write(struct csi_state *state, u32 reg, u32 val)
392 {
393 writel(val, state->regs + reg);
394 }
395
mipi_csis_read(struct csi_state * state,u32 reg)396 static inline u32 mipi_csis_read(struct csi_state *state, u32 reg)
397 {
398 return readl(state->regs + reg);
399 }
400
mipi_csis_dump_regs(struct csi_state * state)401 static int mipi_csis_dump_regs(struct csi_state *state)
402 {
403 struct device *dev = &state->pdev->dev;
404 unsigned int i;
405 u32 cfg;
406 static const struct {
407 u32 offset;
408 const char * const name;
409 } registers[] = {
410 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
411 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
412 { MIPI_CSIS_INT_MSK, "INT_MSK" },
413 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
414 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
415 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
416 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
417 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
418 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
419 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
420 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
421 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
422 };
423
424 dev_info(dev, "--- REGISTERS ---\n");
425
426 for (i = 0; i < ARRAY_SIZE(registers); i++) {
427 cfg = mipi_csis_read(state, registers[i].offset);
428 dev_info(dev, "%14s: 0x%08x\n", registers[i].name, cfg);
429 }
430
431 return 0;
432 }
433
434 static struct csi_state *
mipi_notifier_to_csis_state(struct v4l2_async_notifier * n)435 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
436 {
437 return container_of(n, struct csi_state, notifier);
438 }
439
mipi_sd_to_csis_state(struct v4l2_subdev * sdev)440 static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
441 {
442 return container_of(sdev, struct csi_state, mipi_sd);
443 }
444
find_csis_format(u32 code)445 static const struct csis_pix_format *find_csis_format(u32 code)
446 {
447 unsigned int i;
448
449 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
450 if (code == mipi_csis_formats[i].code)
451 return &mipi_csis_formats[i];
452 return NULL;
453 }
454
mipi_csis_enable_interrupts(struct csi_state * state,bool on)455 static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
456 {
457 mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
458 }
459
mipi_csis_sw_reset(struct csi_state * state)460 static void mipi_csis_sw_reset(struct csi_state *state)
461 {
462 u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
463
464 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
465 val | MIPI_CSIS_CMN_CTRL_RESET);
466 usleep_range(10, 20);
467 }
468
mipi_csis_phy_init(struct csi_state * state)469 static int mipi_csis_phy_init(struct csi_state *state)
470 {
471 state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
472 if (IS_ERR(state->mipi_phy_regulator))
473 return PTR_ERR(state->mipi_phy_regulator);
474
475 return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
476 1000000);
477 }
478
mipi_csis_phy_reset(struct csi_state * state)479 static void mipi_csis_phy_reset(struct csi_state *state)
480 {
481 reset_control_assert(state->mrst);
482
483 msleep(20);
484
485 reset_control_deassert(state->mrst);
486 }
487
mipi_csis_system_enable(struct csi_state * state,int on)488 static void mipi_csis_system_enable(struct csi_state *state, int on)
489 {
490 u32 val, mask;
491
492 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
493 if (on)
494 val |= MIPI_CSIS_CMN_CTRL_ENABLE;
495 else
496 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
497 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
498
499 val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL);
500 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
501 if (on) {
502 mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
503 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
504 }
505 mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val);
506 }
507
508 /* Called with the state.lock mutex held */
__mipi_csis_set_format(struct csi_state * state)509 static void __mipi_csis_set_format(struct csi_state *state)
510 {
511 struct v4l2_mbus_framefmt *mf = &state->format_mbus;
512 u32 val;
513
514 /* Color format */
515 val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0));
516 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
517 val |= state->csis_fmt->fmt_reg;
518 mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val);
519
520 /* Pixel resolution */
521 val = mf->width | (mf->height << 16);
522 mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val);
523 }
524
mipi_csis_calculate_params(struct csi_state * state)525 static int mipi_csis_calculate_params(struct csi_state *state)
526 {
527 s64 link_freq;
528 u32 lane_rate;
529
530 /* Calculate the line rate from the pixel rate. */
531 link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler,
532 state->csis_fmt->width,
533 state->bus.num_data_lanes * 2);
534 if (link_freq < 0) {
535 dev_err(state->dev, "Unable to obtain link frequency: %d\n",
536 (int)link_freq);
537 return link_freq;
538 }
539
540 lane_rate = link_freq * 2;
541
542 if (lane_rate < 80000000 || lane_rate > 1500000000) {
543 dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
544 return -EINVAL;
545 }
546
547 /*
548 * The HSSETTLE counter value is document in a table, but can also
549 * easily be calculated.
550 */
551 state->hs_settle = (lane_rate - 5000000) / 45000000;
552 dev_dbg(state->dev, "lane rate %u, Ths_settle %u\n",
553 lane_rate, state->hs_settle);
554
555 return 0;
556 }
557
mipi_csis_set_params(struct csi_state * state)558 static void mipi_csis_set_params(struct csi_state *state)
559 {
560 int lanes = state->bus.num_data_lanes;
561 u32 val;
562
563 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
564 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
565 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
566 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
567 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
568
569 __mipi_csis_set_format(state);
570
571 mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL,
572 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle));
573
574 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
575 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
576 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
577 mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val);
578
579 val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
580 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
581 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
582 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
583 mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
584
585 mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_L,
586 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
587 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
588 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
589 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
590 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
591 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
592 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
593 mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_H, 0);
594
595 /* Update the shadow register. */
596 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
597 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
598 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
599 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
600 }
601
mipi_csis_clk_enable(struct csi_state * state)602 static int mipi_csis_clk_enable(struct csi_state *state)
603 {
604 return clk_bulk_prepare_enable(state->num_clks, state->clks);
605 }
606
mipi_csis_clk_disable(struct csi_state * state)607 static void mipi_csis_clk_disable(struct csi_state *state)
608 {
609 clk_bulk_disable_unprepare(state->num_clks, state->clks);
610 }
611
mipi_csis_clk_get(struct csi_state * state)612 static int mipi_csis_clk_get(struct csi_state *state)
613 {
614 struct device *dev = &state->pdev->dev;
615 unsigned int i;
616 int ret;
617
618 state->num_clks = ARRAY_SIZE(mipi_csis_clk_id);
619 state->clks = devm_kcalloc(dev, state->num_clks, sizeof(*state->clks),
620 GFP_KERNEL);
621
622 if (!state->clks)
623 return -ENOMEM;
624
625 for (i = 0; i < state->num_clks; i++)
626 state->clks[i].id = mipi_csis_clk_id[i];
627
628 ret = devm_clk_bulk_get(dev, state->num_clks, state->clks);
629 if (ret < 0)
630 return ret;
631
632 /* Set clock rate */
633 ret = clk_set_rate(state->clks[MIPI_CSIS_CLK_WRAP].clk,
634 state->clk_frequency);
635 if (ret < 0)
636 dev_err(dev, "set rate=%d failed: %d\n", state->clk_frequency,
637 ret);
638
639 return ret;
640 }
641
mipi_csis_start_stream(struct csi_state * state)642 static void mipi_csis_start_stream(struct csi_state *state)
643 {
644 mipi_csis_sw_reset(state);
645 mipi_csis_set_params(state);
646 mipi_csis_system_enable(state, true);
647 mipi_csis_enable_interrupts(state, true);
648 }
649
mipi_csis_stop_stream(struct csi_state * state)650 static void mipi_csis_stop_stream(struct csi_state *state)
651 {
652 mipi_csis_enable_interrupts(state, false);
653 mipi_csis_system_enable(state, false);
654 }
655
mipi_csis_clear_counters(struct csi_state * state)656 static void mipi_csis_clear_counters(struct csi_state *state)
657 {
658 unsigned long flags;
659 unsigned int i;
660
661 spin_lock_irqsave(&state->slock, flags);
662 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
663 state->events[i].counter = 0;
664 spin_unlock_irqrestore(&state->slock, flags);
665 }
666
mipi_csis_log_counters(struct csi_state * state,bool non_errors)667 static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
668 {
669 int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4;
670 struct device *dev = &state->pdev->dev;
671 unsigned long flags;
672
673 spin_lock_irqsave(&state->slock, flags);
674
675 for (i--; i >= 0; i--) {
676 if (state->events[i].counter > 0 || state->debug)
677 dev_info(dev, "%s events: %d\n", state->events[i].name,
678 state->events[i].counter);
679 }
680 spin_unlock_irqrestore(&state->slock, flags);
681 }
682
683 /*
684 * V4L2 subdev operations
685 */
mipi_csis_s_stream(struct v4l2_subdev * mipi_sd,int enable)686 static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable)
687 {
688 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
689 int ret;
690
691 if (enable) {
692 ret = mipi_csis_calculate_params(state);
693 if (ret < 0)
694 return ret;
695
696 mipi_csis_clear_counters(state);
697
698 ret = pm_runtime_get_sync(&state->pdev->dev);
699 if (ret < 0) {
700 pm_runtime_put_noidle(&state->pdev->dev);
701 return ret;
702 }
703 ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
704 if (ret < 0 && ret != -ENOIOCTLCMD)
705 goto done;
706 }
707
708 mutex_lock(&state->lock);
709
710 if (enable) {
711 if (state->flags & ST_SUSPENDED) {
712 ret = -EBUSY;
713 goto unlock;
714 }
715
716 mipi_csis_start_stream(state);
717 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
718 if (ret < 0)
719 goto unlock;
720
721 mipi_csis_log_counters(state, true);
722
723 state->flags |= ST_STREAMING;
724 } else {
725 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
726 ret = v4l2_subdev_call(state->src_sd, core, s_power, 0);
727 if (ret == -ENOIOCTLCMD)
728 ret = 0;
729 mipi_csis_stop_stream(state);
730 state->flags &= ~ST_STREAMING;
731 if (state->debug)
732 mipi_csis_log_counters(state, true);
733 }
734
735 unlock:
736 mutex_unlock(&state->lock);
737
738 done:
739 if (!enable || ret < 0)
740 pm_runtime_put(&state->pdev->dev);
741
742 return ret;
743 }
744
mipi_csis_link_setup(struct media_entity * entity,const struct media_pad * local_pad,const struct media_pad * remote_pad,u32 flags)745 static int mipi_csis_link_setup(struct media_entity *entity,
746 const struct media_pad *local_pad,
747 const struct media_pad *remote_pad, u32 flags)
748 {
749 struct v4l2_subdev *mipi_sd = media_entity_to_v4l2_subdev(entity);
750 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
751 struct v4l2_subdev *remote_sd;
752
753 dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
754 local_pad->entity->name);
755
756 /* We only care about the link to the source. */
757 if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
758 return 0;
759
760 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
761
762 if (flags & MEDIA_LNK_FL_ENABLED) {
763 if (state->src_sd)
764 return -EBUSY;
765
766 state->src_sd = remote_sd;
767 } else {
768 state->src_sd = NULL;
769 }
770
771 return 0;
772 }
773
774 static struct v4l2_mbus_framefmt *
mipi_csis_get_format(struct csi_state * state,struct v4l2_subdev_pad_config * cfg,enum v4l2_subdev_format_whence which,unsigned int pad)775 mipi_csis_get_format(struct csi_state *state,
776 struct v4l2_subdev_pad_config *cfg,
777 enum v4l2_subdev_format_whence which,
778 unsigned int pad)
779 {
780 if (which == V4L2_SUBDEV_FORMAT_TRY)
781 return v4l2_subdev_get_try_format(&state->mipi_sd, cfg, pad);
782
783 return &state->format_mbus;
784 }
785
mipi_csis_init_cfg(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg)786 static int mipi_csis_init_cfg(struct v4l2_subdev *mipi_sd,
787 struct v4l2_subdev_pad_config *cfg)
788 {
789 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
790 struct v4l2_mbus_framefmt *fmt_sink;
791 struct v4l2_mbus_framefmt *fmt_source;
792 enum v4l2_subdev_format_whence which;
793
794 which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
795 fmt_sink = mipi_csis_get_format(state, cfg, which, CSIS_PAD_SINK);
796
797 fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16;
798 fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH;
799 fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT;
800 fmt_sink->field = V4L2_FIELD_NONE;
801
802 fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M;
803 fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
804 fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
805 fmt_sink->quantization =
806 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
807 fmt_sink->ycbcr_enc);
808
809 /*
810 * When called from mipi_csis_subdev_init() to initialize the active
811 * configuration, cfg is NULL, which indicates there's no source pad
812 * configuration to set.
813 */
814 if (!cfg)
815 return 0;
816
817 fmt_source = mipi_csis_get_format(state, cfg, which, CSIS_PAD_SOURCE);
818 *fmt_source = *fmt_sink;
819
820 return 0;
821 }
822
mipi_csis_get_fmt(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * sdformat)823 static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd,
824 struct v4l2_subdev_pad_config *cfg,
825 struct v4l2_subdev_format *sdformat)
826 {
827 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
828 struct v4l2_mbus_framefmt *fmt;
829
830 mutex_lock(&state->lock);
831 fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
832 sdformat->format = *fmt;
833 mutex_unlock(&state->lock);
834
835 return 0;
836 }
837
mipi_csis_enum_mbus_code(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)838 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *mipi_sd,
839 struct v4l2_subdev_pad_config *cfg,
840 struct v4l2_subdev_mbus_code_enum *code)
841 {
842 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
843
844 /*
845 * The CSIS can't transcode in any way, the source format is identical
846 * to the sink format.
847 */
848 if (code->pad == CSIS_PAD_SOURCE) {
849 struct v4l2_mbus_framefmt *fmt;
850
851 if (code->index > 0)
852 return -EINVAL;
853
854 fmt = mipi_csis_get_format(state, cfg, code->which, code->pad);
855 code->code = fmt->code;
856 return 0;
857 }
858
859 if (code->pad != CSIS_PAD_SINK)
860 return -EINVAL;
861
862 if (code->index >= ARRAY_SIZE(mipi_csis_formats))
863 return -EINVAL;
864
865 code->code = mipi_csis_formats[code->index].code;
866
867 return 0;
868 }
869
mipi_csis_set_fmt(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * sdformat)870 static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd,
871 struct v4l2_subdev_pad_config *cfg,
872 struct v4l2_subdev_format *sdformat)
873 {
874 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
875 struct csis_pix_format const *csis_fmt;
876 struct v4l2_mbus_framefmt *fmt;
877 unsigned int align;
878
879 /*
880 * The CSIS can't transcode in any way, the source format can't be
881 * modified.
882 */
883 if (sdformat->pad == CSIS_PAD_SOURCE)
884 return mipi_csis_get_fmt(mipi_sd, cfg, sdformat);
885
886 if (sdformat->pad != CSIS_PAD_SINK)
887 return -EINVAL;
888
889 fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
890
891 mutex_lock(&state->lock);
892
893 /* Validate the media bus code and clamp the size. */
894 csis_fmt = find_csis_format(sdformat->format.code);
895 if (!csis_fmt)
896 csis_fmt = &mipi_csis_formats[0];
897
898 fmt->code = csis_fmt->code;
899 fmt->width = sdformat->format.width;
900 fmt->height = sdformat->format.height;
901
902 /*
903 * The total number of bits per line must be a multiple of 8. We thus
904 * need to align the width for formats that are not multiples of 8
905 * bits.
906 */
907 switch (csis_fmt->width % 8) {
908 case 0:
909 align = 0;
910 break;
911 case 4:
912 align = 1;
913 break;
914 case 2:
915 case 6:
916 align = 2;
917 break;
918 case 1:
919 case 3:
920 case 5:
921 case 7:
922 align = 3;
923 break;
924 }
925
926 v4l_bound_align_image(&fmt->width, 1, CSIS_MAX_PIX_WIDTH, align,
927 &fmt->height, 1, CSIS_MAX_PIX_HEIGHT, 0, 0);
928
929 sdformat->format = *fmt;
930
931 /* Propagate the format from sink to source. */
932 fmt = mipi_csis_get_format(state, cfg, sdformat->which,
933 CSIS_PAD_SOURCE);
934 *fmt = sdformat->format;
935
936 /* Store the CSIS format descriptor for active formats. */
937 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
938 state->csis_fmt = csis_fmt;
939
940 mutex_unlock(&state->lock);
941
942 return 0;
943 }
944
mipi_csis_log_status(struct v4l2_subdev * mipi_sd)945 static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd)
946 {
947 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
948
949 mutex_lock(&state->lock);
950 mipi_csis_log_counters(state, true);
951 if (state->debug && (state->flags & ST_POWERED))
952 mipi_csis_dump_regs(state);
953 mutex_unlock(&state->lock);
954
955 return 0;
956 }
957
mipi_csis_irq_handler(int irq,void * dev_id)958 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
959 {
960 struct csi_state *state = dev_id;
961 unsigned long flags;
962 unsigned int i;
963 u32 status;
964
965 status = mipi_csis_read(state, MIPI_CSIS_INT_SRC);
966
967 spin_lock_irqsave(&state->slock, flags);
968
969 /* Update the event/error counters */
970 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug) {
971 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
972 if (!(status & state->events[i].mask))
973 continue;
974 state->events[i].counter++;
975 }
976 }
977 spin_unlock_irqrestore(&state->slock, flags);
978
979 mipi_csis_write(state, MIPI_CSIS_INT_SRC, status);
980
981 return IRQ_HANDLED;
982 }
983
984 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
985 .log_status = mipi_csis_log_status,
986 };
987
988 static const struct media_entity_operations mipi_csis_entity_ops = {
989 .link_setup = mipi_csis_link_setup,
990 .link_validate = v4l2_subdev_link_validate,
991 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
992 };
993
994 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
995 .s_stream = mipi_csis_s_stream,
996 };
997
998 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
999 .init_cfg = mipi_csis_init_cfg,
1000 .enum_mbus_code = mipi_csis_enum_mbus_code,
1001 .get_fmt = mipi_csis_get_fmt,
1002 .set_fmt = mipi_csis_set_fmt,
1003 };
1004
1005 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1006 .core = &mipi_csis_core_ops,
1007 .video = &mipi_csis_video_ops,
1008 .pad = &mipi_csis_pad_ops,
1009 };
1010
mipi_csis_parse_dt(struct platform_device * pdev,struct csi_state * state)1011 static int mipi_csis_parse_dt(struct platform_device *pdev,
1012 struct csi_state *state)
1013 {
1014 struct device_node *node = pdev->dev.of_node;
1015
1016 if (of_property_read_u32(node, "clock-frequency",
1017 &state->clk_frequency))
1018 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
1019
1020 /* Get MIPI PHY resets */
1021 state->mrst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1022 if (IS_ERR(state->mrst))
1023 return PTR_ERR(state->mrst);
1024
1025 return 0;
1026 }
1027
1028 static int mipi_csis_pm_resume(struct device *dev, bool runtime);
1029
mipi_csis_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)1030 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1031 struct v4l2_subdev *sd,
1032 struct v4l2_async_subdev *asd)
1033 {
1034 struct csi_state *state = mipi_notifier_to_csis_state(notifier);
1035 struct media_pad *sink = &state->mipi_sd.entity.pads[CSIS_PAD_SINK];
1036
1037 return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1038 }
1039
1040 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1041 .bound = mipi_csis_notify_bound,
1042 };
1043
mipi_csis_subdev_init(struct v4l2_subdev * mipi_sd,struct platform_device * pdev,const struct v4l2_subdev_ops * ops)1044 static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd,
1045 struct platform_device *pdev,
1046 const struct v4l2_subdev_ops *ops)
1047 {
1048 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1049
1050 v4l2_subdev_init(mipi_sd, ops);
1051 mipi_sd->owner = THIS_MODULE;
1052 snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d",
1053 CSIS_SUBDEV_NAME, state->index);
1054
1055 mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1056 mipi_sd->ctrl_handler = NULL;
1057
1058 mipi_sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1059 mipi_sd->entity.ops = &mipi_csis_entity_ops;
1060
1061 mipi_sd->dev = &pdev->dev;
1062
1063 state->csis_fmt = &mipi_csis_formats[0];
1064 mipi_csis_init_cfg(mipi_sd, NULL);
1065
1066 v4l2_set_subdevdata(mipi_sd, &pdev->dev);
1067
1068 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1069 | MEDIA_PAD_FL_MUST_CONNECT;
1070 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1071 | MEDIA_PAD_FL_MUST_CONNECT;
1072 return media_entity_pads_init(&mipi_sd->entity, CSIS_PADS_NUM,
1073 state->pads);
1074 }
1075
mipi_csis_async_register(struct csi_state * state)1076 static int mipi_csis_async_register(struct csi_state *state)
1077 {
1078 struct v4l2_fwnode_endpoint vep = {
1079 .bus_type = V4L2_MBUS_CSI2_DPHY,
1080 };
1081 struct v4l2_async_subdev *asd;
1082 struct fwnode_handle *ep;
1083 int ret;
1084
1085 v4l2_async_notifier_init(&state->notifier);
1086
1087 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
1088 FWNODE_GRAPH_ENDPOINT_NEXT);
1089 if (!ep)
1090 return -ENOTCONN;
1091
1092 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1093 if (ret)
1094 goto err_parse;
1095
1096 state->bus = vep.bus.mipi_csi2;
1097
1098 dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
1099 dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
1100
1101 asd = v4l2_async_notifier_add_fwnode_remote_subdev(
1102 &state->notifier, ep, struct v4l2_async_subdev);
1103 if (IS_ERR(asd)) {
1104 ret = PTR_ERR(asd);
1105 goto err_parse;
1106 }
1107
1108 fwnode_handle_put(ep);
1109
1110 state->notifier.ops = &mipi_csis_notify_ops;
1111
1112 ret = v4l2_async_subdev_notifier_register(&state->mipi_sd,
1113 &state->notifier);
1114 if (ret)
1115 return ret;
1116
1117 return v4l2_async_register_subdev(&state->mipi_sd);
1118
1119 err_parse:
1120 fwnode_handle_put(ep);
1121
1122 return ret;
1123 }
1124
mipi_csis_dump_regs_show(struct seq_file * m,void * private)1125 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
1126 {
1127 struct csi_state *state = m->private;
1128
1129 return mipi_csis_dump_regs(state);
1130 }
1131 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
1132
mipi_csis_debugfs_init(struct csi_state * state)1133 static void mipi_csis_debugfs_init(struct csi_state *state)
1134 {
1135 state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
1136
1137 debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
1138 &state->debug);
1139 debugfs_create_file("dump_regs", 0600, state->debugfs_root, state,
1140 &mipi_csis_dump_regs_fops);
1141 }
1142
mipi_csis_debugfs_exit(struct csi_state * state)1143 static void mipi_csis_debugfs_exit(struct csi_state *state)
1144 {
1145 debugfs_remove_recursive(state->debugfs_root);
1146 }
1147
mipi_csis_probe(struct platform_device * pdev)1148 static int mipi_csis_probe(struct platform_device *pdev)
1149 {
1150 struct device *dev = &pdev->dev;
1151 struct csi_state *state;
1152 int ret;
1153
1154 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1155 if (!state)
1156 return -ENOMEM;
1157
1158 spin_lock_init(&state->slock);
1159
1160 state->pdev = pdev;
1161 state->dev = dev;
1162
1163 ret = mipi_csis_parse_dt(pdev, state);
1164 if (ret < 0) {
1165 dev_err(dev, "Failed to parse device tree: %d\n", ret);
1166 return ret;
1167 }
1168
1169 ret = mipi_csis_phy_init(state);
1170 if (ret < 0)
1171 return ret;
1172
1173 mipi_csis_phy_reset(state);
1174
1175 state->regs = devm_platform_ioremap_resource(pdev, 0);
1176 if (IS_ERR(state->regs))
1177 return PTR_ERR(state->regs);
1178
1179 state->irq = platform_get_irq(pdev, 0);
1180 if (state->irq < 0)
1181 return state->irq;
1182
1183 ret = mipi_csis_clk_get(state);
1184 if (ret < 0)
1185 return ret;
1186
1187 ret = mipi_csis_clk_enable(state);
1188 if (ret < 0) {
1189 dev_err(state->dev, "failed to enable clocks: %d\n", ret);
1190 return ret;
1191 }
1192
1193 ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler,
1194 0, dev_name(dev), state);
1195 if (ret) {
1196 dev_err(dev, "Interrupt request failed\n");
1197 goto disable_clock;
1198 }
1199
1200 platform_set_drvdata(pdev, &state->mipi_sd);
1201
1202 mutex_init(&state->lock);
1203 ret = mipi_csis_subdev_init(&state->mipi_sd, pdev,
1204 &mipi_csis_subdev_ops);
1205 if (ret < 0)
1206 goto disable_clock;
1207
1208 ret = mipi_csis_async_register(state);
1209 if (ret < 0) {
1210 dev_err(&pdev->dev, "async register failed: %d\n", ret);
1211 goto cleanup;
1212 }
1213
1214 memcpy(state->events, mipi_csis_events, sizeof(state->events));
1215
1216 mipi_csis_debugfs_init(state);
1217 pm_runtime_enable(dev);
1218 if (!pm_runtime_enabled(dev)) {
1219 ret = mipi_csis_pm_resume(dev, true);
1220 if (ret < 0)
1221 goto unregister_all;
1222 }
1223
1224 dev_info(&pdev->dev, "lanes: %d, freq: %u\n",
1225 state->bus.num_data_lanes, state->clk_frequency);
1226
1227 return 0;
1228
1229 unregister_all:
1230 mipi_csis_debugfs_exit(state);
1231 cleanup:
1232 media_entity_cleanup(&state->mipi_sd.entity);
1233 v4l2_async_notifier_unregister(&state->notifier);
1234 v4l2_async_notifier_cleanup(&state->notifier);
1235 v4l2_async_unregister_subdev(&state->mipi_sd);
1236 disable_clock:
1237 mipi_csis_clk_disable(state);
1238 mutex_destroy(&state->lock);
1239
1240 return ret;
1241 }
1242
mipi_csis_pm_suspend(struct device * dev,bool runtime)1243 static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1244 {
1245 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1246 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1247 int ret = 0;
1248
1249 mutex_lock(&state->lock);
1250 if (state->flags & ST_POWERED) {
1251 mipi_csis_stop_stream(state);
1252 ret = regulator_disable(state->mipi_phy_regulator);
1253 if (ret)
1254 goto unlock;
1255 mipi_csis_clk_disable(state);
1256 state->flags &= ~ST_POWERED;
1257 if (!runtime)
1258 state->flags |= ST_SUSPENDED;
1259 }
1260
1261 unlock:
1262 mutex_unlock(&state->lock);
1263
1264 return ret ? -EAGAIN : 0;
1265 }
1266
mipi_csis_pm_resume(struct device * dev,bool runtime)1267 static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1268 {
1269 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1270 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1271 int ret = 0;
1272
1273 mutex_lock(&state->lock);
1274 if (!runtime && !(state->flags & ST_SUSPENDED))
1275 goto unlock;
1276
1277 if (!(state->flags & ST_POWERED)) {
1278 ret = regulator_enable(state->mipi_phy_regulator);
1279 if (ret)
1280 goto unlock;
1281
1282 state->flags |= ST_POWERED;
1283 mipi_csis_clk_enable(state);
1284 }
1285 if (state->flags & ST_STREAMING)
1286 mipi_csis_start_stream(state);
1287
1288 state->flags &= ~ST_SUSPENDED;
1289
1290 unlock:
1291 mutex_unlock(&state->lock);
1292
1293 return ret ? -EAGAIN : 0;
1294 }
1295
mipi_csis_suspend(struct device * dev)1296 static int __maybe_unused mipi_csis_suspend(struct device *dev)
1297 {
1298 return mipi_csis_pm_suspend(dev, false);
1299 }
1300
mipi_csis_resume(struct device * dev)1301 static int __maybe_unused mipi_csis_resume(struct device *dev)
1302 {
1303 return mipi_csis_pm_resume(dev, false);
1304 }
1305
mipi_csis_runtime_suspend(struct device * dev)1306 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1307 {
1308 return mipi_csis_pm_suspend(dev, true);
1309 }
1310
mipi_csis_runtime_resume(struct device * dev)1311 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1312 {
1313 return mipi_csis_pm_resume(dev, true);
1314 }
1315
mipi_csis_remove(struct platform_device * pdev)1316 static int mipi_csis_remove(struct platform_device *pdev)
1317 {
1318 struct v4l2_subdev *mipi_sd = platform_get_drvdata(pdev);
1319 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1320
1321 mipi_csis_debugfs_exit(state);
1322 v4l2_async_notifier_unregister(&state->notifier);
1323 v4l2_async_notifier_cleanup(&state->notifier);
1324 v4l2_async_unregister_subdev(&state->mipi_sd);
1325
1326 pm_runtime_disable(&pdev->dev);
1327 mipi_csis_pm_suspend(&pdev->dev, true);
1328 mipi_csis_clk_disable(state);
1329 media_entity_cleanup(&state->mipi_sd.entity);
1330 mutex_destroy(&state->lock);
1331 pm_runtime_set_suspended(&pdev->dev);
1332
1333 return 0;
1334 }
1335
1336 static const struct dev_pm_ops mipi_csis_pm_ops = {
1337 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1338 NULL)
1339 SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1340 };
1341
1342 static const struct of_device_id mipi_csis_of_match[] = {
1343 { .compatible = "fsl,imx7-mipi-csi2", },
1344 { /* sentinel */ },
1345 };
1346 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1347
1348 static struct platform_driver mipi_csis_driver = {
1349 .probe = mipi_csis_probe,
1350 .remove = mipi_csis_remove,
1351 .driver = {
1352 .of_match_table = mipi_csis_of_match,
1353 .name = CSIS_DRIVER_NAME,
1354 .pm = &mipi_csis_pm_ops,
1355 },
1356 };
1357
1358 module_platform_driver(mipi_csis_driver);
1359
1360 MODULE_DESCRIPTION("i.MX7 MIPI CSI-2 Receiver driver");
1361 MODULE_LICENSE("GPL v2");
1362 MODULE_ALIAS("platform:imx7-mipi-csi2");
1363