1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _LINUX_QCOM_GENI_SE
7 #define _LINUX_QCOM_GENI_SE
8
9 #include <linux/interconnect.h>
10
11 /* Transfer mode supported by GENI Serial Engines */
12 enum geni_se_xfer_mode {
13 GENI_SE_INVALID,
14 GENI_SE_FIFO,
15 GENI_SE_DMA,
16 };
17
18 /* Protocols supported by GENI Serial Engines */
19 enum geni_se_protocol_type {
20 GENI_SE_NONE,
21 GENI_SE_SPI,
22 GENI_SE_UART,
23 GENI_SE_I2C,
24 GENI_SE_I3C,
25 };
26
27 struct geni_wrapper;
28 struct clk;
29
30 enum geni_icc_path_index {
31 GENI_TO_CORE,
32 CPU_TO_GENI,
33 GENI_TO_DDR
34 };
35
36 struct geni_icc_path {
37 struct icc_path *path;
38 unsigned int avg_bw;
39 };
40
41 /**
42 * struct geni_se - GENI Serial Engine
43 * @base: Base Address of the Serial Engine's register block
44 * @dev: Pointer to the Serial Engine device
45 * @wrapper: Pointer to the parent QUP Wrapper core
46 * @clk: Handle to the core serial engine clock
47 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl
48 * @clk_perf_tbl: Table of clock frequency input to serial engine clock
49 * @icc_paths: Array of ICC paths for SE
50 */
51 struct geni_se {
52 void __iomem *base;
53 struct device *dev;
54 struct geni_wrapper *wrapper;
55 struct clk *clk;
56 unsigned int num_clk_levels;
57 unsigned long *clk_perf_tbl;
58 struct geni_icc_path icc_paths[3];
59 };
60
61 /* Common SE registers */
62 #define GENI_FORCE_DEFAULT_REG 0x20
63 #define SE_GENI_STATUS 0x40
64 #define GENI_SER_M_CLK_CFG 0x48
65 #define GENI_SER_S_CLK_CFG 0x4c
66 #define GENI_FW_REVISION_RO 0x68
67 #define SE_GENI_CLK_SEL 0x7c
68 #define SE_GENI_DMA_MODE_EN 0x258
69 #define SE_GENI_M_CMD0 0x600
70 #define SE_GENI_M_CMD_CTRL_REG 0x604
71 #define SE_GENI_M_IRQ_STATUS 0x610
72 #define SE_GENI_M_IRQ_EN 0x614
73 #define SE_GENI_M_IRQ_CLEAR 0x618
74 #define SE_GENI_S_CMD0 0x630
75 #define SE_GENI_S_CMD_CTRL_REG 0x634
76 #define SE_GENI_S_IRQ_STATUS 0x640
77 #define SE_GENI_S_IRQ_EN 0x644
78 #define SE_GENI_S_IRQ_CLEAR 0x648
79 #define SE_GENI_TX_FIFOn 0x700
80 #define SE_GENI_RX_FIFOn 0x780
81 #define SE_GENI_TX_FIFO_STATUS 0x800
82 #define SE_GENI_RX_FIFO_STATUS 0x804
83 #define SE_GENI_TX_WATERMARK_REG 0x80c
84 #define SE_GENI_RX_WATERMARK_REG 0x810
85 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814
86 #define SE_GENI_IOS 0x908
87 #define SE_DMA_TX_IRQ_STAT 0xc40
88 #define SE_DMA_TX_IRQ_CLR 0xc44
89 #define SE_DMA_TX_FSM_RST 0xc58
90 #define SE_DMA_RX_IRQ_STAT 0xd40
91 #define SE_DMA_RX_IRQ_CLR 0xd44
92 #define SE_DMA_RX_FSM_RST 0xd58
93 #define SE_HW_PARAM_0 0xe24
94 #define SE_HW_PARAM_1 0xe28
95
96 /* GENI_FORCE_DEFAULT_REG fields */
97 #define FORCE_DEFAULT BIT(0)
98
99 /* GENI_STATUS fields */
100 #define M_GENI_CMD_ACTIVE BIT(0)
101 #define S_GENI_CMD_ACTIVE BIT(12)
102
103 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
104 #define SER_CLK_EN BIT(0)
105 #define CLK_DIV_MSK GENMASK(15, 4)
106 #define CLK_DIV_SHFT 4
107
108 /* GENI_FW_REVISION_RO fields */
109 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
110 #define FW_REV_PROTOCOL_SHFT 8
111
112 /* GENI_CLK_SEL fields */
113 #define CLK_SEL_MSK GENMASK(2, 0)
114
115 /* SE_GENI_DMA_MODE_EN */
116 #define GENI_DMA_MODE_EN BIT(0)
117
118 /* GENI_M_CMD0 fields */
119 #define M_OPCODE_MSK GENMASK(31, 27)
120 #define M_OPCODE_SHFT 27
121 #define M_PARAMS_MSK GENMASK(26, 0)
122
123 /* GENI_M_CMD_CTRL_REG */
124 #define M_GENI_CMD_CANCEL BIT(2)
125 #define M_GENI_CMD_ABORT BIT(1)
126 #define M_GENI_DISABLE BIT(0)
127
128 /* GENI_S_CMD0 fields */
129 #define S_OPCODE_MSK GENMASK(31, 27)
130 #define S_OPCODE_SHFT 27
131 #define S_PARAMS_MSK GENMASK(26, 0)
132
133 /* GENI_S_CMD_CTRL_REG */
134 #define S_GENI_CMD_CANCEL BIT(2)
135 #define S_GENI_CMD_ABORT BIT(1)
136 #define S_GENI_DISABLE BIT(0)
137
138 /* GENI_M_IRQ_EN fields */
139 #define M_CMD_DONE_EN BIT(0)
140 #define M_CMD_OVERRUN_EN BIT(1)
141 #define M_ILLEGAL_CMD_EN BIT(2)
142 #define M_CMD_FAILURE_EN BIT(3)
143 #define M_CMD_CANCEL_EN BIT(4)
144 #define M_CMD_ABORT_EN BIT(5)
145 #define M_TIMESTAMP_EN BIT(6)
146 #define M_RX_IRQ_EN BIT(7)
147 #define M_GP_SYNC_IRQ_0_EN BIT(8)
148 #define M_GP_IRQ_0_EN BIT(9)
149 #define M_GP_IRQ_1_EN BIT(10)
150 #define M_GP_IRQ_2_EN BIT(11)
151 #define M_GP_IRQ_3_EN BIT(12)
152 #define M_GP_IRQ_4_EN BIT(13)
153 #define M_GP_IRQ_5_EN BIT(14)
154 #define M_IO_DATA_DEASSERT_EN BIT(22)
155 #define M_IO_DATA_ASSERT_EN BIT(23)
156 #define M_RX_FIFO_RD_ERR_EN BIT(24)
157 #define M_RX_FIFO_WR_ERR_EN BIT(25)
158 #define M_RX_FIFO_WATERMARK_EN BIT(26)
159 #define M_RX_FIFO_LAST_EN BIT(27)
160 #define M_TX_FIFO_RD_ERR_EN BIT(28)
161 #define M_TX_FIFO_WR_ERR_EN BIT(29)
162 #define M_TX_FIFO_WATERMARK_EN BIT(30)
163 #define M_SEC_IRQ_EN BIT(31)
164 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
165 M_IO_DATA_DEASSERT_EN | \
166 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
167 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
168 M_TX_FIFO_WR_ERR_EN)
169
170 /* GENI_S_IRQ_EN fields */
171 #define S_CMD_DONE_EN BIT(0)
172 #define S_CMD_OVERRUN_EN BIT(1)
173 #define S_ILLEGAL_CMD_EN BIT(2)
174 #define S_CMD_FAILURE_EN BIT(3)
175 #define S_CMD_CANCEL_EN BIT(4)
176 #define S_CMD_ABORT_EN BIT(5)
177 #define S_GP_SYNC_IRQ_0_EN BIT(8)
178 #define S_GP_IRQ_0_EN BIT(9)
179 #define S_GP_IRQ_1_EN BIT(10)
180 #define S_GP_IRQ_2_EN BIT(11)
181 #define S_GP_IRQ_3_EN BIT(12)
182 #define S_GP_IRQ_4_EN BIT(13)
183 #define S_GP_IRQ_5_EN BIT(14)
184 #define S_IO_DATA_DEASSERT_EN BIT(22)
185 #define S_IO_DATA_ASSERT_EN BIT(23)
186 #define S_RX_FIFO_RD_ERR_EN BIT(24)
187 #define S_RX_FIFO_WR_ERR_EN BIT(25)
188 #define S_RX_FIFO_WATERMARK_EN BIT(26)
189 #define S_RX_FIFO_LAST_EN BIT(27)
190 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
191 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
192
193 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
194 #define WATERMARK_MSK GENMASK(5, 0)
195
196 /* GENI_TX_FIFO_STATUS fields */
197 #define TX_FIFO_WC GENMASK(27, 0)
198
199 /* GENI_RX_FIFO_STATUS fields */
200 #define RX_LAST BIT(31)
201 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
202 #define RX_LAST_BYTE_VALID_SHFT 28
203 #define RX_FIFO_WC_MSK GENMASK(24, 0)
204
205 /* SE_GENI_IOS fields */
206 #define IO2_DATA_IN BIT(1)
207 #define RX_DATA_IN BIT(0)
208
209 /* SE_DMA_TX_IRQ_STAT Register fields */
210 #define TX_DMA_DONE BIT(0)
211 #define TX_EOT BIT(1)
212 #define TX_SBE BIT(2)
213 #define TX_RESET_DONE BIT(3)
214
215 /* SE_DMA_RX_IRQ_STAT Register fields */
216 #define RX_DMA_DONE BIT(0)
217 #define RX_EOT BIT(1)
218 #define RX_SBE BIT(2)
219 #define RX_RESET_DONE BIT(3)
220 #define RX_FLUSH_DONE BIT(4)
221 #define RX_GENI_GP_IRQ GENMASK(10, 5)
222 #define RX_GENI_CANCEL_IRQ BIT(11)
223 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
224
225 /* SE_HW_PARAM_0 fields */
226 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
227 #define TX_FIFO_WIDTH_SHFT 24
228 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
229 #define TX_FIFO_DEPTH_SHFT 16
230
231 /* SE_HW_PARAM_1 fields */
232 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
233 #define RX_FIFO_WIDTH_SHFT 24
234 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
235 #define RX_FIFO_DEPTH_SHFT 16
236
237 #define HW_VER_MAJOR_MASK GENMASK(31, 28)
238 #define HW_VER_MAJOR_SHFT 28
239 #define HW_VER_MINOR_MASK GENMASK(27, 16)
240 #define HW_VER_MINOR_SHFT 16
241 #define HW_VER_STEP_MASK GENMASK(15, 0)
242
243 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
244 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
245 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
246
247 /* QUP SE VERSION value for major number 2 and minor number 5 */
248 #define QUP_SE_VERSION_2_5 0x20050000
249
250 /*
251 * Define bandwidth thresholds that cause the underlying Core 2X interconnect
252 * clock to run at the named frequency. These baseline values are recommended
253 * by the hardware team, and are not dynamically scaled with GENI bandwidth
254 * beyond basic on/off.
255 */
256 #define CORE_2X_19_2_MHZ 960
257 #define CORE_2X_50_MHZ 2500
258 #define CORE_2X_100_MHZ 5000
259 #define CORE_2X_150_MHZ 7500
260 #define CORE_2X_200_MHZ 10000
261 #define CORE_2X_236_MHZ 16383
262
263 #define GENI_DEFAULT_BW Bps_to_icc(1000)
264
265 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
266
267 u32 geni_se_get_qup_hw_version(struct geni_se *se);
268
269 /**
270 * geni_se_read_proto() - Read the protocol configured for a serial engine
271 * @se: Pointer to the concerned serial engine.
272 *
273 * Return: Protocol value as configured in the serial engine.
274 */
geni_se_read_proto(struct geni_se * se)275 static inline u32 geni_se_read_proto(struct geni_se *se)
276 {
277 u32 val;
278
279 val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
280
281 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
282 }
283
284 /**
285 * geni_se_setup_m_cmd() - Setup the primary sequencer
286 * @se: Pointer to the concerned serial engine.
287 * @cmd: Command/Operation to setup in the primary sequencer.
288 * @params: Parameter for the sequencer command.
289 *
290 * This function is used to configure the primary sequencer with the
291 * command and its associated parameters.
292 */
geni_se_setup_m_cmd(struct geni_se * se,u32 cmd,u32 params)293 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
294 {
295 u32 m_cmd;
296
297 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
298 writel(m_cmd, se->base + SE_GENI_M_CMD0);
299 }
300
301 /**
302 * geni_se_setup_s_cmd() - Setup the secondary sequencer
303 * @se: Pointer to the concerned serial engine.
304 * @cmd: Command/Operation to setup in the secondary sequencer.
305 * @params: Parameter for the sequencer command.
306 *
307 * This function is used to configure the secondary sequencer with the
308 * command and its associated parameters.
309 */
geni_se_setup_s_cmd(struct geni_se * se,u32 cmd,u32 params)310 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
311 {
312 u32 s_cmd;
313
314 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
315 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
316 s_cmd |= (cmd << S_OPCODE_SHFT);
317 s_cmd |= (params & S_PARAMS_MSK);
318 writel(s_cmd, se->base + SE_GENI_S_CMD0);
319 }
320
321 /**
322 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary
323 * sequencer
324 * @se: Pointer to the concerned serial engine.
325 *
326 * This function is used to cancel the currently configured command in the
327 * primary sequencer.
328 */
geni_se_cancel_m_cmd(struct geni_se * se)329 static inline void geni_se_cancel_m_cmd(struct geni_se *se)
330 {
331 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
332 }
333
334 /**
335 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
336 * sequencer
337 * @se: Pointer to the concerned serial engine.
338 *
339 * This function is used to cancel the currently configured command in the
340 * secondary sequencer.
341 */
geni_se_cancel_s_cmd(struct geni_se * se)342 static inline void geni_se_cancel_s_cmd(struct geni_se *se)
343 {
344 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
345 }
346
347 /**
348 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
349 * @se: Pointer to the concerned serial engine.
350 *
351 * This function is used to force abort the currently configured command in the
352 * primary sequencer.
353 */
geni_se_abort_m_cmd(struct geni_se * se)354 static inline void geni_se_abort_m_cmd(struct geni_se *se)
355 {
356 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
357 }
358
359 /**
360 * geni_se_abort_s_cmd() - Abort the command configured in the secondary
361 * sequencer
362 * @se: Pointer to the concerned serial engine.
363 *
364 * This function is used to force abort the currently configured command in the
365 * secondary sequencer.
366 */
geni_se_abort_s_cmd(struct geni_se * se)367 static inline void geni_se_abort_s_cmd(struct geni_se *se)
368 {
369 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
370 }
371
372 /**
373 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
374 * @se: Pointer to the concerned serial engine.
375 *
376 * This function is used to get the depth i.e. number of elements in the
377 * TX fifo of the serial engine.
378 *
379 * Return: TX fifo depth in units of FIFO words.
380 */
geni_se_get_tx_fifo_depth(struct geni_se * se)381 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
382 {
383 u32 val;
384
385 val = readl_relaxed(se->base + SE_HW_PARAM_0);
386
387 return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
388 }
389
390 /**
391 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
392 * @se: Pointer to the concerned serial engine.
393 *
394 * This function is used to get the width i.e. word size per element in the
395 * TX fifo of the serial engine.
396 *
397 * Return: TX fifo width in bits
398 */
geni_se_get_tx_fifo_width(struct geni_se * se)399 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
400 {
401 u32 val;
402
403 val = readl_relaxed(se->base + SE_HW_PARAM_0);
404
405 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
406 }
407
408 /**
409 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
410 * @se: Pointer to the concerned serial engine.
411 *
412 * This function is used to get the depth i.e. number of elements in the
413 * RX fifo of the serial engine.
414 *
415 * Return: RX fifo depth in units of FIFO words
416 */
geni_se_get_rx_fifo_depth(struct geni_se * se)417 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
418 {
419 u32 val;
420
421 val = readl_relaxed(se->base + SE_HW_PARAM_1);
422
423 return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
424 }
425
426 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
427
428 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
429
430 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
431 bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
432
433 int geni_se_resources_off(struct geni_se *se);
434
435 int geni_se_resources_on(struct geni_se *se);
436
437 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
438
439 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
440 unsigned int *index, unsigned long *res_freq,
441 bool exact);
442
443 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
444 dma_addr_t *iova);
445
446 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
447 dma_addr_t *iova);
448
449 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
450
451 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
452
453 int geni_icc_get(struct geni_se *se, const char *icc_ddr);
454
455 int geni_icc_set_bw(struct geni_se *se);
456 void geni_icc_set_tag(struct geni_se *se, u32 tag);
457
458 int geni_icc_enable(struct geni_se *se);
459
460 int geni_icc_disable(struct geni_se *se);
461 #endif
462 #endif
463