1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
5 */
6
7 #ifndef _QED_IF_H
8 #define _QED_IF_H
9
10 #include <linux/ethtool.h>
11 #include <linux/types.h>
12 #include <linux/interrupt.h>
13 #include <linux/netdevice.h>
14 #include <linux/pci.h>
15 #include <linux/skbuff.h>
16 #include <asm/byteorder.h>
17 #include <linux/io.h>
18 #include <linux/compiler.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/slab.h>
22 #include <linux/qed/common_hsi.h>
23 #include <linux/qed/qed_chain.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <net/devlink.h>
26
27 enum dcbx_protocol_type {
28 DCBX_PROTOCOL_ISCSI,
29 DCBX_PROTOCOL_FCOE,
30 DCBX_PROTOCOL_ROCE,
31 DCBX_PROTOCOL_ROCE_V2,
32 DCBX_PROTOCOL_ETH,
33 DCBX_MAX_PROTOCOL_TYPE
34 };
35
36 #define QED_ROCE_PROTOCOL_INDEX (3)
37
38 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
39 #define QED_LLDP_PORT_ID_STAT_LEN 4
40 #define QED_DCBX_MAX_APP_PROTOCOL 32
41 #define QED_MAX_PFC_PRIORITIES 8
42 #define QED_DCBX_DSCP_SIZE 64
43
44 struct qed_dcbx_lldp_remote {
45 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
46 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
47 bool enable_rx;
48 bool enable_tx;
49 u32 tx_interval;
50 u32 max_credit;
51 };
52
53 struct qed_dcbx_lldp_local {
54 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
55 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
56 };
57
58 struct qed_dcbx_app_prio {
59 u8 roce;
60 u8 roce_v2;
61 u8 fcoe;
62 u8 iscsi;
63 u8 eth;
64 };
65
66 struct qed_dbcx_pfc_params {
67 bool willing;
68 bool enabled;
69 u8 prio[QED_MAX_PFC_PRIORITIES];
70 u8 max_tc;
71 };
72
73 enum qed_dcbx_sf_ieee_type {
74 QED_DCBX_SF_IEEE_ETHTYPE,
75 QED_DCBX_SF_IEEE_TCP_PORT,
76 QED_DCBX_SF_IEEE_UDP_PORT,
77 QED_DCBX_SF_IEEE_TCP_UDP_PORT
78 };
79
80 struct qed_app_entry {
81 bool ethtype;
82 enum qed_dcbx_sf_ieee_type sf_ieee;
83 bool enabled;
84 u8 prio;
85 u16 proto_id;
86 enum dcbx_protocol_type proto_type;
87 };
88
89 struct qed_dcbx_params {
90 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
91 u16 num_app_entries;
92 bool app_willing;
93 bool app_valid;
94 bool app_error;
95 bool ets_willing;
96 bool ets_enabled;
97 bool ets_cbs;
98 bool valid;
99 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
100 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
101 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
102 struct qed_dbcx_pfc_params pfc;
103 u8 max_ets_tc;
104 };
105
106 struct qed_dcbx_admin_params {
107 struct qed_dcbx_params params;
108 bool valid;
109 };
110
111 struct qed_dcbx_remote_params {
112 struct qed_dcbx_params params;
113 bool valid;
114 };
115
116 struct qed_dcbx_operational_params {
117 struct qed_dcbx_app_prio app_prio;
118 struct qed_dcbx_params params;
119 bool valid;
120 bool enabled;
121 bool ieee;
122 bool cee;
123 bool local;
124 u32 err;
125 };
126
127 struct qed_dcbx_get {
128 struct qed_dcbx_operational_params operational;
129 struct qed_dcbx_lldp_remote lldp_remote;
130 struct qed_dcbx_lldp_local lldp_local;
131 struct qed_dcbx_remote_params remote;
132 struct qed_dcbx_admin_params local;
133 };
134
135 enum qed_nvm_images {
136 QED_NVM_IMAGE_ISCSI_CFG,
137 QED_NVM_IMAGE_FCOE_CFG,
138 QED_NVM_IMAGE_MDUMP,
139 QED_NVM_IMAGE_NVM_CFG1,
140 QED_NVM_IMAGE_DEFAULT_CFG,
141 QED_NVM_IMAGE_NVM_META,
142 };
143
144 struct qed_link_eee_params {
145 u32 tx_lpi_timer;
146 #define QED_EEE_1G_ADV BIT(0)
147 #define QED_EEE_10G_ADV BIT(1)
148
149 /* Capabilities are represented using QED_EEE_*_ADV values */
150 u8 adv_caps;
151 u8 lp_adv_caps;
152 bool enable;
153 bool tx_lpi_enable;
154 };
155
156 enum qed_led_mode {
157 QED_LED_MODE_OFF,
158 QED_LED_MODE_ON,
159 QED_LED_MODE_RESTORE
160 };
161
162 struct qed_mfw_tlv_eth {
163 u16 lso_maxoff_size;
164 bool lso_maxoff_size_set;
165 u16 lso_minseg_size;
166 bool lso_minseg_size_set;
167 u8 prom_mode;
168 bool prom_mode_set;
169 u16 tx_descr_size;
170 bool tx_descr_size_set;
171 u16 rx_descr_size;
172 bool rx_descr_size_set;
173 u16 netq_count;
174 bool netq_count_set;
175 u32 tcp4_offloads;
176 bool tcp4_offloads_set;
177 u32 tcp6_offloads;
178 bool tcp6_offloads_set;
179 u16 tx_descr_qdepth;
180 bool tx_descr_qdepth_set;
181 u16 rx_descr_qdepth;
182 bool rx_descr_qdepth_set;
183 u8 iov_offload;
184 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
185 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
186 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
187 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
188 bool iov_offload_set;
189 u8 txqs_empty;
190 bool txqs_empty_set;
191 u8 rxqs_empty;
192 bool rxqs_empty_set;
193 u8 num_txqs_full;
194 bool num_txqs_full_set;
195 u8 num_rxqs_full;
196 bool num_rxqs_full_set;
197 };
198
199 #define QED_MFW_TLV_TIME_SIZE 14
200 struct qed_mfw_tlv_time {
201 bool b_set;
202 u8 month;
203 u8 day;
204 u8 hour;
205 u8 min;
206 u16 msec;
207 u16 usec;
208 };
209
210 struct qed_mfw_tlv_fcoe {
211 u8 scsi_timeout;
212 bool scsi_timeout_set;
213 u32 rt_tov;
214 bool rt_tov_set;
215 u32 ra_tov;
216 bool ra_tov_set;
217 u32 ed_tov;
218 bool ed_tov_set;
219 u32 cr_tov;
220 bool cr_tov_set;
221 u8 boot_type;
222 bool boot_type_set;
223 u8 npiv_state;
224 bool npiv_state_set;
225 u32 num_npiv_ids;
226 bool num_npiv_ids_set;
227 u8 switch_name[8];
228 bool switch_name_set;
229 u16 switch_portnum;
230 bool switch_portnum_set;
231 u8 switch_portid[3];
232 bool switch_portid_set;
233 u8 vendor_name[8];
234 bool vendor_name_set;
235 u8 switch_model[8];
236 bool switch_model_set;
237 u8 switch_fw_version[8];
238 bool switch_fw_version_set;
239 u8 qos_pri;
240 bool qos_pri_set;
241 u8 port_alias[3];
242 bool port_alias_set;
243 u8 port_state;
244 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
245 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
246 #define QED_MFW_TLV_PORT_STATE_P2P (2)
247 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
248 bool port_state_set;
249 u16 fip_tx_descr_size;
250 bool fip_tx_descr_size_set;
251 u16 fip_rx_descr_size;
252 bool fip_rx_descr_size_set;
253 u16 link_failures;
254 bool link_failures_set;
255 u8 fcoe_boot_progress;
256 bool fcoe_boot_progress_set;
257 u64 rx_bcast;
258 bool rx_bcast_set;
259 u64 tx_bcast;
260 bool tx_bcast_set;
261 u16 fcoe_txq_depth;
262 bool fcoe_txq_depth_set;
263 u16 fcoe_rxq_depth;
264 bool fcoe_rxq_depth_set;
265 u64 fcoe_rx_frames;
266 bool fcoe_rx_frames_set;
267 u64 fcoe_rx_bytes;
268 bool fcoe_rx_bytes_set;
269 u64 fcoe_tx_frames;
270 bool fcoe_tx_frames_set;
271 u64 fcoe_tx_bytes;
272 bool fcoe_tx_bytes_set;
273 u16 crc_count;
274 bool crc_count_set;
275 u32 crc_err_src_fcid[5];
276 bool crc_err_src_fcid_set[5];
277 struct qed_mfw_tlv_time crc_err[5];
278 u16 losync_err;
279 bool losync_err_set;
280 u16 losig_err;
281 bool losig_err_set;
282 u16 primtive_err;
283 bool primtive_err_set;
284 u16 disparity_err;
285 bool disparity_err_set;
286 u16 code_violation_err;
287 bool code_violation_err_set;
288 u32 flogi_param[4];
289 bool flogi_param_set[4];
290 struct qed_mfw_tlv_time flogi_tstamp;
291 u32 flogi_acc_param[4];
292 bool flogi_acc_param_set[4];
293 struct qed_mfw_tlv_time flogi_acc_tstamp;
294 u32 flogi_rjt;
295 bool flogi_rjt_set;
296 struct qed_mfw_tlv_time flogi_rjt_tstamp;
297 u32 fdiscs;
298 bool fdiscs_set;
299 u8 fdisc_acc;
300 bool fdisc_acc_set;
301 u8 fdisc_rjt;
302 bool fdisc_rjt_set;
303 u8 plogi;
304 bool plogi_set;
305 u8 plogi_acc;
306 bool plogi_acc_set;
307 u8 plogi_rjt;
308 bool plogi_rjt_set;
309 u32 plogi_dst_fcid[5];
310 bool plogi_dst_fcid_set[5];
311 struct qed_mfw_tlv_time plogi_tstamp[5];
312 u32 plogi_acc_src_fcid[5];
313 bool plogi_acc_src_fcid_set[5];
314 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
315 u8 tx_plogos;
316 bool tx_plogos_set;
317 u8 plogo_acc;
318 bool plogo_acc_set;
319 u8 plogo_rjt;
320 bool plogo_rjt_set;
321 u32 plogo_src_fcid[5];
322 bool plogo_src_fcid_set[5];
323 struct qed_mfw_tlv_time plogo_tstamp[5];
324 u8 rx_logos;
325 bool rx_logos_set;
326 u8 tx_accs;
327 bool tx_accs_set;
328 u8 tx_prlis;
329 bool tx_prlis_set;
330 u8 rx_accs;
331 bool rx_accs_set;
332 u8 tx_abts;
333 bool tx_abts_set;
334 u8 rx_abts_acc;
335 bool rx_abts_acc_set;
336 u8 rx_abts_rjt;
337 bool rx_abts_rjt_set;
338 u32 abts_dst_fcid[5];
339 bool abts_dst_fcid_set[5];
340 struct qed_mfw_tlv_time abts_tstamp[5];
341 u8 rx_rscn;
342 bool rx_rscn_set;
343 u32 rx_rscn_nport[4];
344 bool rx_rscn_nport_set[4];
345 u8 tx_lun_rst;
346 bool tx_lun_rst_set;
347 u8 abort_task_sets;
348 bool abort_task_sets_set;
349 u8 tx_tprlos;
350 bool tx_tprlos_set;
351 u8 tx_nos;
352 bool tx_nos_set;
353 u8 rx_nos;
354 bool rx_nos_set;
355 u8 ols;
356 bool ols_set;
357 u8 lr;
358 bool lr_set;
359 u8 lrr;
360 bool lrr_set;
361 u8 tx_lip;
362 bool tx_lip_set;
363 u8 rx_lip;
364 bool rx_lip_set;
365 u8 eofa;
366 bool eofa_set;
367 u8 eofni;
368 bool eofni_set;
369 u8 scsi_chks;
370 bool scsi_chks_set;
371 u8 scsi_cond_met;
372 bool scsi_cond_met_set;
373 u8 scsi_busy;
374 bool scsi_busy_set;
375 u8 scsi_inter;
376 bool scsi_inter_set;
377 u8 scsi_inter_cond_met;
378 bool scsi_inter_cond_met_set;
379 u8 scsi_rsv_conflicts;
380 bool scsi_rsv_conflicts_set;
381 u8 scsi_tsk_full;
382 bool scsi_tsk_full_set;
383 u8 scsi_aca_active;
384 bool scsi_aca_active_set;
385 u8 scsi_tsk_abort;
386 bool scsi_tsk_abort_set;
387 u32 scsi_rx_chk[5];
388 bool scsi_rx_chk_set[5];
389 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
390 };
391
392 struct qed_mfw_tlv_iscsi {
393 u8 target_llmnr;
394 bool target_llmnr_set;
395 u8 header_digest;
396 bool header_digest_set;
397 u8 data_digest;
398 bool data_digest_set;
399 u8 auth_method;
400 #define QED_MFW_TLV_AUTH_METHOD_NONE (1)
401 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
402 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
403 bool auth_method_set;
404 u16 boot_taget_portal;
405 bool boot_taget_portal_set;
406 u16 frame_size;
407 bool frame_size_set;
408 u16 tx_desc_size;
409 bool tx_desc_size_set;
410 u16 rx_desc_size;
411 bool rx_desc_size_set;
412 u8 boot_progress;
413 bool boot_progress_set;
414 u16 tx_desc_qdepth;
415 bool tx_desc_qdepth_set;
416 u16 rx_desc_qdepth;
417 bool rx_desc_qdepth_set;
418 u64 rx_frames;
419 bool rx_frames_set;
420 u64 rx_bytes;
421 bool rx_bytes_set;
422 u64 tx_frames;
423 bool tx_frames_set;
424 u64 tx_bytes;
425 bool tx_bytes_set;
426 };
427
428 enum qed_db_rec_width {
429 DB_REC_WIDTH_32B,
430 DB_REC_WIDTH_64B,
431 };
432
433 enum qed_db_rec_space {
434 DB_REC_KERNEL,
435 DB_REC_USER,
436 };
437
438 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
439 (void __iomem *)(reg_addr))
440
441 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
442
443 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \
444 (void __iomem *)(reg_addr))
445
446 #define QED_COALESCE_MAX 0x1FF
447 #define QED_DEFAULT_RX_USECS 12
448 #define QED_DEFAULT_TX_USECS 48
449
450 /* forward */
451 struct qed_dev;
452
453 struct qed_eth_pf_params {
454 /* The following parameters are used during HW-init
455 * and these parameters need to be passed as arguments
456 * to update_pf_params routine invoked before slowpath start
457 */
458 u16 num_cons;
459
460 /* per-VF number of CIDs */
461 u8 num_vf_cons;
462 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
463
464 /* To enable arfs, previous to HW-init a positive number needs to be
465 * set [as filters require allocated searcher ILT memory].
466 * This will set the maximal number of configured steering-filters.
467 */
468 u32 num_arfs_filters;
469 };
470
471 struct qed_fcoe_pf_params {
472 /* The following parameters are used during protocol-init */
473 u64 glbl_q_params_addr;
474 u64 bdq_pbl_base_addr[2];
475
476 /* The following parameters are used during HW-init
477 * and these parameters need to be passed as arguments
478 * to update_pf_params routine invoked before slowpath start
479 */
480 u16 num_cons;
481 u16 num_tasks;
482
483 /* The following parameters are used during protocol-init */
484 u16 sq_num_pbl_pages;
485
486 u16 cq_num_entries;
487 u16 cmdq_num_entries;
488 u16 rq_buffer_log_size;
489 u16 mtu;
490 u16 dummy_icid;
491 u16 bdq_xoff_threshold[2];
492 u16 bdq_xon_threshold[2];
493 u16 rq_buffer_size;
494 u8 num_cqs; /* num of global CQs */
495 u8 log_page_size;
496 u8 gl_rq_pi;
497 u8 gl_cmd_pi;
498 u8 debug_mode;
499 u8 is_target;
500 u8 bdq_pbl_num_entries[2];
501 };
502
503 /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
504 struct qed_iscsi_pf_params {
505 u64 glbl_q_params_addr;
506 u64 bdq_pbl_base_addr[3];
507 u16 cq_num_entries;
508 u16 cmdq_num_entries;
509 u32 two_msl_timer;
510 u16 tx_sws_timer;
511
512 /* The following parameters are used during HW-init
513 * and these parameters need to be passed as arguments
514 * to update_pf_params routine invoked before slowpath start
515 */
516 u16 num_cons;
517 u16 num_tasks;
518
519 /* The following parameters are used during protocol-init */
520 u16 half_way_close_timeout;
521 u16 bdq_xoff_threshold[3];
522 u16 bdq_xon_threshold[3];
523 u16 cmdq_xoff_threshold;
524 u16 cmdq_xon_threshold;
525 u16 rq_buffer_size;
526
527 u8 num_sq_pages_in_ring;
528 u8 num_r2tq_pages_in_ring;
529 u8 num_uhq_pages_in_ring;
530 u8 num_queues;
531 u8 log_page_size;
532 u8 rqe_log_size;
533 u8 max_fin_rt;
534 u8 gl_rq_pi;
535 u8 gl_cmd_pi;
536 u8 debug_mode;
537 u8 ll2_ooo_queue_id;
538
539 u8 is_target;
540 u8 is_soc_en;
541 u8 soc_num_of_blocks_log;
542 u8 bdq_pbl_num_entries[3];
543 };
544
545 struct qed_rdma_pf_params {
546 /* Supplied to QED during resource allocation (may affect the ILT and
547 * the doorbell BAR).
548 */
549 u32 min_dpis; /* number of requested DPIs */
550 u32 num_qps; /* number of requested Queue Pairs */
551 u32 num_srqs; /* number of requested SRQ */
552 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
553 u8 gl_pi; /* protocol index */
554
555 /* Will allocate rate limiters to be used with QPs */
556 u8 enable_dcqcn;
557 };
558
559 struct qed_pf_params {
560 struct qed_eth_pf_params eth_pf_params;
561 struct qed_fcoe_pf_params fcoe_pf_params;
562 struct qed_iscsi_pf_params iscsi_pf_params;
563 struct qed_rdma_pf_params rdma_pf_params;
564 };
565
566 enum qed_int_mode {
567 QED_INT_MODE_INTA,
568 QED_INT_MODE_MSIX,
569 QED_INT_MODE_MSI,
570 QED_INT_MODE_POLL,
571 };
572
573 struct qed_sb_info {
574 struct status_block_e4 *sb_virt;
575 dma_addr_t sb_phys;
576 u32 sb_ack; /* Last given ack */
577 u16 igu_sb_id;
578 void __iomem *igu_addr;
579 u8 flags;
580 #define QED_SB_INFO_INIT 0x1
581 #define QED_SB_INFO_SETUP 0x2
582
583 struct qed_dev *cdev;
584 };
585
586 enum qed_hw_err_type {
587 QED_HW_ERR_FAN_FAIL,
588 QED_HW_ERR_MFW_RESP_FAIL,
589 QED_HW_ERR_HW_ATTN,
590 QED_HW_ERR_DMAE_FAIL,
591 QED_HW_ERR_RAMROD_FAIL,
592 QED_HW_ERR_FW_ASSERT,
593 QED_HW_ERR_LAST,
594 };
595
596 enum qed_dev_type {
597 QED_DEV_TYPE_BB,
598 QED_DEV_TYPE_AH,
599 QED_DEV_TYPE_E5,
600 };
601
602 struct qed_dev_info {
603 unsigned long pci_mem_start;
604 unsigned long pci_mem_end;
605 unsigned int pci_irq;
606 u8 num_hwfns;
607
608 u8 hw_mac[ETH_ALEN];
609
610 /* FW version */
611 u16 fw_major;
612 u16 fw_minor;
613 u16 fw_rev;
614 u16 fw_eng;
615
616 /* MFW version */
617 u32 mfw_rev;
618 #define QED_MFW_VERSION_0_MASK 0x000000FF
619 #define QED_MFW_VERSION_0_OFFSET 0
620 #define QED_MFW_VERSION_1_MASK 0x0000FF00
621 #define QED_MFW_VERSION_1_OFFSET 8
622 #define QED_MFW_VERSION_2_MASK 0x00FF0000
623 #define QED_MFW_VERSION_2_OFFSET 16
624 #define QED_MFW_VERSION_3_MASK 0xFF000000
625 #define QED_MFW_VERSION_3_OFFSET 24
626
627 u32 flash_size;
628 bool b_arfs_capable;
629 bool b_inter_pf_switch;
630 bool tx_switching;
631 bool rdma_supported;
632 u16 mtu;
633
634 bool wol_support;
635 bool smart_an;
636
637 /* MBI version */
638 u32 mbi_version;
639 #define QED_MBI_VERSION_0_MASK 0x000000FF
640 #define QED_MBI_VERSION_0_OFFSET 0
641 #define QED_MBI_VERSION_1_MASK 0x0000FF00
642 #define QED_MBI_VERSION_1_OFFSET 8
643 #define QED_MBI_VERSION_2_MASK 0x00FF0000
644 #define QED_MBI_VERSION_2_OFFSET 16
645
646 enum qed_dev_type dev_type;
647
648 /* Output parameters for qede */
649 bool vxlan_enable;
650 bool gre_enable;
651 bool geneve_enable;
652
653 u8 abs_pf_id;
654 };
655
656 enum qed_sb_type {
657 QED_SB_TYPE_L2_QUEUE,
658 QED_SB_TYPE_CNQ,
659 QED_SB_TYPE_STORAGE,
660 };
661
662 enum qed_protocol {
663 QED_PROTOCOL_ETH,
664 QED_PROTOCOL_ISCSI,
665 QED_PROTOCOL_FCOE,
666 };
667
668 enum qed_fec_mode {
669 QED_FEC_MODE_NONE = BIT(0),
670 QED_FEC_MODE_FIRECODE = BIT(1),
671 QED_FEC_MODE_RS = BIT(2),
672 QED_FEC_MODE_AUTO = BIT(3),
673 QED_FEC_MODE_UNSUPPORTED = BIT(4),
674 };
675
676 struct qed_link_params {
677 bool link_up;
678
679 u32 override_flags;
680 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
681 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
682 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
683 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
684 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
685 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
686 #define QED_LINK_OVERRIDE_FEC_CONFIG BIT(6)
687
688 bool autoneg;
689 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
690 u32 forced_speed;
691
692 u32 pause_config;
693 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
694 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
695 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
696
697 u32 loopback_mode;
698 #define QED_LINK_LOOPBACK_NONE BIT(0)
699 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
700 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
701 #define QED_LINK_LOOPBACK_EXT BIT(3)
702 #define QED_LINK_LOOPBACK_MAC BIT(4)
703 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123 BIT(5)
704 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301 BIT(6)
705 #define QED_LINK_LOOPBACK_PCS_AH_ONLY BIT(7)
706 #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY BIT(8)
707 #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY BIT(9)
708
709 struct qed_link_eee_params eee;
710 u32 fec;
711 };
712
713 struct qed_link_output {
714 bool link_up;
715
716 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
717 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
718 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
719
720 u32 speed; /* In Mb/s */
721 u8 duplex; /* In DUPLEX defs */
722 u8 port; /* In PORT defs */
723 bool autoneg;
724 u32 pause_config;
725
726 /* EEE - capability & param */
727 bool eee_supported;
728 bool eee_active;
729 u8 sup_caps;
730 struct qed_link_eee_params eee;
731
732 u32 sup_fec;
733 u32 active_fec;
734 };
735
736 struct qed_probe_params {
737 enum qed_protocol protocol;
738 u32 dp_module;
739 u8 dp_level;
740 bool is_vf;
741 bool recov_in_prog;
742 };
743
744 #define QED_DRV_VER_STR_SIZE 12
745 struct qed_slowpath_params {
746 u32 int_mode;
747 u8 drv_major;
748 u8 drv_minor;
749 u8 drv_rev;
750 u8 drv_eng;
751 u8 name[QED_DRV_VER_STR_SIZE];
752 };
753
754 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
755
756 struct qed_int_info {
757 struct msix_entry *msix;
758 u8 msix_cnt;
759
760 /* This should be updated by the protocol driver */
761 u8 used_cnt;
762 };
763
764 struct qed_generic_tlvs {
765 #define QED_TLV_IP_CSUM BIT(0)
766 #define QED_TLV_LSO BIT(1)
767 u16 feat_flags;
768 #define QED_TLV_MAC_COUNT 3
769 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
770 };
771
772 #define QED_I2C_DEV_ADDR_A0 0xA0
773 #define QED_I2C_DEV_ADDR_A2 0xA2
774
775 #define QED_NVM_SIGNATURE 0x12435687
776
777 enum qed_nvm_flash_cmd {
778 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
779 QED_NVM_FLASH_CMD_FILE_START = 0x3,
780 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
781 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
782 QED_NVM_FLASH_CMD_NVM_MAX,
783 };
784
785 struct qed_devlink {
786 struct qed_dev *cdev;
787 struct devlink_health_reporter *fw_reporter;
788 };
789
790 struct qed_common_cb_ops {
791 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
792 void (*link_update)(void *dev, struct qed_link_output *link);
793 void (*schedule_recovery_handler)(void *dev);
794 void (*schedule_hw_err_handler)(void *dev,
795 enum qed_hw_err_type err_type);
796 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
797 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
798 void (*get_protocol_tlv_data)(void *dev, void *data);
799 void (*bw_update)(void *dev);
800 };
801
802 struct qed_selftest_ops {
803 /**
804 * @brief selftest_interrupt - Perform interrupt test
805 *
806 * @param cdev
807 *
808 * @return 0 on success, error otherwise.
809 */
810 int (*selftest_interrupt)(struct qed_dev *cdev);
811
812 /**
813 * @brief selftest_memory - Perform memory test
814 *
815 * @param cdev
816 *
817 * @return 0 on success, error otherwise.
818 */
819 int (*selftest_memory)(struct qed_dev *cdev);
820
821 /**
822 * @brief selftest_register - Perform register test
823 *
824 * @param cdev
825 *
826 * @return 0 on success, error otherwise.
827 */
828 int (*selftest_register)(struct qed_dev *cdev);
829
830 /**
831 * @brief selftest_clock - Perform clock test
832 *
833 * @param cdev
834 *
835 * @return 0 on success, error otherwise.
836 */
837 int (*selftest_clock)(struct qed_dev *cdev);
838
839 /**
840 * @brief selftest_nvram - Perform nvram test
841 *
842 * @param cdev
843 *
844 * @return 0 on success, error otherwise.
845 */
846 int (*selftest_nvram) (struct qed_dev *cdev);
847 };
848
849 struct qed_common_ops {
850 struct qed_selftest_ops *selftest;
851
852 struct qed_dev* (*probe)(struct pci_dev *dev,
853 struct qed_probe_params *params);
854
855 void (*remove)(struct qed_dev *cdev);
856
857 int (*set_power_state)(struct qed_dev *cdev, pci_power_t state);
858
859 void (*set_name) (struct qed_dev *cdev, char name[]);
860
861 /* Client drivers need to make this call before slowpath_start.
862 * PF params required for the call before slowpath_start is
863 * documented within the qed_pf_params structure definition.
864 */
865 void (*update_pf_params)(struct qed_dev *cdev,
866 struct qed_pf_params *params);
867
868 int (*slowpath_start)(struct qed_dev *cdev,
869 struct qed_slowpath_params *params);
870
871 int (*slowpath_stop)(struct qed_dev *cdev);
872
873 /* Requests to use `cnt' interrupts for fastpath.
874 * upon success, returns number of interrupts allocated for fastpath.
875 */
876 int (*set_fp_int)(struct qed_dev *cdev, u16 cnt);
877
878 /* Fills `info' with pointers required for utilizing interrupts */
879 int (*get_fp_int)(struct qed_dev *cdev, struct qed_int_info *info);
880
881 u32 (*sb_init)(struct qed_dev *cdev,
882 struct qed_sb_info *sb_info,
883 void *sb_virt_addr,
884 dma_addr_t sb_phy_addr,
885 u16 sb_id,
886 enum qed_sb_type type);
887
888 u32 (*sb_release)(struct qed_dev *cdev,
889 struct qed_sb_info *sb_info,
890 u16 sb_id,
891 enum qed_sb_type type);
892
893 void (*simd_handler_config)(struct qed_dev *cdev,
894 void *token,
895 int index,
896 void (*handler)(void *));
897
898 void (*simd_handler_clean)(struct qed_dev *cdev, int index);
899
900 int (*dbg_grc)(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
901
902 int (*dbg_grc_size)(struct qed_dev *cdev);
903
904 int (*dbg_all_data)(struct qed_dev *cdev, void *buffer);
905
906 int (*dbg_all_data_size)(struct qed_dev *cdev);
907
908 int (*report_fatal_error)(struct devlink *devlink,
909 enum qed_hw_err_type err_type);
910
911 /**
912 * @brief can_link_change - can the instance change the link or not
913 *
914 * @param cdev
915 *
916 * @return true if link-change is allowed, false otherwise.
917 */
918 bool (*can_link_change)(struct qed_dev *cdev);
919
920 /**
921 * @brief set_link - set links according to params
922 *
923 * @param cdev
924 * @param params - values used to override the default link configuration
925 *
926 * @return 0 on success, error otherwise.
927 */
928 int (*set_link)(struct qed_dev *cdev,
929 struct qed_link_params *params);
930
931 /**
932 * @brief get_link - returns the current link state.
933 *
934 * @param cdev
935 * @param if_link - structure to be filled with current link configuration.
936 */
937 void (*get_link)(struct qed_dev *cdev,
938 struct qed_link_output *if_link);
939
940 /**
941 * @brief - drains chip in case Tx completions fail to arrive due to pause.
942 *
943 * @param cdev
944 */
945 int (*drain)(struct qed_dev *cdev);
946
947 /**
948 * @brief update_msglvl - update module debug level
949 *
950 * @param cdev
951 * @param dp_module
952 * @param dp_level
953 */
954 void (*update_msglvl)(struct qed_dev *cdev,
955 u32 dp_module,
956 u8 dp_level);
957
958 int (*chain_alloc)(struct qed_dev *cdev,
959 struct qed_chain *chain,
960 struct qed_chain_init_params *params);
961
962 void (*chain_free)(struct qed_dev *cdev,
963 struct qed_chain *p_chain);
964
965 /**
966 * @brief nvm_flash - Flash nvm data.
967 *
968 * @param cdev
969 * @param name - file containing the data
970 *
971 * @return 0 on success, error otherwise.
972 */
973 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
974
975 /**
976 * @brief nvm_get_image - reads an entire image from nvram
977 *
978 * @param cdev
979 * @param type - type of the request nvram image
980 * @param buf - preallocated buffer to fill with the image
981 * @param len - length of the allocated buffer
982 *
983 * @return 0 on success, error otherwise
984 */
985 int (*nvm_get_image)(struct qed_dev *cdev,
986 enum qed_nvm_images type, u8 *buf, u16 len);
987
988 /**
989 * @brief set_coalesce - Configure Rx coalesce value in usec
990 *
991 * @param cdev
992 * @param rx_coal - Rx coalesce value in usec
993 * @param tx_coal - Tx coalesce value in usec
994 * @param qid - Queue index
995 * @param sb_id - Status Block Id
996 *
997 * @return 0 on success, error otherwise.
998 */
999 int (*set_coalesce)(struct qed_dev *cdev,
1000 u16 rx_coal, u16 tx_coal, void *handle);
1001
1002 /**
1003 * @brief set_led - Configure LED mode
1004 *
1005 * @param cdev
1006 * @param mode - LED mode
1007 *
1008 * @return 0 on success, error otherwise.
1009 */
1010 int (*set_led)(struct qed_dev *cdev,
1011 enum qed_led_mode mode);
1012
1013 /**
1014 * @brief attn_clr_enable - Prevent attentions from being reasserted
1015 *
1016 * @param cdev
1017 * @param clr_enable
1018 */
1019 void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1020
1021 /**
1022 * @brief db_recovery_add - add doorbell information to the doorbell
1023 * recovery mechanism.
1024 *
1025 * @param cdev
1026 * @param db_addr - doorbell address
1027 * @param db_data - address of where db_data is stored
1028 * @param db_is_32b - doorbell is 32b pr 64b
1029 * @param db_is_user - doorbell recovery addresses are user or kernel space
1030 */
1031 int (*db_recovery_add)(struct qed_dev *cdev,
1032 void __iomem *db_addr,
1033 void *db_data,
1034 enum qed_db_rec_width db_width,
1035 enum qed_db_rec_space db_space);
1036
1037 /**
1038 * @brief db_recovery_del - remove doorbell information from the doorbell
1039 * recovery mechanism. db_data serves as key (db_addr is not unique).
1040 *
1041 * @param cdev
1042 * @param db_addr - doorbell address
1043 * @param db_data - address where db_data is stored. Serves as key for the
1044 * entry to delete.
1045 */
1046 int (*db_recovery_del)(struct qed_dev *cdev,
1047 void __iomem *db_addr, void *db_data);
1048
1049 /**
1050 * @brief recovery_process - Trigger a recovery process
1051 *
1052 * @param cdev
1053 *
1054 * @return 0 on success, error otherwise.
1055 */
1056 int (*recovery_process)(struct qed_dev *cdev);
1057
1058 /**
1059 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1060 *
1061 * @param cdev
1062 *
1063 * @return 0 on success, error otherwise.
1064 */
1065 int (*recovery_prolog)(struct qed_dev *cdev);
1066
1067 /**
1068 * @brief update_drv_state - API to inform the change in the driver state.
1069 *
1070 * @param cdev
1071 * @param active
1072 *
1073 */
1074 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1075
1076 /**
1077 * @brief update_mac - API to inform the change in the mac address
1078 *
1079 * @param cdev
1080 * @param mac
1081 *
1082 */
1083 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1084
1085 /**
1086 * @brief update_mtu - API to inform the change in the mtu
1087 *
1088 * @param cdev
1089 * @param mtu
1090 *
1091 */
1092 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1093
1094 /**
1095 * @brief update_wol - update of changes in the WoL configuration
1096 *
1097 * @param cdev
1098 * @param enabled - true iff WoL should be enabled.
1099 */
1100 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1101
1102 /**
1103 * @brief read_module_eeprom
1104 *
1105 * @param cdev
1106 * @param buf - buffer
1107 * @param dev_addr - PHY device memory region
1108 * @param offset - offset into eeprom contents to be read
1109 * @param len - buffer length, i.e., max bytes to be read
1110 */
1111 int (*read_module_eeprom)(struct qed_dev *cdev,
1112 char *buf, u8 dev_addr, u32 offset, u32 len);
1113
1114 /**
1115 * @brief get_affin_hwfn_idx
1116 *
1117 * @param cdev
1118 */
1119 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1120
1121 /**
1122 * @brief read_nvm_cfg - Read NVM config attribute value.
1123 * @param cdev
1124 * @param buf - buffer
1125 * @param cmd - NVM CFG command id
1126 * @param entity_id - Entity id
1127 *
1128 */
1129 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1130 u32 entity_id);
1131 /**
1132 * @brief read_nvm_cfg - Read NVM config attribute value.
1133 * @param cdev
1134 * @param cmd - NVM CFG command id
1135 *
1136 * @return config id length, 0 on error.
1137 */
1138 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1139
1140 /**
1141 * @brief set_grc_config - Configure value for grc config id.
1142 * @param cdev
1143 * @param cfg_id - grc config id
1144 * @param val - grc config value
1145 *
1146 */
1147 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1148
1149 struct devlink* (*devlink_register)(struct qed_dev *cdev);
1150
1151 void (*devlink_unregister)(struct devlink *devlink);
1152 };
1153
1154 #define MASK_FIELD(_name, _value) \
1155 ((_value) &= (_name ## _MASK))
1156
1157 #define FIELD_VALUE(_name, _value) \
1158 ((_value & _name ## _MASK) << _name ## _SHIFT)
1159
1160 #define SET_FIELD(value, name, flag) \
1161 do { \
1162 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1163 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1164 } while (0)
1165
1166 #define GET_FIELD(value, name) \
1167 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1168
1169 #define GET_MFW_FIELD(name, field) \
1170 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
1171
1172 #define SET_MFW_FIELD(name, field, value) \
1173 do { \
1174 (name) &= ~(field ## _MASK); \
1175 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1176 } while (0)
1177
1178 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1179
1180 /* Debug print definitions */
1181 #define DP_ERR(cdev, fmt, ...) \
1182 do { \
1183 pr_err("[%s:%d(%s)]" fmt, \
1184 __func__, __LINE__, \
1185 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1186 ## __VA_ARGS__); \
1187 } while (0)
1188
1189 #define DP_NOTICE(cdev, fmt, ...) \
1190 do { \
1191 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1192 pr_notice("[%s:%d(%s)]" fmt, \
1193 __func__, __LINE__, \
1194 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1195 ## __VA_ARGS__); \
1196 \
1197 } \
1198 } while (0)
1199
1200 #define DP_INFO(cdev, fmt, ...) \
1201 do { \
1202 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1203 pr_notice("[%s:%d(%s)]" fmt, \
1204 __func__, __LINE__, \
1205 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1206 ## __VA_ARGS__); \
1207 } \
1208 } while (0)
1209
1210 #define DP_VERBOSE(cdev, module, fmt, ...) \
1211 do { \
1212 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1213 ((cdev)->dp_module & module))) { \
1214 pr_notice("[%s:%d(%s)]" fmt, \
1215 __func__, __LINE__, \
1216 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1217 ## __VA_ARGS__); \
1218 } \
1219 } while (0)
1220
1221 enum DP_LEVEL {
1222 QED_LEVEL_VERBOSE = 0x0,
1223 QED_LEVEL_INFO = 0x1,
1224 QED_LEVEL_NOTICE = 0x2,
1225 QED_LEVEL_ERR = 0x3,
1226 };
1227
1228 #define QED_LOG_LEVEL_SHIFT (30)
1229 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1230 #define QED_LOG_INFO_MASK (0x40000000)
1231 #define QED_LOG_NOTICE_MASK (0x80000000)
1232
1233 enum DP_MODULE {
1234 QED_MSG_SPQ = 0x10000,
1235 QED_MSG_STATS = 0x20000,
1236 QED_MSG_DCB = 0x40000,
1237 QED_MSG_IOV = 0x80000,
1238 QED_MSG_SP = 0x100000,
1239 QED_MSG_STORAGE = 0x200000,
1240 QED_MSG_CXT = 0x800000,
1241 QED_MSG_LL2 = 0x1000000,
1242 QED_MSG_ILT = 0x2000000,
1243 QED_MSG_RDMA = 0x4000000,
1244 QED_MSG_DEBUG = 0x8000000,
1245 /* to be added...up to 0x8000000 */
1246 };
1247
1248 enum qed_mf_mode {
1249 QED_MF_DEFAULT,
1250 QED_MF_OVLAN,
1251 QED_MF_NPAR,
1252 };
1253
1254 struct qed_eth_stats_common {
1255 u64 no_buff_discards;
1256 u64 packet_too_big_discard;
1257 u64 ttl0_discard;
1258 u64 rx_ucast_bytes;
1259 u64 rx_mcast_bytes;
1260 u64 rx_bcast_bytes;
1261 u64 rx_ucast_pkts;
1262 u64 rx_mcast_pkts;
1263 u64 rx_bcast_pkts;
1264 u64 mftag_filter_discards;
1265 u64 mac_filter_discards;
1266 u64 gft_filter_drop;
1267 u64 tx_ucast_bytes;
1268 u64 tx_mcast_bytes;
1269 u64 tx_bcast_bytes;
1270 u64 tx_ucast_pkts;
1271 u64 tx_mcast_pkts;
1272 u64 tx_bcast_pkts;
1273 u64 tx_err_drop_pkts;
1274 u64 tpa_coalesced_pkts;
1275 u64 tpa_coalesced_events;
1276 u64 tpa_aborts_num;
1277 u64 tpa_not_coalesced_pkts;
1278 u64 tpa_coalesced_bytes;
1279
1280 /* port */
1281 u64 rx_64_byte_packets;
1282 u64 rx_65_to_127_byte_packets;
1283 u64 rx_128_to_255_byte_packets;
1284 u64 rx_256_to_511_byte_packets;
1285 u64 rx_512_to_1023_byte_packets;
1286 u64 rx_1024_to_1518_byte_packets;
1287 u64 rx_crc_errors;
1288 u64 rx_mac_crtl_frames;
1289 u64 rx_pause_frames;
1290 u64 rx_pfc_frames;
1291 u64 rx_align_errors;
1292 u64 rx_carrier_errors;
1293 u64 rx_oversize_packets;
1294 u64 rx_jabbers;
1295 u64 rx_undersize_packets;
1296 u64 rx_fragments;
1297 u64 tx_64_byte_packets;
1298 u64 tx_65_to_127_byte_packets;
1299 u64 tx_128_to_255_byte_packets;
1300 u64 tx_256_to_511_byte_packets;
1301 u64 tx_512_to_1023_byte_packets;
1302 u64 tx_1024_to_1518_byte_packets;
1303 u64 tx_pause_frames;
1304 u64 tx_pfc_frames;
1305 u64 brb_truncates;
1306 u64 brb_discards;
1307 u64 rx_mac_bytes;
1308 u64 rx_mac_uc_packets;
1309 u64 rx_mac_mc_packets;
1310 u64 rx_mac_bc_packets;
1311 u64 rx_mac_frames_ok;
1312 u64 tx_mac_bytes;
1313 u64 tx_mac_uc_packets;
1314 u64 tx_mac_mc_packets;
1315 u64 tx_mac_bc_packets;
1316 u64 tx_mac_ctrl_frames;
1317 u64 link_change_count;
1318 };
1319
1320 struct qed_eth_stats_bb {
1321 u64 rx_1519_to_1522_byte_packets;
1322 u64 rx_1519_to_2047_byte_packets;
1323 u64 rx_2048_to_4095_byte_packets;
1324 u64 rx_4096_to_9216_byte_packets;
1325 u64 rx_9217_to_16383_byte_packets;
1326 u64 tx_1519_to_2047_byte_packets;
1327 u64 tx_2048_to_4095_byte_packets;
1328 u64 tx_4096_to_9216_byte_packets;
1329 u64 tx_9217_to_16383_byte_packets;
1330 u64 tx_lpi_entry_count;
1331 u64 tx_total_collisions;
1332 };
1333
1334 struct qed_eth_stats_ah {
1335 u64 rx_1519_to_max_byte_packets;
1336 u64 tx_1519_to_max_byte_packets;
1337 };
1338
1339 struct qed_eth_stats {
1340 struct qed_eth_stats_common common;
1341
1342 union {
1343 struct qed_eth_stats_bb bb;
1344 struct qed_eth_stats_ah ah;
1345 };
1346 };
1347
1348 #define QED_SB_IDX 0x0002
1349
1350 #define RX_PI 0
1351 #define TX_PI(tc) (RX_PI + 1 + tc)
1352
1353 struct qed_sb_cnt_info {
1354 /* Original, current, and free SBs for PF */
1355 int orig;
1356 int cnt;
1357 int free_cnt;
1358
1359 /* Original, current and free SBS for child VFs */
1360 int iov_orig;
1361 int iov_cnt;
1362 int free_cnt_iov;
1363 };
1364
qed_sb_update_sb_idx(struct qed_sb_info * sb_info)1365 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1366 {
1367 u32 prod = 0;
1368 u16 rc = 0;
1369
1370 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1371 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1372 if (sb_info->sb_ack != prod) {
1373 sb_info->sb_ack = prod;
1374 rc |= QED_SB_IDX;
1375 }
1376
1377 /* Let SB update */
1378 return rc;
1379 }
1380
1381 /**
1382 *
1383 * @brief This function creates an update command for interrupts that is
1384 * written to the IGU.
1385 *
1386 * @param sb_info - This is the structure allocated and
1387 * initialized per status block. Assumption is
1388 * that it was initialized using qed_sb_init
1389 * @param int_cmd - Enable/Disable/Nop
1390 * @param upd_flg - whether igu consumer should be
1391 * updated.
1392 *
1393 * @return inline void
1394 */
qed_sb_ack(struct qed_sb_info * sb_info,enum igu_int_cmd int_cmd,u8 upd_flg)1395 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1396 enum igu_int_cmd int_cmd,
1397 u8 upd_flg)
1398 {
1399 u32 igu_ack;
1400
1401 igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1402 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1403 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1404 (IGU_SEG_ACCESS_REG <<
1405 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1406
1407 DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1408
1409 /* Both segments (interrupts & acks) are written to same place address;
1410 * Need to guarantee all commands will be received (in-order) by HW.
1411 */
1412 barrier();
1413 }
1414
__internal_ram_wr(void * p_hwfn,void __iomem * addr,int size,u32 * data)1415 static inline void __internal_ram_wr(void *p_hwfn,
1416 void __iomem *addr,
1417 int size,
1418 u32 *data)
1419
1420 {
1421 unsigned int i;
1422
1423 for (i = 0; i < size / sizeof(*data); i++)
1424 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1425 }
1426
internal_ram_wr(void __iomem * addr,int size,u32 * data)1427 static inline void internal_ram_wr(void __iomem *addr,
1428 int size,
1429 u32 *data)
1430 {
1431 __internal_ram_wr(NULL, addr, size, data);
1432 }
1433
1434 enum qed_rss_caps {
1435 QED_RSS_IPV4 = 0x1,
1436 QED_RSS_IPV6 = 0x2,
1437 QED_RSS_IPV4_TCP = 0x4,
1438 QED_RSS_IPV6_TCP = 0x8,
1439 QED_RSS_IPV4_UDP = 0x10,
1440 QED_RSS_IPV6_UDP = 0x20,
1441 };
1442
1443 #define QED_RSS_IND_TABLE_SIZE 128
1444 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1445 #endif
1446