1 /* 2 * Copyright 2013 Red Hat 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef VIRTGPU_DRM_H 25 #define VIRTGPU_DRM_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /* Please note that modifications to all structs defined here are 34 * subject to backwards-compatibility constraints. 35 * 36 * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel 37 * compatibility Keep fields aligned to their size 38 */ 39 40 #define DRM_VIRTGPU_MAP 0x01 41 #define DRM_VIRTGPU_EXECBUFFER 0x02 42 #define DRM_VIRTGPU_GETPARAM 0x03 43 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 44 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 45 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 46 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 47 #define DRM_VIRTGPU_WAIT 0x08 48 #define DRM_VIRTGPU_GET_CAPS 0x09 49 #define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a 50 51 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 52 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 53 #define VIRTGPU_EXECBUF_FLAGS (\ 54 VIRTGPU_EXECBUF_FENCE_FD_IN |\ 55 VIRTGPU_EXECBUF_FENCE_FD_OUT |\ 56 0) 57 58 struct drm_virtgpu_map { 59 uint64_t offset; /* use for mmap system call */ 60 uint32_t handle; 61 uint32_t pad; 62 }; 63 64 struct drm_virtgpu_execbuffer { 65 uint32_t flags; 66 uint32_t size; 67 uint64_t command; /* void* */ 68 uint64_t bo_handles; 69 uint32_t num_bo_handles; 70 int32_t fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ 71 }; 72 73 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ 74 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ 75 #define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */ 76 #define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */ 77 #define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */ 78 79 struct drm_virtgpu_getparam { 80 uint64_t param; 81 uint64_t value; 82 }; 83 84 /* NO_BO flags? NO resource flag? */ 85 /* resource flag for y_0_top */ 86 struct drm_virtgpu_resource_create { 87 uint32_t target; 88 uint32_t format; 89 uint32_t bind; 90 uint32_t width; 91 uint32_t height; 92 uint32_t depth; 93 uint32_t array_size; 94 uint32_t last_level; 95 uint32_t nr_samples; 96 uint32_t flags; 97 uint32_t bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ 98 uint32_t res_handle; /* returned by kernel */ 99 uint32_t size; /* validate transfer in the host */ 100 uint32_t stride; /* validate transfer in the host */ 101 }; 102 103 struct drm_virtgpu_resource_info { 104 uint32_t bo_handle; 105 uint32_t res_handle; 106 uint32_t size; 107 uint32_t blob_mem; 108 }; 109 110 struct drm_virtgpu_3d_box { 111 uint32_t x; 112 uint32_t y; 113 uint32_t z; 114 uint32_t w; 115 uint32_t h; 116 uint32_t d; 117 }; 118 119 struct drm_virtgpu_3d_transfer_to_host { 120 uint32_t bo_handle; 121 struct drm_virtgpu_3d_box box; 122 uint32_t level; 123 uint32_t offset; 124 uint32_t stride; 125 uint32_t layer_stride; 126 }; 127 128 struct drm_virtgpu_3d_transfer_from_host { 129 uint32_t bo_handle; 130 struct drm_virtgpu_3d_box box; 131 uint32_t level; 132 uint32_t offset; 133 uint32_t stride; 134 uint32_t layer_stride; 135 }; 136 137 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ 138 struct drm_virtgpu_3d_wait { 139 uint32_t handle; /* 0 is an invalid handle */ 140 uint32_t flags; 141 }; 142 143 struct drm_virtgpu_get_caps { 144 uint32_t cap_set_id; 145 uint32_t cap_set_ver; 146 uint64_t addr; 147 uint32_t size; 148 uint32_t pad; 149 }; 150 151 struct drm_virtgpu_resource_create_blob { 152 #define VIRTGPU_BLOB_MEM_GUEST 0x0001 153 #define VIRTGPU_BLOB_MEM_HOST3D 0x0002 154 #define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003 155 156 #define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001 157 #define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002 158 #define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 159 /* zero is invalid blob_mem */ 160 uint32_t blob_mem; 161 uint32_t blob_flags; 162 uint32_t bo_handle; 163 uint32_t res_handle; 164 uint64_t size; 165 166 /* 167 * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and 168 * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero. 169 */ 170 uint32_t pad; 171 uint32_t cmd_size; 172 uint64_t cmd; 173 uint64_t blob_id; 174 }; 175 176 #define DRM_IOCTL_VIRTGPU_MAP \ 177 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 178 179 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ 180 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ 181 struct drm_virtgpu_execbuffer) 182 183 #define DRM_IOCTL_VIRTGPU_GETPARAM \ 184 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ 185 struct drm_virtgpu_getparam) 186 187 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ 188 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ 189 struct drm_virtgpu_resource_create) 190 191 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ 192 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ 193 struct drm_virtgpu_resource_info) 194 195 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ 196 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ 197 struct drm_virtgpu_3d_transfer_from_host) 198 199 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ 200 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ 201 struct drm_virtgpu_3d_transfer_to_host) 202 203 #define DRM_IOCTL_VIRTGPU_WAIT \ 204 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ 205 struct drm_virtgpu_3d_wait) 206 207 #define DRM_IOCTL_VIRTGPU_GET_CAPS \ 208 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ 209 struct drm_virtgpu_get_caps) 210 211 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \ 212 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \ 213 struct drm_virtgpu_resource_create_blob) 214 215 #if defined(__cplusplus) 216 } 217 #endif 218 219 #endif 220