1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Digigram pcxhr compatible soundcards
4 *
5 * main file with alsa callbacks
6 *
7 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
8 */
9
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/info.h>
23 #include <sound/control.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include "pcxhr.h"
27 #include "pcxhr_mixer.h"
28 #include "pcxhr_hwdep.h"
29 #include "pcxhr_core.h"
30 #include "pcxhr_mix22.h"
31
32 #define DRIVER_NAME "pcxhr"
33
34 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
35 "Marc Titinger <titinger@digigram.com>");
36 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
37 MODULE_LICENSE("GPL");
38
39 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
40 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
41 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
42 static bool mono[SNDRV_CARDS]; /* capture mono only */
43
44 module_param_array(index, int, NULL, 0444);
45 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
46 module_param_array(id, charp, NULL, 0444);
47 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
48 module_param_array(enable, bool, NULL, 0444);
49 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
50 module_param_array(mono, bool, NULL, 0444);
51 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
52
53 enum {
54 PCI_ID_VX882HR,
55 PCI_ID_PCX882HR,
56 PCI_ID_VX881HR,
57 PCI_ID_PCX881HR,
58 PCI_ID_VX882E,
59 PCI_ID_PCX882E,
60 PCI_ID_VX881E,
61 PCI_ID_PCX881E,
62 PCI_ID_VX1222HR,
63 PCI_ID_PCX1222HR,
64 PCI_ID_VX1221HR,
65 PCI_ID_PCX1221HR,
66 PCI_ID_VX1222E,
67 PCI_ID_PCX1222E,
68 PCI_ID_VX1221E,
69 PCI_ID_PCX1221E,
70 PCI_ID_VX222HR,
71 PCI_ID_VX222E,
72 PCI_ID_PCX22HR,
73 PCI_ID_PCX22E,
74 PCI_ID_VX222HRMIC,
75 PCI_ID_VX222E_MIC,
76 PCI_ID_PCX924HR,
77 PCI_ID_PCX924E,
78 PCI_ID_PCX924HRMIC,
79 PCI_ID_PCX924E_MIC,
80 PCI_ID_VX442HR,
81 PCI_ID_PCX442HR,
82 PCI_ID_VX442E,
83 PCI_ID_PCX442E,
84 PCI_ID_VX822HR,
85 PCI_ID_PCX822HR,
86 PCI_ID_VX822E,
87 PCI_ID_PCX822E,
88 PCI_ID_LAST
89 };
90
91 static const struct pci_device_id pcxhr_ids[] = {
92 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
93 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
94 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
95 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
96 { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
97 { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
98 { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
99 { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
100 { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
101 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
102 { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
103 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
104 { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
105 { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
106 { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
107 { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
108 { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
109 { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
110 { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
111 { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
112 { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
113 { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
114 { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
115 { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
116 { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
117 { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
118 { 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, },
119 { 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, },
120 { 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, },
121 { 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, },
122 { 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, },
123 { 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, },
124 { 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, },
125 { 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, },
126 { 0, }
127 };
128
129 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
130
131 struct board_parameters {
132 char* board_name;
133 short playback_chips;
134 short capture_chips;
135 short fw_file_set;
136 short firmware_num;
137 };
138 static const struct board_parameters pcxhr_board_params[] = {
139 [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 },
140 [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 },
141 [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 },
142 [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 },
143 [PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 },
144 [PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 },
145 [PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 },
146 [PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 },
147 [PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 },
148 [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 },
149 [PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 },
150 [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 },
151 [PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 },
152 [PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 },
153 [PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 },
154 [PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 },
155 [PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 },
156 [PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 },
157 [PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 },
158 [PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 },
159 [PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 },
160 [PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 },
161 [PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 },
162 [PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 },
163 [PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 },
164 [PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 },
165 [PCI_ID_VX442HR] = { "VX442HR", 2, 2, 0, 41 },
166 [PCI_ID_PCX442HR] = { "PCX442HR", 2, 2, 0, 41 },
167 [PCI_ID_VX442E] = { "VX442e", 2, 2, 1, 41 },
168 [PCI_ID_PCX442E] = { "PCX442e", 2, 2, 1, 41 },
169 [PCI_ID_VX822HR] = { "VX822HR", 4, 1, 2, 42 },
170 [PCI_ID_PCX822HR] = { "PCX822HR", 4, 1, 2, 42 },
171 [PCI_ID_VX822E] = { "VX822e", 4, 1, 3, 42 },
172 [PCI_ID_PCX822E] = { "PCX822e", 4, 1, 3, 42 },
173 };
174
175 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
176 /* VX222HR, VX222e, PCX22HR and PCX22e */
177 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
178 /* some boards do not support 192kHz on digital AES input plugs */
179 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
180 (x->fw_file_set == 0) || \
181 (x->fw_file_set == 2))
182
pcxhr_pll_freq_register(unsigned int freq,unsigned int * pllreg,unsigned int * realfreq)183 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
184 unsigned int* realfreq)
185 {
186 unsigned int reg;
187
188 if (freq < 6900 || freq > 110000)
189 return -EINVAL;
190 reg = (28224000 * 2) / freq;
191 reg = (reg - 1) / 2;
192 if (reg < 0x200)
193 *pllreg = reg + 0x800;
194 else if (reg < 0x400)
195 *pllreg = reg & 0x1ff;
196 else if (reg < 0x800) {
197 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
198 reg &= ~1;
199 } else {
200 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
201 reg &= ~3;
202 }
203 if (realfreq)
204 *realfreq = (28224000 / (reg + 1));
205 return 0;
206 }
207
208
209 #define PCXHR_FREQ_REG_MASK 0x1f
210 #define PCXHR_FREQ_QUARTZ_48000 0x00
211 #define PCXHR_FREQ_QUARTZ_24000 0x01
212 #define PCXHR_FREQ_QUARTZ_12000 0x09
213 #define PCXHR_FREQ_QUARTZ_32000 0x08
214 #define PCXHR_FREQ_QUARTZ_16000 0x04
215 #define PCXHR_FREQ_QUARTZ_8000 0x0c
216 #define PCXHR_FREQ_QUARTZ_44100 0x02
217 #define PCXHR_FREQ_QUARTZ_22050 0x0a
218 #define PCXHR_FREQ_QUARTZ_11025 0x06
219 #define PCXHR_FREQ_PLL 0x05
220 #define PCXHR_FREQ_QUARTZ_192000 0x10
221 #define PCXHR_FREQ_QUARTZ_96000 0x18
222 #define PCXHR_FREQ_QUARTZ_176400 0x14
223 #define PCXHR_FREQ_QUARTZ_88200 0x1c
224 #define PCXHR_FREQ_QUARTZ_128000 0x12
225 #define PCXHR_FREQ_QUARTZ_64000 0x1a
226
227 #define PCXHR_FREQ_WORD_CLOCK 0x0f
228 #define PCXHR_FREQ_SYNC_AES 0x0e
229 #define PCXHR_FREQ_AES_1 0x07
230 #define PCXHR_FREQ_AES_2 0x0b
231 #define PCXHR_FREQ_AES_3 0x03
232 #define PCXHR_FREQ_AES_4 0x0d
233
pcxhr_get_clock_reg(struct pcxhr_mgr * mgr,unsigned int rate,unsigned int * reg,unsigned int * freq)234 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
235 unsigned int *reg, unsigned int *freq)
236 {
237 unsigned int val, realfreq, pllreg;
238 struct pcxhr_rmh rmh;
239 int err;
240
241 realfreq = rate;
242 switch (mgr->use_clock_type) {
243 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
244 switch (rate) {
245 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
246 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
247 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
248 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
249 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
250 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
251 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
252 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
253 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
254 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
255 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
256 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
257 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
258 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
259 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
260 default :
261 val = PCXHR_FREQ_PLL;
262 /* get the value for the pll register */
263 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
264 if (err)
265 return err;
266 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
267 rmh.cmd[0] |= IO_NUM_REG_GENCLK;
268 rmh.cmd[1] = pllreg & MASK_DSP_WORD;
269 rmh.cmd[2] = pllreg >> 24;
270 rmh.cmd_len = 3;
271 err = pcxhr_send_msg(mgr, &rmh);
272 if (err < 0) {
273 dev_err(&mgr->pci->dev,
274 "error CMD_ACCESS_IO_WRITE "
275 "for PLL register : %x!\n", err);
276 return err;
277 }
278 }
279 break;
280 case PCXHR_CLOCK_TYPE_WORD_CLOCK:
281 val = PCXHR_FREQ_WORD_CLOCK;
282 break;
283 case PCXHR_CLOCK_TYPE_AES_SYNC:
284 val = PCXHR_FREQ_SYNC_AES;
285 break;
286 case PCXHR_CLOCK_TYPE_AES_1:
287 val = PCXHR_FREQ_AES_1;
288 break;
289 case PCXHR_CLOCK_TYPE_AES_2:
290 val = PCXHR_FREQ_AES_2;
291 break;
292 case PCXHR_CLOCK_TYPE_AES_3:
293 val = PCXHR_FREQ_AES_3;
294 break;
295 case PCXHR_CLOCK_TYPE_AES_4:
296 val = PCXHR_FREQ_AES_4;
297 break;
298 default:
299 return -EINVAL;
300 }
301 *reg = val;
302 *freq = realfreq;
303 return 0;
304 }
305
306
pcxhr_sub_set_clock(struct pcxhr_mgr * mgr,unsigned int rate,int * changed)307 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
308 unsigned int rate,
309 int *changed)
310 {
311 unsigned int val, realfreq, speed;
312 struct pcxhr_rmh rmh;
313 int err;
314
315 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
316 if (err)
317 return err;
318
319 /* codec speed modes */
320 if (rate < 55000)
321 speed = 0; /* single speed */
322 else if (rate < 100000)
323 speed = 1; /* dual speed */
324 else
325 speed = 2; /* quad speed */
326 if (mgr->codec_speed != speed) {
327 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
328 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
329 if (DSP_EXT_CMD_SET(mgr)) {
330 rmh.cmd[1] = 1;
331 rmh.cmd_len = 2;
332 }
333 err = pcxhr_send_msg(mgr, &rmh);
334 if (err)
335 return err;
336
337 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
338 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
339 rmh.cmd[1] = speed;
340 rmh.cmd_len = 2;
341 err = pcxhr_send_msg(mgr, &rmh);
342 if (err)
343 return err;
344 }
345 /* set the new frequency */
346 dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val);
347 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
348 val, changed);
349 if (err)
350 return err;
351
352 mgr->sample_rate_real = realfreq;
353 mgr->cur_clock_type = mgr->use_clock_type;
354
355 /* unmute after codec speed modes */
356 if (mgr->codec_speed != speed) {
357 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
358 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
359 if (DSP_EXT_CMD_SET(mgr)) {
360 rmh.cmd[1] = 1;
361 rmh.cmd_len = 2;
362 }
363 err = pcxhr_send_msg(mgr, &rmh);
364 if (err)
365 return err;
366 mgr->codec_speed = speed; /* save new codec speed */
367 }
368
369 dev_dbg(&mgr->pci->dev, "pcxhr_sub_set_clock to %dHz (realfreq=%d)\n",
370 rate, realfreq);
371 return 0;
372 }
373
374 #define PCXHR_MODIFY_CLOCK_S_BIT 0x04
375
376 #define PCXHR_IRQ_TIMER_FREQ 92000
377 #define PCXHR_IRQ_TIMER_PERIOD 48
378
pcxhr_set_clock(struct pcxhr_mgr * mgr,unsigned int rate)379 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
380 {
381 struct pcxhr_rmh rmh;
382 int err, changed;
383
384 if (rate == 0)
385 return 0; /* nothing to do */
386
387 if (mgr->is_hr_stereo)
388 err = hr222_sub_set_clock(mgr, rate, &changed);
389 else
390 err = pcxhr_sub_set_clock(mgr, rate, &changed);
391
392 if (err)
393 return err;
394
395 if (changed) {
396 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
397 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
398 if (rate < PCXHR_IRQ_TIMER_FREQ)
399 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
400 else
401 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
402 rmh.cmd[2] = rate;
403 rmh.cmd_len = 3;
404 err = pcxhr_send_msg(mgr, &rmh);
405 if (err)
406 return err;
407 }
408 return 0;
409 }
410
411
pcxhr_sub_get_external_clock(struct pcxhr_mgr * mgr,enum pcxhr_clock_type clock_type,int * sample_rate)412 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
413 enum pcxhr_clock_type clock_type,
414 int *sample_rate)
415 {
416 struct pcxhr_rmh rmh;
417 unsigned char reg;
418 int err, rate;
419
420 switch (clock_type) {
421 case PCXHR_CLOCK_TYPE_WORD_CLOCK:
422 reg = REG_STATUS_WORD_CLOCK;
423 break;
424 case PCXHR_CLOCK_TYPE_AES_SYNC:
425 reg = REG_STATUS_AES_SYNC;
426 break;
427 case PCXHR_CLOCK_TYPE_AES_1:
428 reg = REG_STATUS_AES_1;
429 break;
430 case PCXHR_CLOCK_TYPE_AES_2:
431 reg = REG_STATUS_AES_2;
432 break;
433 case PCXHR_CLOCK_TYPE_AES_3:
434 reg = REG_STATUS_AES_3;
435 break;
436 case PCXHR_CLOCK_TYPE_AES_4:
437 reg = REG_STATUS_AES_4;
438 break;
439 default:
440 return -EINVAL;
441 }
442 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
443 rmh.cmd_len = 2;
444 rmh.cmd[0] |= IO_NUM_REG_STATUS;
445 if (mgr->last_reg_stat != reg) {
446 rmh.cmd[1] = reg;
447 err = pcxhr_send_msg(mgr, &rmh);
448 if (err)
449 return err;
450 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
451 mgr->last_reg_stat = reg;
452 }
453 rmh.cmd[1] = REG_STATUS_CURRENT;
454 err = pcxhr_send_msg(mgr, &rmh);
455 if (err)
456 return err;
457 switch (rmh.stat[1] & 0x0f) {
458 case REG_STATUS_SYNC_32000 : rate = 32000; break;
459 case REG_STATUS_SYNC_44100 : rate = 44100; break;
460 case REG_STATUS_SYNC_48000 : rate = 48000; break;
461 case REG_STATUS_SYNC_64000 : rate = 64000; break;
462 case REG_STATUS_SYNC_88200 : rate = 88200; break;
463 case REG_STATUS_SYNC_96000 : rate = 96000; break;
464 case REG_STATUS_SYNC_128000 : rate = 128000; break;
465 case REG_STATUS_SYNC_176400 : rate = 176400; break;
466 case REG_STATUS_SYNC_192000 : rate = 192000; break;
467 default: rate = 0;
468 }
469 dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate);
470 *sample_rate = rate;
471 return 0;
472 }
473
474
pcxhr_get_external_clock(struct pcxhr_mgr * mgr,enum pcxhr_clock_type clock_type,int * sample_rate)475 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
476 enum pcxhr_clock_type clock_type,
477 int *sample_rate)
478 {
479 if (mgr->is_hr_stereo)
480 return hr222_get_external_clock(mgr, clock_type,
481 sample_rate);
482 else
483 return pcxhr_sub_get_external_clock(mgr, clock_type,
484 sample_rate);
485 }
486
487 /*
488 * start or stop playback/capture substream
489 */
pcxhr_set_stream_state(struct snd_pcxhr * chip,struct pcxhr_stream * stream)490 static int pcxhr_set_stream_state(struct snd_pcxhr *chip,
491 struct pcxhr_stream *stream)
492 {
493 int err;
494 struct pcxhr_rmh rmh;
495 int stream_mask, start;
496
497 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
498 start = 1;
499 else {
500 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
501 dev_err(chip->card->dev,
502 "pcxhr_set_stream_state CANNOT be stopped\n");
503 return -EINVAL;
504 }
505 start = 0;
506 }
507 if (!stream->substream)
508 return -EINVAL;
509
510 stream->timer_abs_periods = 0;
511 stream->timer_period_frag = 0; /* reset theoretical stream pos */
512 stream->timer_buf_periods = 0;
513 stream->timer_is_synced = 0;
514
515 stream_mask =
516 stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
517
518 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
519 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
520 stream->pipe->first_audio, 0, stream_mask);
521
522 chip = snd_pcm_substream_chip(stream->substream);
523
524 err = pcxhr_send_msg(chip->mgr, &rmh);
525 if (err)
526 dev_err(chip->card->dev,
527 "ERROR pcxhr_set_stream_state err=%x;\n", err);
528 stream->status =
529 start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
530 return err;
531 }
532
533 #define HEADER_FMT_BASE_LIN 0xfed00000
534 #define HEADER_FMT_BASE_FLOAT 0xfad00000
535 #define HEADER_FMT_INTEL 0x00008000
536 #define HEADER_FMT_24BITS 0x00004000
537 #define HEADER_FMT_16BITS 0x00002000
538 #define HEADER_FMT_UPTO11 0x00000200
539 #define HEADER_FMT_UPTO32 0x00000100
540 #define HEADER_FMT_MONO 0x00000080
541
pcxhr_set_format(struct pcxhr_stream * stream)542 static int pcxhr_set_format(struct pcxhr_stream *stream)
543 {
544 int err, is_capture, sample_rate, stream_num;
545 struct snd_pcxhr *chip;
546 struct pcxhr_rmh rmh;
547 unsigned int header;
548
549 chip = snd_pcm_substream_chip(stream->substream);
550 switch (stream->format) {
551 case SNDRV_PCM_FORMAT_U8:
552 header = HEADER_FMT_BASE_LIN;
553 break;
554 case SNDRV_PCM_FORMAT_S16_LE:
555 header = HEADER_FMT_BASE_LIN |
556 HEADER_FMT_16BITS | HEADER_FMT_INTEL;
557 break;
558 case SNDRV_PCM_FORMAT_S16_BE:
559 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
560 break;
561 case SNDRV_PCM_FORMAT_S24_3LE:
562 header = HEADER_FMT_BASE_LIN |
563 HEADER_FMT_24BITS | HEADER_FMT_INTEL;
564 break;
565 case SNDRV_PCM_FORMAT_S24_3BE:
566 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
567 break;
568 case SNDRV_PCM_FORMAT_FLOAT_LE:
569 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
570 break;
571 default:
572 dev_err(chip->card->dev,
573 "error pcxhr_set_format() : unknown format\n");
574 return -EINVAL;
575 }
576
577 sample_rate = chip->mgr->sample_rate;
578 if (sample_rate <= 32000 && sample_rate !=0) {
579 if (sample_rate <= 11025)
580 header |= HEADER_FMT_UPTO11;
581 else
582 header |= HEADER_FMT_UPTO32;
583 }
584 if (stream->channels == 1)
585 header |= HEADER_FMT_MONO;
586
587 is_capture = stream->pipe->is_capture;
588 stream_num = is_capture ? 0 : stream->substream->number;
589
590 pcxhr_init_rmh(&rmh, is_capture ?
591 CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
592 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
593 stream_num, 0);
594 if (is_capture) {
595 /* bug with old dsp versions: */
596 /* bit 12 also sets the format of the playback stream */
597 if (DSP_EXT_CMD_SET(chip->mgr))
598 rmh.cmd[0] |= 1<<10;
599 else
600 rmh.cmd[0] |= 1<<12;
601 }
602 rmh.cmd[1] = 0;
603 rmh.cmd_len = 2;
604 if (DSP_EXT_CMD_SET(chip->mgr)) {
605 /* add channels and set bit 19 if channels>2 */
606 rmh.cmd[1] = stream->channels;
607 if (!is_capture) {
608 /* playback : add channel mask to command */
609 rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
610 rmh.cmd_len = 3;
611 }
612 }
613 rmh.cmd[rmh.cmd_len++] = header >> 8;
614 rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
615 err = pcxhr_send_msg(chip->mgr, &rmh);
616 if (err)
617 dev_err(chip->card->dev,
618 "ERROR pcxhr_set_format err=%x;\n", err);
619 return err;
620 }
621
pcxhr_update_r_buffer(struct pcxhr_stream * stream)622 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
623 {
624 int err, is_capture, stream_num;
625 struct pcxhr_rmh rmh;
626 struct snd_pcm_substream *subs = stream->substream;
627 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
628
629 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
630 stream_num = is_capture ? 0 : subs->number;
631
632 dev_dbg(chip->card->dev,
633 "pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
634 is_capture ? 'c' : 'p',
635 chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
636 subs->runtime->dma_bytes, subs->number);
637
638 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
639 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
640 stream_num, 0);
641
642 /* max buffer size is 2 MByte */
643 snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
644 /* size in bits */
645 rmh.cmd[1] = subs->runtime->dma_bytes * 8;
646 /* most significant byte */
647 rmh.cmd[2] = subs->runtime->dma_addr >> 24;
648 /* this is a circular buffer */
649 rmh.cmd[2] |= 1<<19;
650 /* least 3 significant bytes */
651 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
652 rmh.cmd_len = 4;
653 err = pcxhr_send_msg(chip->mgr, &rmh);
654 if (err)
655 dev_err(chip->card->dev,
656 "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
657 return err;
658 }
659
660
661 #if 0
662 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
663 snd_pcm_uframes_t *sample_count)
664 {
665 struct pcxhr_rmh rmh;
666 int err;
667 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
668 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
669 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
670 1<<stream->pipe->first_audio);
671 err = pcxhr_send_msg(chip->mgr, &rmh);
672 if (err == 0) {
673 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
674 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
675 }
676 dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
677 return err;
678 }
679 #endif
680
pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream * stream,struct pcxhr_pipe ** pipe)681 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
682 struct pcxhr_pipe **pipe)
683 {
684 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
685 *pipe = stream->pipe;
686 return 1;
687 }
688 return 0;
689 }
690
pcxhr_start_linked_stream(struct pcxhr_mgr * mgr)691 static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr)
692 {
693 int i, j, err;
694 struct pcxhr_pipe *pipe;
695 struct snd_pcxhr *chip;
696 int capture_mask = 0;
697 int playback_mask = 0;
698
699 #ifdef CONFIG_SND_DEBUG_VERBOSE
700 ktime_t start_time, stop_time, diff_time;
701
702 start_time = ktime_get();
703 #endif
704 mutex_lock(&mgr->setup_mutex);
705
706 /* check the pipes concerned and build pipe_array */
707 for (i = 0; i < mgr->num_cards; i++) {
708 chip = mgr->chip[i];
709 for (j = 0; j < chip->nb_streams_capt; j++) {
710 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
711 capture_mask |= (1 << pipe->first_audio);
712 }
713 for (j = 0; j < chip->nb_streams_play; j++) {
714 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
715 playback_mask |= (1 << pipe->first_audio);
716 break; /* add only once, as all playback
717 * streams of one chip use the same pipe
718 */
719 }
720 }
721 }
722 if (capture_mask == 0 && playback_mask == 0) {
723 mutex_unlock(&mgr->setup_mutex);
724 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : no pipes\n");
725 return;
726 }
727
728 dev_dbg(&mgr->pci->dev, "pcxhr_start_linked_stream : "
729 "playback_mask=%x capture_mask=%x\n",
730 playback_mask, capture_mask);
731
732 /* synchronous stop of all the pipes concerned */
733 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
734 if (err) {
735 mutex_unlock(&mgr->setup_mutex);
736 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : "
737 "error stop pipes (P%x C%x)\n",
738 playback_mask, capture_mask);
739 return;
740 }
741
742 /* the dsp lost format and buffer info with the stop pipe */
743 for (i = 0; i < mgr->num_cards; i++) {
744 struct pcxhr_stream *stream;
745 chip = mgr->chip[i];
746 for (j = 0; j < chip->nb_streams_capt; j++) {
747 stream = &chip->capture_stream[j];
748 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
749 err = pcxhr_set_format(stream);
750 err = pcxhr_update_r_buffer(stream);
751 }
752 }
753 for (j = 0; j < chip->nb_streams_play; j++) {
754 stream = &chip->playback_stream[j];
755 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
756 err = pcxhr_set_format(stream);
757 err = pcxhr_update_r_buffer(stream);
758 }
759 }
760 }
761 /* start all the streams */
762 for (i = 0; i < mgr->num_cards; i++) {
763 struct pcxhr_stream *stream;
764 chip = mgr->chip[i];
765 for (j = 0; j < chip->nb_streams_capt; j++) {
766 stream = &chip->capture_stream[j];
767 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
768 err = pcxhr_set_stream_state(chip, stream);
769 }
770 for (j = 0; j < chip->nb_streams_play; j++) {
771 stream = &chip->playback_stream[j];
772 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
773 err = pcxhr_set_stream_state(chip, stream);
774 }
775 }
776
777 /* synchronous start of all the pipes concerned */
778 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
779 if (err) {
780 mutex_unlock(&mgr->setup_mutex);
781 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : "
782 "error start pipes (P%x C%x)\n",
783 playback_mask, capture_mask);
784 return;
785 }
786
787 /* put the streams into the running state now
788 * (increment pointer by interrupt)
789 */
790 mutex_lock(&mgr->lock);
791 for ( i =0; i < mgr->num_cards; i++) {
792 struct pcxhr_stream *stream;
793 chip = mgr->chip[i];
794 for(j = 0; j < chip->nb_streams_capt; j++) {
795 stream = &chip->capture_stream[j];
796 if(stream->status == PCXHR_STREAM_STATUS_STARTED)
797 stream->status = PCXHR_STREAM_STATUS_RUNNING;
798 }
799 for (j = 0; j < chip->nb_streams_play; j++) {
800 stream = &chip->playback_stream[j];
801 if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
802 /* playback will already have advanced ! */
803 stream->timer_period_frag += mgr->granularity;
804 stream->status = PCXHR_STREAM_STATUS_RUNNING;
805 }
806 }
807 }
808 mutex_unlock(&mgr->lock);
809
810 mutex_unlock(&mgr->setup_mutex);
811
812 #ifdef CONFIG_SND_DEBUG_VERBOSE
813 stop_time = ktime_get();
814 diff_time = ktime_sub(stop_time, start_time);
815 dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n",
816 (long)(ktime_to_ns(diff_time)), err);
817 #endif
818 }
819
820
821 /*
822 * trigger callback
823 */
pcxhr_trigger(struct snd_pcm_substream * subs,int cmd)824 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
825 {
826 struct pcxhr_stream *stream;
827 struct snd_pcm_substream *s;
828 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
829
830 switch (cmd) {
831 case SNDRV_PCM_TRIGGER_START:
832 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n");
833 if (snd_pcm_stream_linked(subs)) {
834 snd_pcm_group_for_each_entry(s, subs) {
835 if (snd_pcm_substream_chip(s) != chip)
836 continue;
837 stream = s->runtime->private_data;
838 stream->status =
839 PCXHR_STREAM_STATUS_SCHEDULE_RUN;
840 snd_pcm_trigger_done(s, subs);
841 }
842 pcxhr_start_linked_stream(chip->mgr);
843 } else {
844 stream = subs->runtime->private_data;
845 dev_dbg(chip->card->dev, "Only one Substream %c %d\n",
846 stream->pipe->is_capture ? 'C' : 'P',
847 stream->pipe->first_audio);
848 if (pcxhr_set_format(stream))
849 return -EINVAL;
850 if (pcxhr_update_r_buffer(stream))
851 return -EINVAL;
852
853 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
854 if (pcxhr_set_stream_state(chip, stream))
855 return -EINVAL;
856 stream->status = PCXHR_STREAM_STATUS_RUNNING;
857 }
858 break;
859 case SNDRV_PCM_TRIGGER_STOP:
860 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n");
861 snd_pcm_group_for_each_entry(s, subs) {
862 stream = s->runtime->private_data;
863 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
864 if (pcxhr_set_stream_state(chip, stream))
865 return -EINVAL;
866 snd_pcm_trigger_done(s, subs);
867 }
868 break;
869 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
870 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
871 /* TODO */
872 default:
873 return -EINVAL;
874 }
875 return 0;
876 }
877
878
pcxhr_hardware_timer(struct pcxhr_mgr * mgr,int start)879 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
880 {
881 struct pcxhr_rmh rmh;
882 int err;
883
884 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
885 if (start) {
886 /* last dsp time invalid */
887 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
888 rmh.cmd[0] |= mgr->granularity;
889 }
890 err = pcxhr_send_msg(mgr, &rmh);
891 if (err < 0)
892 dev_err(&mgr->pci->dev, "error pcxhr_hardware_timer err(%x)\n",
893 err);
894 return err;
895 }
896
897 /*
898 * prepare callback for all pcms
899 */
pcxhr_prepare(struct snd_pcm_substream * subs)900 static int pcxhr_prepare(struct snd_pcm_substream *subs)
901 {
902 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
903 struct pcxhr_mgr *mgr = chip->mgr;
904 int err = 0;
905
906 dev_dbg(chip->card->dev,
907 "pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
908 subs->runtime->period_size, subs->runtime->periods,
909 subs->runtime->buffer_size);
910
911 mutex_lock(&mgr->setup_mutex);
912
913 do {
914 /* only the first stream can choose the sample rate */
915 /* set the clock only once (first stream) */
916 if (mgr->sample_rate != subs->runtime->rate) {
917 err = pcxhr_set_clock(mgr, subs->runtime->rate);
918 if (err)
919 break;
920 if (mgr->sample_rate == 0)
921 /* start the DSP-timer */
922 err = pcxhr_hardware_timer(mgr, 1);
923 mgr->sample_rate = subs->runtime->rate;
924 }
925 } while(0); /* do only once (so we can use break instead of goto) */
926
927 mutex_unlock(&mgr->setup_mutex);
928
929 return err;
930 }
931
932
933 /*
934 * HW_PARAMS callback for all pcms
935 */
pcxhr_hw_params(struct snd_pcm_substream * subs,struct snd_pcm_hw_params * hw)936 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
937 struct snd_pcm_hw_params *hw)
938 {
939 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
940 struct pcxhr_mgr *mgr = chip->mgr;
941 struct pcxhr_stream *stream = subs->runtime->private_data;
942
943 mutex_lock(&mgr->setup_mutex);
944
945 /* set up channels */
946 stream->channels = params_channels(hw);
947 /* set up format for the stream */
948 stream->format = params_format(hw);
949
950 mutex_unlock(&mgr->setup_mutex);
951
952 return 0;
953 }
954
955
956 /*
957 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
958 */
959 static const struct snd_pcm_hardware pcxhr_caps =
960 {
961 .info = (SNDRV_PCM_INFO_MMAP |
962 SNDRV_PCM_INFO_INTERLEAVED |
963 SNDRV_PCM_INFO_MMAP_VALID |
964 SNDRV_PCM_INFO_SYNC_START),
965 .formats = (SNDRV_PCM_FMTBIT_U8 |
966 SNDRV_PCM_FMTBIT_S16_LE |
967 SNDRV_PCM_FMTBIT_S16_BE |
968 SNDRV_PCM_FMTBIT_S24_3LE |
969 SNDRV_PCM_FMTBIT_S24_3BE |
970 SNDRV_PCM_FMTBIT_FLOAT_LE),
971 .rates = (SNDRV_PCM_RATE_CONTINUOUS |
972 SNDRV_PCM_RATE_8000_192000),
973 .rate_min = 8000,
974 .rate_max = 192000,
975 .channels_min = 1,
976 .channels_max = 2,
977 .buffer_bytes_max = (32*1024),
978 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
979 .period_bytes_min = (2*PCXHR_GRANULARITY),
980 .period_bytes_max = (16*1024),
981 .periods_min = 2,
982 .periods_max = (32*1024/PCXHR_GRANULARITY),
983 };
984
985
pcxhr_open(struct snd_pcm_substream * subs)986 static int pcxhr_open(struct snd_pcm_substream *subs)
987 {
988 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
989 struct pcxhr_mgr *mgr = chip->mgr;
990 struct snd_pcm_runtime *runtime = subs->runtime;
991 struct pcxhr_stream *stream;
992 int err;
993
994 mutex_lock(&mgr->setup_mutex);
995
996 /* copy the struct snd_pcm_hardware struct */
997 runtime->hw = pcxhr_caps;
998
999 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
1000 dev_dbg(chip->card->dev, "pcxhr_open playback chip%d subs%d\n",
1001 chip->chip_idx, subs->number);
1002 stream = &chip->playback_stream[subs->number];
1003 } else {
1004 dev_dbg(chip->card->dev, "pcxhr_open capture chip%d subs%d\n",
1005 chip->chip_idx, subs->number);
1006 if (mgr->mono_capture)
1007 runtime->hw.channels_max = 1;
1008 else
1009 runtime->hw.channels_min = 2;
1010 stream = &chip->capture_stream[subs->number];
1011 }
1012 if (stream->status != PCXHR_STREAM_STATUS_FREE){
1013 /* streams in use */
1014 dev_err(chip->card->dev, "pcxhr_open chip%d subs%d in use\n",
1015 chip->chip_idx, subs->number);
1016 mutex_unlock(&mgr->setup_mutex);
1017 return -EBUSY;
1018 }
1019
1020 /* float format support is in some cases buggy on stereo cards */
1021 if (mgr->is_hr_stereo)
1022 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1023
1024 /* buffer-size should better be multiple of period-size */
1025 err = snd_pcm_hw_constraint_integer(runtime,
1026 SNDRV_PCM_HW_PARAM_PERIODS);
1027 if (err < 0) {
1028 mutex_unlock(&mgr->setup_mutex);
1029 return err;
1030 }
1031
1032 /* if a sample rate is already used or fixed by external clock,
1033 * the stream cannot change
1034 */
1035 if (mgr->sample_rate)
1036 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1037 else {
1038 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1039 int external_rate;
1040 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
1041 &external_rate) ||
1042 external_rate == 0) {
1043 /* cannot detect the external clock rate */
1044 mutex_unlock(&mgr->setup_mutex);
1045 return -EBUSY;
1046 }
1047 runtime->hw.rate_min = external_rate;
1048 runtime->hw.rate_max = external_rate;
1049 }
1050 }
1051
1052 stream->status = PCXHR_STREAM_STATUS_OPEN;
1053 stream->substream = subs;
1054 stream->channels = 0; /* not configured yet */
1055
1056 runtime->private_data = stream;
1057
1058 /* better get a divisor of granularity values (96 or 192) */
1059 snd_pcm_hw_constraint_step(runtime, 0,
1060 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1061 snd_pcm_hw_constraint_step(runtime, 0,
1062 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
1063 snd_pcm_set_sync(subs);
1064
1065 mgr->ref_count_rate++;
1066
1067 mutex_unlock(&mgr->setup_mutex);
1068 return 0;
1069 }
1070
1071
pcxhr_close(struct snd_pcm_substream * subs)1072 static int pcxhr_close(struct snd_pcm_substream *subs)
1073 {
1074 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1075 struct pcxhr_mgr *mgr = chip->mgr;
1076 struct pcxhr_stream *stream = subs->runtime->private_data;
1077
1078 mutex_lock(&mgr->setup_mutex);
1079
1080 dev_dbg(chip->card->dev, "pcxhr_close chip%d subs%d\n",
1081 chip->chip_idx, subs->number);
1082
1083 /* sample rate released */
1084 if (--mgr->ref_count_rate == 0) {
1085 mgr->sample_rate = 0; /* the sample rate is no more locked */
1086 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
1087 }
1088
1089 stream->status = PCXHR_STREAM_STATUS_FREE;
1090 stream->substream = NULL;
1091
1092 mutex_unlock(&mgr->setup_mutex);
1093
1094 return 0;
1095 }
1096
1097
pcxhr_stream_pointer(struct snd_pcm_substream * subs)1098 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1099 {
1100 u_int32_t timer_period_frag;
1101 int timer_buf_periods;
1102 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1103 struct snd_pcm_runtime *runtime = subs->runtime;
1104 struct pcxhr_stream *stream = runtime->private_data;
1105
1106 mutex_lock(&chip->mgr->lock);
1107
1108 /* get the period fragment and the nb of periods in the buffer */
1109 timer_period_frag = stream->timer_period_frag;
1110 timer_buf_periods = stream->timer_buf_periods;
1111
1112 mutex_unlock(&chip->mgr->lock);
1113
1114 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1115 timer_period_frag);
1116 }
1117
1118
1119 static const struct snd_pcm_ops pcxhr_ops = {
1120 .open = pcxhr_open,
1121 .close = pcxhr_close,
1122 .prepare = pcxhr_prepare,
1123 .hw_params = pcxhr_hw_params,
1124 .trigger = pcxhr_trigger,
1125 .pointer = pcxhr_stream_pointer,
1126 };
1127
1128 /*
1129 */
pcxhr_create_pcm(struct snd_pcxhr * chip)1130 int pcxhr_create_pcm(struct snd_pcxhr *chip)
1131 {
1132 int err;
1133 struct snd_pcm *pcm;
1134 char name[32];
1135
1136 snprintf(name, sizeof(name), "pcxhr %d", chip->chip_idx);
1137 if ((err = snd_pcm_new(chip->card, name, 0,
1138 chip->nb_streams_play,
1139 chip->nb_streams_capt, &pcm)) < 0) {
1140 dev_err(chip->card->dev, "cannot create pcm %s\n", name);
1141 return err;
1142 }
1143 pcm->private_data = chip;
1144
1145 if (chip->nb_streams_play)
1146 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
1147 if (chip->nb_streams_capt)
1148 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
1149
1150 pcm->info_flags = 0;
1151 pcm->nonatomic = true;
1152 strcpy(pcm->name, name);
1153
1154 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1155 &chip->mgr->pci->dev,
1156 32*1024, 32*1024);
1157 chip->pcm = pcm;
1158 return 0;
1159 }
1160
pcxhr_chip_free(struct snd_pcxhr * chip)1161 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1162 {
1163 kfree(chip);
1164 return 0;
1165 }
1166
pcxhr_chip_dev_free(struct snd_device * device)1167 static int pcxhr_chip_dev_free(struct snd_device *device)
1168 {
1169 struct snd_pcxhr *chip = device->device_data;
1170 return pcxhr_chip_free(chip);
1171 }
1172
1173
1174 /*
1175 */
pcxhr_create(struct pcxhr_mgr * mgr,struct snd_card * card,int idx)1176 static int pcxhr_create(struct pcxhr_mgr *mgr,
1177 struct snd_card *card, int idx)
1178 {
1179 int err;
1180 struct snd_pcxhr *chip;
1181 static const struct snd_device_ops ops = {
1182 .dev_free = pcxhr_chip_dev_free,
1183 };
1184
1185 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1186 if (!chip)
1187 return -ENOMEM;
1188
1189 chip->card = card;
1190 chip->chip_idx = idx;
1191 chip->mgr = mgr;
1192 card->sync_irq = mgr->irq;
1193
1194 if (idx < mgr->playback_chips)
1195 /* stereo or mono streams */
1196 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1197
1198 if (idx < mgr->capture_chips) {
1199 if (mgr->mono_capture)
1200 chip->nb_streams_capt = 2; /* 2 mono streams */
1201 else
1202 chip->nb_streams_capt = 1; /* or 1 stereo stream */
1203 }
1204
1205 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1206 pcxhr_chip_free(chip);
1207 return err;
1208 }
1209
1210 mgr->chip[idx] = chip;
1211
1212 return 0;
1213 }
1214
1215 /* proc interface */
pcxhr_proc_info(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1216 static void pcxhr_proc_info(struct snd_info_entry *entry,
1217 struct snd_info_buffer *buffer)
1218 {
1219 struct snd_pcxhr *chip = entry->private_data;
1220 struct pcxhr_mgr *mgr = chip->mgr;
1221
1222 snd_iprintf(buffer, "\n%s\n", mgr->name);
1223
1224 /* stats available when embedded DSP is running */
1225 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1226 struct pcxhr_rmh rmh;
1227 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1228 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1229 short ver_build = mgr->dsp_version & 0xff;
1230 snd_iprintf(buffer, "module version %s\n",
1231 PCXHR_DRIVER_VERSION_STRING);
1232 snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1233 ver_maj, ver_min, ver_build);
1234 if (mgr->board_has_analog)
1235 snd_iprintf(buffer, "analog io available\n");
1236 else
1237 snd_iprintf(buffer, "digital only board\n");
1238
1239 /* calc cpu load of the dsp */
1240 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1241 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1242 int cur = rmh.stat[0];
1243 int ref = rmh.stat[1];
1244 if (ref > 0) {
1245 if (mgr->sample_rate_real != 0 &&
1246 mgr->sample_rate_real != 48000) {
1247 ref = (ref * 48000) /
1248 mgr->sample_rate_real;
1249 if (mgr->sample_rate_real >=
1250 PCXHR_IRQ_TIMER_FREQ)
1251 ref *= 2;
1252 }
1253 cur = 100 - (100 * cur) / ref;
1254 snd_iprintf(buffer, "cpu load %d%%\n", cur);
1255 snd_iprintf(buffer, "buffer pool %d/%d\n",
1256 rmh.stat[2], rmh.stat[3]);
1257 }
1258 }
1259 snd_iprintf(buffer, "dma granularity : %d\n",
1260 mgr->granularity);
1261 snd_iprintf(buffer, "dsp time errors : %d\n",
1262 mgr->dsp_time_err);
1263 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1264 mgr->async_err_pipe_xrun);
1265 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1266 mgr->async_err_stream_xrun);
1267 snd_iprintf(buffer, "dsp async last other error : %x\n",
1268 mgr->async_err_other_last);
1269 /* debug zone dsp */
1270 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1271 rmh.cmd_len = 1;
1272 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1273 rmh.dsp_stat = 0;
1274 rmh.cmd_idx = CMD_LAST_INDEX;
1275 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1276 int i;
1277 if (rmh.stat_len > 8)
1278 rmh.stat_len = 8;
1279 for (i = 0; i < rmh.stat_len; i++)
1280 snd_iprintf(buffer, "debug[%02d] = %06x\n",
1281 i, rmh.stat[i]);
1282 }
1283 } else
1284 snd_iprintf(buffer, "no firmware loaded\n");
1285 snd_iprintf(buffer, "\n");
1286 }
pcxhr_proc_sync(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1287 static void pcxhr_proc_sync(struct snd_info_entry *entry,
1288 struct snd_info_buffer *buffer)
1289 {
1290 struct snd_pcxhr *chip = entry->private_data;
1291 struct pcxhr_mgr *mgr = chip->mgr;
1292 static const char *textsHR22[3] = {
1293 "Internal", "AES Sync", "AES 1"
1294 };
1295 static const char *textsPCXHR[7] = {
1296 "Internal", "Word", "AES Sync",
1297 "AES 1", "AES 2", "AES 3", "AES 4"
1298 };
1299 const char **texts;
1300 int max_clock;
1301 if (mgr->is_hr_stereo) {
1302 texts = textsHR22;
1303 max_clock = HR22_CLOCK_TYPE_MAX;
1304 } else {
1305 texts = textsPCXHR;
1306 max_clock = PCXHR_CLOCK_TYPE_MAX;
1307 }
1308
1309 snd_iprintf(buffer, "\n%s\n", mgr->name);
1310 snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1311 texts[mgr->cur_clock_type]);
1312 snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1313 mgr->sample_rate_real);
1314 /* commands available when embedded DSP is running */
1315 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1316 int i, err, sample_rate;
1317 for (i = 1; i <= max_clock; i++) {
1318 err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1319 if (err)
1320 break;
1321 snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1322 texts[i], sample_rate);
1323 }
1324 } else
1325 snd_iprintf(buffer, "no firmware loaded\n");
1326 snd_iprintf(buffer, "\n");
1327 }
1328
pcxhr_proc_gpio_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1329 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1330 struct snd_info_buffer *buffer)
1331 {
1332 struct snd_pcxhr *chip = entry->private_data;
1333 struct pcxhr_mgr *mgr = chip->mgr;
1334 /* commands available when embedded DSP is running */
1335 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1336 /* gpio ports on stereo boards only available */
1337 int value = 0;
1338 hr222_read_gpio(mgr, 1, &value); /* GPI */
1339 snd_iprintf(buffer, "GPI: 0x%x\n", value);
1340 hr222_read_gpio(mgr, 0, &value); /* GP0 */
1341 snd_iprintf(buffer, "GPO: 0x%x\n", value);
1342 } else
1343 snd_iprintf(buffer, "no firmware loaded\n");
1344 snd_iprintf(buffer, "\n");
1345 }
pcxhr_proc_gpo_write(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1346 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1347 struct snd_info_buffer *buffer)
1348 {
1349 struct snd_pcxhr *chip = entry->private_data;
1350 struct pcxhr_mgr *mgr = chip->mgr;
1351 char line[64];
1352 int value;
1353 /* commands available when embedded DSP is running */
1354 if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1355 return;
1356 while (!snd_info_get_line(buffer, line, sizeof(line))) {
1357 if (sscanf(line, "GPO: 0x%x", &value) != 1)
1358 continue;
1359 hr222_write_gpo(mgr, value); /* GP0 */
1360 }
1361 }
1362
1363 /* Access to the results of the CMD_GET_TIME_CODE RMH */
1364 #define TIME_CODE_VALID_MASK 0x00800000
1365 #define TIME_CODE_NEW_MASK 0x00400000
1366 #define TIME_CODE_BACK_MASK 0x00200000
1367 #define TIME_CODE_WAIT_MASK 0x00100000
1368
1369 /* Values for the CMD_MANAGE_SIGNAL RMH */
1370 #define MANAGE_SIGNAL_TIME_CODE 0x01
1371 #define MANAGE_SIGNAL_MIDI 0x02
1372
1373 /* linear time code read proc*/
pcxhr_proc_ltc(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1374 static void pcxhr_proc_ltc(struct snd_info_entry *entry,
1375 struct snd_info_buffer *buffer)
1376 {
1377 struct snd_pcxhr *chip = entry->private_data;
1378 struct pcxhr_mgr *mgr = chip->mgr;
1379 struct pcxhr_rmh rmh;
1380 unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm;
1381 int err;
1382 /* commands available when embedded DSP is running */
1383 if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) {
1384 snd_iprintf(buffer, "no firmware loaded\n");
1385 return;
1386 }
1387 if (!mgr->capture_ltc) {
1388 pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL);
1389 rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE;
1390 err = pcxhr_send_msg(mgr, &rmh);
1391 if (err) {
1392 snd_iprintf(buffer, "ltc not activated (%d)\n", err);
1393 return;
1394 }
1395 if (mgr->is_hr_stereo)
1396 hr222_manage_timecode(mgr, 1);
1397 else
1398 pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE,
1399 REG_CONT_VALSMPTE, NULL);
1400 mgr->capture_ltc = 1;
1401 }
1402 pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE);
1403 err = pcxhr_send_msg(mgr, &rmh);
1404 if (err) {
1405 snd_iprintf(buffer, "ltc read error (err=%d)\n", err);
1406 return ;
1407 }
1408 ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf);
1409 ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf);
1410 ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf);
1411 ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf);
1412
1413 snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n",
1414 ltcHrs, ltcMin, ltcSec, ltcFrm);
1415 snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff,
1416 rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff);
1417 /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n",
1418 rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/
1419 if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) {
1420 snd_iprintf(buffer, "warning: linear timecode not valid\n");
1421 }
1422 }
1423
pcxhr_proc_init(struct snd_pcxhr * chip)1424 static void pcxhr_proc_init(struct snd_pcxhr *chip)
1425 {
1426 snd_card_ro_proc_new(chip->card, "info", chip, pcxhr_proc_info);
1427 snd_card_ro_proc_new(chip->card, "sync", chip, pcxhr_proc_sync);
1428 /* gpio available on stereo sound cards only */
1429 if (chip->mgr->is_hr_stereo)
1430 snd_card_rw_proc_new(chip->card, "gpio", chip,
1431 pcxhr_proc_gpio_read,
1432 pcxhr_proc_gpo_write);
1433 snd_card_ro_proc_new(chip->card, "ltc", chip, pcxhr_proc_ltc);
1434 }
1435 /* end of proc interface */
1436
1437 /*
1438 * release all the cards assigned to a manager instance
1439 */
pcxhr_free(struct pcxhr_mgr * mgr)1440 static int pcxhr_free(struct pcxhr_mgr *mgr)
1441 {
1442 unsigned int i;
1443
1444 for (i = 0; i < mgr->num_cards; i++) {
1445 if (mgr->chip[i])
1446 snd_card_free(mgr->chip[i]->card);
1447 }
1448
1449 /* reset board if some firmware was loaded */
1450 if(mgr->dsp_loaded) {
1451 pcxhr_reset_board(mgr);
1452 dev_dbg(&mgr->pci->dev, "reset pcxhr !\n");
1453 }
1454
1455 /* release irq */
1456 if (mgr->irq >= 0)
1457 free_irq(mgr->irq, mgr);
1458
1459 pci_release_regions(mgr->pci);
1460
1461 /* free hostport purgebuffer */
1462 if (mgr->hostport.area) {
1463 snd_dma_free_pages(&mgr->hostport);
1464 mgr->hostport.area = NULL;
1465 }
1466
1467 kfree(mgr->prmh);
1468
1469 pci_disable_device(mgr->pci);
1470 kfree(mgr);
1471 return 0;
1472 }
1473
1474 /*
1475 * probe function - creates the card manager
1476 */
pcxhr_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1477 static int pcxhr_probe(struct pci_dev *pci,
1478 const struct pci_device_id *pci_id)
1479 {
1480 static int dev;
1481 struct pcxhr_mgr *mgr;
1482 unsigned int i;
1483 int err;
1484 size_t size;
1485 char *card_name;
1486
1487 if (dev >= SNDRV_CARDS)
1488 return -ENODEV;
1489 if (! enable[dev]) {
1490 dev++;
1491 return -ENOENT;
1492 }
1493
1494 /* enable PCI device */
1495 if ((err = pci_enable_device(pci)) < 0)
1496 return err;
1497 pci_set_master(pci);
1498
1499 /* check if we can restrict PCI DMA transfers to 32 bits */
1500 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
1501 dev_err(&pci->dev,
1502 "architecture does not support 32bit PCI busmaster DMA\n");
1503 pci_disable_device(pci);
1504 return -ENXIO;
1505 }
1506
1507 /* alloc card manager */
1508 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1509 if (! mgr) {
1510 pci_disable_device(pci);
1511 return -ENOMEM;
1512 }
1513
1514 if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1515 kfree(mgr);
1516 pci_disable_device(pci);
1517 return -ENODEV;
1518 }
1519 card_name =
1520 pcxhr_board_params[pci_id->driver_data].board_name;
1521 mgr->playback_chips =
1522 pcxhr_board_params[pci_id->driver_data].playback_chips;
1523 mgr->capture_chips =
1524 pcxhr_board_params[pci_id->driver_data].capture_chips;
1525 mgr->fw_file_set =
1526 pcxhr_board_params[pci_id->driver_data].fw_file_set;
1527 mgr->firmware_num =
1528 pcxhr_board_params[pci_id->driver_data].firmware_num;
1529 mgr->mono_capture = mono[dev];
1530 mgr->is_hr_stereo = (mgr->playback_chips == 1);
1531 mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1532 mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1533
1534 if (mgr->is_hr_stereo)
1535 mgr->granularity = PCXHR_GRANULARITY_HR22;
1536 else
1537 mgr->granularity = PCXHR_GRANULARITY;
1538
1539 /* resource assignment */
1540 if ((err = pci_request_regions(pci, card_name)) < 0) {
1541 kfree(mgr);
1542 pci_disable_device(pci);
1543 return err;
1544 }
1545 for (i = 0; i < 3; i++)
1546 mgr->port[i] = pci_resource_start(pci, i);
1547
1548 mgr->pci = pci;
1549 mgr->irq = -1;
1550
1551 if (request_threaded_irq(pci->irq, pcxhr_interrupt,
1552 pcxhr_threaded_irq, IRQF_SHARED,
1553 KBUILD_MODNAME, mgr)) {
1554 dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq);
1555 pcxhr_free(mgr);
1556 return -EBUSY;
1557 }
1558 mgr->irq = pci->irq;
1559
1560 snprintf(mgr->name, sizeof(mgr->name),
1561 "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i",
1562 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1563
1564 /* ISR lock */
1565 mutex_init(&mgr->lock);
1566 mutex_init(&mgr->msg_lock);
1567
1568 /* init setup mutex*/
1569 mutex_init(&mgr->setup_mutex);
1570
1571 mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1572 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1573 PCXHR_SIZE_MAX_STATUS),
1574 GFP_KERNEL);
1575 if (! mgr->prmh) {
1576 pcxhr_free(mgr);
1577 return -ENOMEM;
1578 }
1579
1580 for (i=0; i < PCXHR_MAX_CARDS; i++) {
1581 struct snd_card *card;
1582 char tmpid[16];
1583 int idx;
1584
1585 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1586 break;
1587 mgr->num_cards++;
1588
1589 if (index[dev] < 0)
1590 idx = index[dev];
1591 else
1592 idx = index[dev] + i;
1593
1594 snprintf(tmpid, sizeof(tmpid), "%s-%d",
1595 id[dev] ? id[dev] : card_name, i);
1596 err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE,
1597 0, &card);
1598
1599 if (err < 0) {
1600 dev_err(&pci->dev, "cannot allocate the card %d\n", i);
1601 pcxhr_free(mgr);
1602 return err;
1603 }
1604
1605 strcpy(card->driver, DRIVER_NAME);
1606 snprintf(card->shortname, sizeof(card->shortname),
1607 "Digigram [PCM #%d]", i);
1608 snprintf(card->longname, sizeof(card->longname),
1609 "%s [PCM #%d]", mgr->name, i);
1610
1611 if ((err = pcxhr_create(mgr, card, i)) < 0) {
1612 snd_card_free(card);
1613 pcxhr_free(mgr);
1614 return err;
1615 }
1616
1617 if (i == 0)
1618 /* init proc interface only for chip0 */
1619 pcxhr_proc_init(mgr->chip[i]);
1620
1621 if ((err = snd_card_register(card)) < 0) {
1622 pcxhr_free(mgr);
1623 return err;
1624 }
1625 }
1626
1627 /* create hostport purgebuffer */
1628 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1629 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
1630 size, &mgr->hostport) < 0) {
1631 pcxhr_free(mgr);
1632 return -ENOMEM;
1633 }
1634 /* init purgebuffer */
1635 memset(mgr->hostport.area, 0, size);
1636
1637 /* create a DSP loader */
1638 err = pcxhr_setup_firmware(mgr);
1639 if (err < 0) {
1640 pcxhr_free(mgr);
1641 return err;
1642 }
1643
1644 pci_set_drvdata(pci, mgr);
1645 dev++;
1646 return 0;
1647 }
1648
pcxhr_remove(struct pci_dev * pci)1649 static void pcxhr_remove(struct pci_dev *pci)
1650 {
1651 pcxhr_free(pci_get_drvdata(pci));
1652 }
1653
1654 static struct pci_driver pcxhr_driver = {
1655 .name = KBUILD_MODNAME,
1656 .id_table = pcxhr_ids,
1657 .probe = pcxhr_probe,
1658 .remove = pcxhr_remove,
1659 };
1660
1661 module_pci_driver(pcxhr_driver);
1662