1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // JZ4740 CODEC driver
4 //
5 // Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
6 
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/io.h>
12 #include <linux/regmap.h>
13 
14 #include <linux/delay.h>
15 
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/initval.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 
23 #define JZ4740_REG_CODEC_1 0x0
24 #define JZ4740_REG_CODEC_2 0x4
25 
26 #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
27 #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
28 #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
29 #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
30 #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
31 #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
32 #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
33 #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
34 #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
35 #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
36 #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
37 #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
38 #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
39 #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
40 #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
41 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
42 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
43 #define JZ4740_CODEC_1_SUSPEND BIT(1)
44 #define JZ4740_CODEC_1_RESET BIT(0)
45 
46 #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
47 #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
48 #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
49 #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
50 #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
51 #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
52 #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
53 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
54 
55 #define JZ4740_CODEC_2_INPUT_VOLUME_MASK		0x1f0000
56 #define JZ4740_CODEC_2_SAMPLE_RATE_MASK			0x000f00
57 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK		0x000030
58 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK	0x000003
59 
60 #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET		16
61 #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET		 8
62 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET	 4
63 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET	 0
64 
65 static const struct reg_default jz4740_codec_reg_defaults[] = {
66 	{ JZ4740_REG_CODEC_1, 0x021b2302 },
67 	{ JZ4740_REG_CODEC_2, 0x00170803 },
68 };
69 
70 struct jz4740_codec {
71 	struct regmap *regmap;
72 };
73 
74 static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv,
75 	0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
76 	3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0)
77 );
78 
79 static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
80 static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
81 
82 static const struct snd_kcontrol_new jz4740_codec_controls[] = {
83 	SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
84 			JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
85 			jz4740_out_tlv),
86 	SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
87 			JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
88 			jz4740_in_tlv),
89 	SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
90 			JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
91 	SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
92 			JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
93 			jz4740_mic_tlv),
94 };
95 
96 static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
97 	SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
98 			JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
99 	SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
100 			JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
101 };
102 
103 static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
104 	SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
105 			JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
106 	SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
107 			JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
108 };
109 
110 static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
111 	SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
112 			JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
113 	SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
114 			JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
115 
116 	SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
117 			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
118 			jz4740_codec_output_controls,
119 			ARRAY_SIZE(jz4740_codec_output_controls)),
120 
121 	SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
122 			jz4740_codec_input_controls,
123 			ARRAY_SIZE(jz4740_codec_input_controls)),
124 	SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
125 
126 	SND_SOC_DAPM_OUTPUT("LOUT"),
127 	SND_SOC_DAPM_OUTPUT("ROUT"),
128 
129 	SND_SOC_DAPM_INPUT("MIC"),
130 	SND_SOC_DAPM_INPUT("LIN"),
131 	SND_SOC_DAPM_INPUT("RIN"),
132 };
133 
134 static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
135 	{"Line Input", NULL, "LIN"},
136 	{"Line Input", NULL, "RIN"},
137 
138 	{"Input Mixer", "Line Capture Switch", "Line Input"},
139 	{"Input Mixer", "Mic Capture Switch", "MIC"},
140 
141 	{"ADC", NULL, "Input Mixer"},
142 
143 	{"Output Mixer", "Bypass Switch", "Input Mixer"},
144 	{"Output Mixer", "DAC Switch", "DAC"},
145 
146 	{"LOUT", NULL, "Output Mixer"},
147 	{"ROUT", NULL, "Output Mixer"},
148 };
149 
jz4740_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)150 static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
151 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
152 {
153 	struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(dai->component);
154 	uint32_t val;
155 
156 	switch (params_rate(params)) {
157 	case 8000:
158 		val = 0;
159 		break;
160 	case 11025:
161 		val = 1;
162 		break;
163 	case 12000:
164 		val = 2;
165 		break;
166 	case 16000:
167 		val = 3;
168 		break;
169 	case 22050:
170 		val = 4;
171 		break;
172 	case 24000:
173 		val = 5;
174 		break;
175 	case 32000:
176 		val = 6;
177 		break;
178 	case 44100:
179 		val = 7;
180 		break;
181 	case 48000:
182 		val = 8;
183 		break;
184 	default:
185 		return -EINVAL;
186 	}
187 
188 	val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
189 
190 	regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
191 				JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
192 
193 	return 0;
194 }
195 
196 static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
197 	.hw_params = jz4740_codec_hw_params,
198 };
199 
200 static struct snd_soc_dai_driver jz4740_codec_dai = {
201 	.name = "jz4740-hifi",
202 	.playback = {
203 		.stream_name = "Playback",
204 		.channels_min = 2,
205 		.channels_max = 2,
206 		.rates = SNDRV_PCM_RATE_8000_48000,
207 		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
208 	},
209 	.capture = {
210 		.stream_name = "Capture",
211 		.channels_min = 2,
212 		.channels_max = 2,
213 		.rates = SNDRV_PCM_RATE_8000_48000,
214 		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
215 	},
216 	.ops = &jz4740_codec_dai_ops,
217 	.symmetric_rate = 1,
218 };
219 
jz4740_codec_wakeup(struct regmap * regmap)220 static void jz4740_codec_wakeup(struct regmap *regmap)
221 {
222 	regmap_set_bits(regmap, JZ4740_REG_CODEC_1, JZ4740_CODEC_1_RESET);
223 	udelay(2);
224 
225 	regmap_clear_bits(regmap, JZ4740_REG_CODEC_1,
226 			  JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET);
227 
228 	regcache_sync(regmap);
229 }
230 
jz4740_codec_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)231 static int jz4740_codec_set_bias_level(struct snd_soc_component *component,
232 	enum snd_soc_bias_level level)
233 {
234 	struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
235 	struct regmap *regmap = jz4740_codec->regmap;
236 	unsigned int mask;
237 
238 	switch (level) {
239 	case SND_SOC_BIAS_ON:
240 		break;
241 	case SND_SOC_BIAS_PREPARE:
242 		mask = JZ4740_CODEC_1_VREF_DISABLE |
243 				JZ4740_CODEC_1_VREF_AMP_DISABLE |
244 				JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
245 
246 		regmap_clear_bits(regmap, JZ4740_REG_CODEC_1, mask);
247 		break;
248 	case SND_SOC_BIAS_STANDBY:
249 		/* The only way to clear the suspend flag is to reset the codec */
250 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
251 			jz4740_codec_wakeup(regmap);
252 
253 		mask = JZ4740_CODEC_1_VREF_DISABLE |
254 			JZ4740_CODEC_1_VREF_AMP_DISABLE |
255 			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
256 
257 		regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask);
258 		break;
259 	case SND_SOC_BIAS_OFF:
260 		mask = JZ4740_CODEC_1_SUSPEND;
261 		regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask);
262 		regcache_mark_dirty(regmap);
263 		break;
264 	default:
265 		break;
266 	}
267 
268 	return 0;
269 }
270 
jz4740_codec_dev_probe(struct snd_soc_component * component)271 static int jz4740_codec_dev_probe(struct snd_soc_component *component)
272 {
273 	struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
274 
275 	regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
276 			JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
277 
278 	return 0;
279 }
280 
281 static const struct snd_soc_component_driver soc_codec_dev_jz4740_codec = {
282 	.probe			= jz4740_codec_dev_probe,
283 	.set_bias_level		= jz4740_codec_set_bias_level,
284 	.controls		= jz4740_codec_controls,
285 	.num_controls		= ARRAY_SIZE(jz4740_codec_controls),
286 	.dapm_widgets		= jz4740_codec_dapm_widgets,
287 	.num_dapm_widgets	= ARRAY_SIZE(jz4740_codec_dapm_widgets),
288 	.dapm_routes		= jz4740_codec_dapm_routes,
289 	.num_dapm_routes	= ARRAY_SIZE(jz4740_codec_dapm_routes),
290 	.suspend_bias_off	= 1,
291 	.idle_bias_on		= 1,
292 	.use_pmdown_time	= 1,
293 	.endianness		= 1,
294 	.non_legacy_dai_naming	= 1,
295 
296 };
297 
298 static const struct regmap_config jz4740_codec_regmap_config = {
299 	.reg_bits = 32,
300 	.reg_stride = 4,
301 	.val_bits = 32,
302 	.max_register = JZ4740_REG_CODEC_2,
303 
304 	.reg_defaults = jz4740_codec_reg_defaults,
305 	.num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
306 	.cache_type = REGCACHE_RBTREE,
307 };
308 
jz4740_codec_probe(struct platform_device * pdev)309 static int jz4740_codec_probe(struct platform_device *pdev)
310 {
311 	int ret;
312 	struct jz4740_codec *jz4740_codec;
313 	void __iomem *base;
314 
315 	jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
316 				    GFP_KERNEL);
317 	if (!jz4740_codec)
318 		return -ENOMEM;
319 
320 	base = devm_platform_ioremap_resource(pdev, 0);
321 	if (IS_ERR(base))
322 		return PTR_ERR(base);
323 
324 	jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
325 					    &jz4740_codec_regmap_config);
326 	if (IS_ERR(jz4740_codec->regmap))
327 		return PTR_ERR(jz4740_codec->regmap);
328 
329 	platform_set_drvdata(pdev, jz4740_codec);
330 
331 	ret = devm_snd_soc_register_component(&pdev->dev,
332 			&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
333 	if (ret)
334 		dev_err(&pdev->dev, "Failed to register codec\n");
335 
336 	return ret;
337 }
338 
339 static const struct of_device_id jz4740_codec_of_matches[] = {
340 	{ .compatible = "ingenic,jz4740-codec", },
341 	{ }
342 };
343 MODULE_DEVICE_TABLE(of, jz4740_codec_of_matches);
344 
345 static struct platform_driver jz4740_codec_driver = {
346 	.probe = jz4740_codec_probe,
347 	.driver = {
348 		.name = "jz4740-codec",
349 		.of_match_table = jz4740_codec_of_matches,
350 	},
351 };
352 
353 module_platform_driver(jz4740_codec_driver);
354 
355 MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
356 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
357 MODULE_LICENSE("GPL v2");
358 MODULE_ALIAS("platform:jz4740-codec");
359