1// cmd/7c/7.out.h from Vita Nuova. 2// https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3// 4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6// Portions Copyright © 1997-1999 Vita Nuova Limited 7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8// Portions Copyright © 2004,2006 Bruce Ellis 9// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11// Portions Copyright © 2009 The Go Authors. All rights reserved. 12// 13// Permission is hereby granted, free of charge, to any person obtaining a copy 14// of this software and associated documentation files (the "Software"), to deal 15// in the Software without restriction, including without limitation the rights 16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17// copies of the Software, and to permit persons to whom the Software is 18// furnished to do so, subject to the following conditions: 19// 20// The above copyright notice and this permission notice shall be included in 21// all copies or substantial portions of the Software. 22// 23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29// THE SOFTWARE. 30 31package arm64 32 33import "cmd/internal/obj" 34 35const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40) 41 42// General purpose registers, kept in the low bits of Prog.Reg. 43const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 // The EQ in 147 // CSET EQ, R0 148 // is encoded as TYPE_REG, even though it's not really a register. 149 COND_EQ 150 COND_NE 151 COND_HS 152 COND_LO 153 COND_MI 154 COND_PL 155 COND_VS 156 COND_VC 157 COND_HI 158 COND_LS 159 COND_GE 160 COND_LT 161 COND_GT 162 COND_LE 163 COND_AL 164 COND_NV 165 166 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 167) 168 169// Not registers, but flags that can be combined with regular register 170// constants to indicate extended register conversion. When checking, 171// you should subtract obj.RBaseARM64 first. From this difference, bit 11 172// indicates extended register, bits 8-10 select the conversion mode. 173const REG_EXT = obj.RBaseARM64 + 1<<11 174 175const ( 176 REG_UXTB = REG_EXT + iota<<8 177 REG_UXTH 178 REG_UXTW 179 REG_UXTX 180 REG_SXTB 181 REG_SXTH 182 REG_SXTW 183 REG_SXTX 184) 185 186// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 187// a special register and the low bits select the register. 188const ( 189 REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota 190 REG_DAIF 191 REG_NZCV 192 REG_FPSR 193 REG_FPCR 194 REG_SPSR_EL1 195 REG_ELR_EL1 196 REG_SPSR_EL2 197 REG_ELR_EL2 198 REG_CurrentEL 199 REG_SP_EL0 200 REG_SPSel 201 REG_DAIFSet 202 REG_DAIFClr 203) 204 205// Register assignments: 206// 207// compiler allocates R0 up as temps 208// compiler allocates register variables R7-R25 209// compiler allocates external registers R26 down 210// 211// compiler allocates register variables F7-F26 212// compiler allocates external registers F26 down 213const ( 214 REGMIN = REG_R7 // register variables allocated from here to REGMAX 215 REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy 216 REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy 217 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 218 REGMAX = REG_R25 219 220 REGCTXT = REG_R26 // environment for closures 221 REGTMP = REG_R27 // reserved for liblink 222 REGG = REG_R28 // G 223 REGFP = REG_R29 // frame pointer, unused in the Go toolchain 224 REGLINK = REG_R30 225 226 // ARM64 uses R31 as both stack pointer and zero register, 227 // depending on the instruction. To differentiate RSP from ZR, 228 // we use a different numeric value for REGZERO and REGSP. 229 REGZERO = REG_R31 230 REGSP = REG_RSP 231 232 FREGRET = REG_F0 233 FREGMIN = REG_F7 // first register variable 234 FREGMAX = REG_F26 // last register variable for 7g only 235 FREGEXT = REG_F26 // first external register 236) 237 238const ( 239 BIG = 2048 - 8 240) 241 242const ( 243 /* mark flags */ 244 LABEL = 1 << iota 245 LEAF 246 FLOAT 247 BRANCH 248 LOAD 249 FCMP 250 SYNC 251 LIST 252 FOLL 253 NOSCHED 254) 255 256const ( 257 // optab is sorted based on the order of these constants 258 // and the first match is chosen. 259 // The more specific class needs to come earlier. 260 C_NONE = iota 261 C_REG // R0..R30 262 C_RSP // R0..R30, RSP 263 C_FREG // F0..F31 264 C_VREG // V0..V31 265 C_PAIR // (Rn, Rm) 266 C_SHIFT // Rn<<2 267 C_EXTREG // Rn.UXTB<<3 268 C_SPR // REG_NZCV 269 C_COND // EQ, NE, etc 270 271 C_ZCON // $0 or ZR 272 C_ABCON0 // could be C_ADDCON0 or C_BITCON 273 C_ADDCON0 // 12-bit unsigned, unshifted 274 C_ABCON // could be C_ADDCON or C_BITCON 275 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 276 C_MBCON // could be C_MOVCON or C_BITCON 277 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 278 C_BITCON // bitfield and logical immediate masks 279 C_LCON // 32-bit constant 280 C_VCON // 64-bit constant 281 C_FCON // floating-point constant 282 C_VCONADDR // 64-bit memory address 283 284 C_AACON // ADDCON offset in auto constant $a(FP) 285 C_LACON // 32-bit offset in auto constant $a(FP) 286 C_AECON // ADDCON offset in extern constant $e(SB) 287 288 // TODO(aram): only one branch class should be enough 289 C_SBRA // for TYPE_BRANCH 290 C_LBRA 291 292 C_NPAUTO // -512 <= x < 0, 0 mod 8 293 C_NSAUTO // -256 <= x < 0 294 C_PSAUTO // 0 to 255 295 C_PPAUTO // 0 to 504, 0 mod 8 296 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 297 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 298 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 299 C_UAUTO4K // 0 to 4095 300 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 301 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 302 C_UAUTO8K // 0 to 8190, 0 mod 2 303 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 304 C_UAUTO16K // 0 to 16380, 0 mod 4 305 C_UAUTO32K // 0 to 32760, 0 mod 8 306 C_LAUTO // any other 32-bit constant 307 308 C_SEXT1 // 0 to 4095, direct 309 C_SEXT2 // 0 to 8190 310 C_SEXT4 // 0 to 16380 311 C_SEXT8 // 0 to 32760 312 C_SEXT16 // 0 to 65520 313 C_LEXT 314 315 C_ZOREG // 0(R) 316 C_NPOREG // must mirror NPAUTO, etc 317 C_NSOREG 318 C_PSOREG 319 C_PPOREG 320 C_UOREG4K_8 321 C_UOREG4K_4 322 C_UOREG4K_2 323 C_UOREG4K 324 C_UOREG8K_8 325 C_UOREG8K_4 326 C_UOREG8K 327 C_UOREG16K_8 328 C_UOREG16K 329 C_UOREG32K 330 C_LOREG 331 332 C_ADDR // TODO(aram): explain difference from C_VCONADDR 333 334 // The GOT slot for a symbol in -dynlink mode. 335 C_GOTADDR 336 337 // TLS "var" in local exec mode: will become a constant offset from 338 // thread local base that is ultimately chosen by the program linker. 339 C_TLS_LE 340 341 // TLS "var" in initial exec mode: will become a memory address (chosen 342 // by the program linker) that the dynamic linker will fill with the 343 // offset from the thread local base. 344 C_TLS_IE 345 346 C_ROFF // register offset (including register extended) 347 348 C_GOK 349 C_TEXTSIZE 350 C_NCLASS // must be last 351) 352 353const ( 354 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 355 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 356) 357 358//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 359 360const ( 361 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 362 AADCS 363 AADCSW 364 AADCW 365 AADD 366 AADDS 367 AADDSW 368 AADDW 369 AADR 370 AADRP 371 AAND 372 AANDS 373 AANDSW 374 AANDW 375 AASR 376 AASRW 377 AAT 378 ABFI 379 ABFIW 380 ABFM 381 ABFMW 382 ABFXIL 383 ABFXILW 384 ABIC 385 ABICS 386 ABICSW 387 ABICW 388 ABRK 389 ACBNZ 390 ACBNZW 391 ACBZ 392 ACBZW 393 ACCMN 394 ACCMNW 395 ACCMP 396 ACCMPW 397 ACINC 398 ACINCW 399 ACINV 400 ACINVW 401 ACLREX 402 ACLS 403 ACLSW 404 ACLZ 405 ACLZW 406 ACMN 407 ACMNW 408 ACMP 409 ACMPW 410 ACNEG 411 ACNEGW 412 ACRC32B 413 ACRC32CB 414 ACRC32CH 415 ACRC32CW 416 ACRC32CX 417 ACRC32H 418 ACRC32W 419 ACRC32X 420 ACSEL 421 ACSELW 422 ACSET 423 ACSETM 424 ACSETMW 425 ACSETW 426 ACSINC 427 ACSINCW 428 ACSINV 429 ACSINVW 430 ACSNEG 431 ACSNEGW 432 ADC 433 ADCPS1 434 ADCPS2 435 ADCPS3 436 ADMB 437 ADRPS 438 ADSB 439 AEON 440 AEONW 441 AEOR 442 AEORW 443 AERET 444 AEXTR 445 AEXTRW 446 AHINT 447 AHLT 448 AHVC 449 AIC 450 AISB 451 ALDAR 452 ALDARB 453 ALDARH 454 ALDARW 455 ALDAXP 456 ALDAXPW 457 ALDAXR 458 ALDAXRB 459 ALDAXRH 460 ALDAXRW 461 ALDP 462 ALDXR 463 ALDXRB 464 ALDXRH 465 ALDXRW 466 ALDXP 467 ALDXPW 468 ALSL 469 ALSLW 470 ALSR 471 ALSRW 472 AMADD 473 AMADDW 474 AMNEG 475 AMNEGW 476 AMOVK 477 AMOVKW 478 AMOVN 479 AMOVNW 480 AMOVZ 481 AMOVZW 482 AMRS 483 AMSR 484 AMSUB 485 AMSUBW 486 AMUL 487 AMULW 488 AMVN 489 AMVNW 490 ANEG 491 ANEGS 492 ANEGSW 493 ANEGW 494 ANGC 495 ANGCS 496 ANGCSW 497 ANGCW 498 AORN 499 AORNW 500 AORR 501 AORRW 502 APRFM 503 APRFUM 504 ARBIT 505 ARBITW 506 AREM 507 AREMW 508 AREV 509 AREV16 510 AREV16W 511 AREV32 512 AREVW 513 AROR 514 ARORW 515 ASBC 516 ASBCS 517 ASBCSW 518 ASBCW 519 ASBFIZ 520 ASBFIZW 521 ASBFM 522 ASBFMW 523 ASBFX 524 ASBFXW 525 ASDIV 526 ASDIVW 527 ASEV 528 ASEVL 529 ASMADDL 530 ASMC 531 ASMNEGL 532 ASMSUBL 533 ASMULH 534 ASMULL 535 ASTXR 536 ASTXRB 537 ASTXRH 538 ASTXP 539 ASTXPW 540 ASTXRW 541 ASTLP 542 ASTLPW 543 ASTLR 544 ASTLRB 545 ASTLRH 546 ASTLRW 547 ASTLXP 548 ASTLXPW 549 ASTLXR 550 ASTLXRB 551 ASTLXRH 552 ASTLXRW 553 ASTP 554 ASUB 555 ASUBS 556 ASUBSW 557 ASUBW 558 ASVC 559 ASXTB 560 ASXTBW 561 ASXTH 562 ASXTHW 563 ASXTW 564 ASYS 565 ASYSL 566 ATBNZ 567 ATBZ 568 ATLBI 569 ATST 570 ATSTW 571 AUBFIZ 572 AUBFIZW 573 AUBFM 574 AUBFMW 575 AUBFX 576 AUBFXW 577 AUDIV 578 AUDIVW 579 AUMADDL 580 AUMNEGL 581 AUMSUBL 582 AUMULH 583 AUMULL 584 AUREM 585 AUREMW 586 AUXTB 587 AUXTH 588 AUXTW 589 AUXTBW 590 AUXTHW 591 AWFE 592 AWFI 593 AYIELD 594 AMOVB 595 AMOVBU 596 AMOVH 597 AMOVHU 598 AMOVW 599 AMOVWU 600 AMOVD 601 AMOVNP 602 AMOVNPW 603 AMOVP 604 AMOVPD 605 AMOVPQ 606 AMOVPS 607 AMOVPSW 608 AMOVPW 609 ABEQ 610 ABNE 611 ABCS 612 ABHS 613 ABCC 614 ABLO 615 ABMI 616 ABPL 617 ABVS 618 ABVC 619 ABHI 620 ABLS 621 ABGE 622 ABLT 623 ABGT 624 ABLE 625 AFABSD 626 AFABSS 627 AFADDD 628 AFADDS 629 AFCCMPD 630 AFCCMPED 631 AFCCMPS 632 AFCCMPES 633 AFCMPD 634 AFCMPED 635 AFCMPES 636 AFCMPS 637 AFCVTSD 638 AFCVTDS 639 AFCVTZSD 640 AFCVTZSDW 641 AFCVTZSS 642 AFCVTZSSW 643 AFCVTZUD 644 AFCVTZUDW 645 AFCVTZUS 646 AFCVTZUSW 647 AFDIVD 648 AFDIVS 649 AFMOVD 650 AFMOVS 651 AFMULD 652 AFMULS 653 AFNEGD 654 AFNEGS 655 AFSQRTD 656 AFSQRTS 657 AFSUBD 658 AFSUBS 659 ASCVTFD 660 ASCVTFS 661 ASCVTFWD 662 ASCVTFWS 663 AUCVTFD 664 AUCVTFS 665 AUCVTFWD 666 AUCVTFWS 667 AWORD 668 ADWORD 669 AFCSELS 670 AFCSELD 671 AFMAXS 672 AFMINS 673 AFMAXD 674 AFMIND 675 AFMAXNMS 676 AFMAXNMD 677 AFNMULS 678 AFNMULD 679 AFRINTNS 680 AFRINTND 681 AFRINTPS 682 AFRINTPD 683 AFRINTMS 684 AFRINTMD 685 AFRINTZS 686 AFRINTZD 687 AFRINTAS 688 AFRINTAD 689 AFRINTXS 690 AFRINTXD 691 AFRINTIS 692 AFRINTID 693 AFMADDS 694 AFMADDD 695 AFMSUBS 696 AFMSUBD 697 AFNMADDS 698 AFNMADDD 699 AFNMSUBS 700 AFNMSUBD 701 AFMINNMS 702 AFMINNMD 703 AFCVTDH 704 AFCVTHS 705 AFCVTHD 706 AFCVTSH 707 AAESD 708 AAESE 709 AAESIMC 710 AAESMC 711 ASHA1C 712 ASHA1H 713 ASHA1M 714 ASHA1P 715 ASHA1SU0 716 ASHA1SU1 717 ASHA256H 718 ASHA256H2 719 ASHA256SU0 720 ASHA256SU1 721 ALAST 722 AB = obj.AJMP 723 ABL = obj.ACALL 724) 725 726const ( 727 // shift types 728 SHIFT_LL = 0 << 22 729 SHIFT_LR = 1 << 22 730 SHIFT_AR = 2 << 22 731) 732