1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include <ipxe/io.h>
20
21 #include "hw.h"
22 #include "ar9003_mac.h"
23
ar9003_hw_rx_enable(struct ath_hw * hw)24 static void ar9003_hw_rx_enable(struct ath_hw *hw)
25 {
26 REG_WRITE(hw, AR_CR, 0);
27 }
28
ar9003_calc_ptr_chksum(struct ar9003_txc * ads)29 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
30 {
31 int checksum;
32
33 checksum = ads->info + ads->link
34 + ads->data0 + ads->ctl3
35 + ads->data1 + ads->ctl5
36 + ads->data2 + ads->ctl7
37 + ads->data3 + ads->ctl9;
38
39 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
40 }
41
ar9003_hw_set_desc_link(void * ds,u32 ds_link)42 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
43 {
44 struct ar9003_txc *ads = ds;
45
46 ads->link = ds_link;
47 ads->ctl10 &= ~AR_TxPtrChkSum;
48 ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
49 }
50
ar9003_hw_get_desc_link(void * ds,u32 ** ds_link)51 static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
52 {
53 struct ar9003_txc *ads = ds;
54
55 *ds_link = &ads->link;
56 }
57
ar9003_hw_get_isr(struct ath_hw * ah,enum ath9k_int * masked)58 static int ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
59 {
60 u32 isr = 0;
61 u32 mask2 = 0;
62 struct ath9k_hw_capabilities *pCap = &ah->caps;
63 u32 sync_cause = 0;
64
65 if (ah->ah_ier & AR_IER_ENABLE) {
66 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
67 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
68 == AR_RTC_STATUS_ON)
69 isr = REG_READ(ah, AR_ISR);
70 }
71
72 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
73
74 *masked = 0;
75
76 if (!isr && !sync_cause)
77 return 0;
78 } else {
79 *masked = 0;
80 isr = REG_READ(ah, AR_ISR);
81 }
82
83 if (isr) {
84 if (isr & AR_ISR_BCNMISC) {
85 u32 isr2;
86 isr2 = REG_READ(ah, AR_ISR_S2);
87
88 mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
89 MAP_ISR_S2_TIM);
90 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
91 MAP_ISR_S2_DTIM);
92 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
93 MAP_ISR_S2_DTIMSYNC);
94 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
95 MAP_ISR_S2_CABEND);
96 mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
97 MAP_ISR_S2_GTT);
98 mask2 |= ((isr2 & AR_ISR_S2_CST) <<
99 MAP_ISR_S2_CST);
100 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
101 MAP_ISR_S2_TSFOOR);
102 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
103 MAP_ISR_S2_BB_WATCHDOG);
104
105 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
106 REG_WRITE(ah, AR_ISR_S2, isr2);
107 isr &= ~AR_ISR_BCNMISC;
108 }
109 }
110
111 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
112 isr = REG_READ(ah, AR_ISR_RAC);
113
114 if (isr == 0xffffffff) {
115 *masked = 0;
116 return 0;
117 }
118
119 *masked = isr & ATH9K_INT_COMMON;
120
121 if (ah->config.rx_intr_mitigation)
122 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
123 *masked |= ATH9K_INT_RXLP;
124
125 if (ah->config.tx_intr_mitigation)
126 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
127 *masked |= ATH9K_INT_TX;
128
129 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
130 *masked |= ATH9K_INT_RXLP;
131
132 if (isr & AR_ISR_HP_RXOK)
133 *masked |= ATH9K_INT_RXHP;
134
135 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
136 *masked |= ATH9K_INT_TX;
137
138 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
139 u32 s0, s1;
140 s0 = REG_READ(ah, AR_ISR_S0);
141 REG_WRITE(ah, AR_ISR_S0, s0);
142 s1 = REG_READ(ah, AR_ISR_S1);
143 REG_WRITE(ah, AR_ISR_S1, s1);
144
145 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
146 AR_ISR_TXEOL);
147 }
148 }
149
150 if (isr & AR_ISR_GENTMR) {
151 u32 s5;
152
153 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
154 s5 = REG_READ(ah, AR_ISR_S5_S);
155 else
156 s5 = REG_READ(ah, AR_ISR_S5);
157
158 ah->intr_gen_timer_trigger =
159 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
160
161 ah->intr_gen_timer_thresh =
162 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
163
164 if (ah->intr_gen_timer_trigger)
165 *masked |= ATH9K_INT_GENTIMER;
166
167 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
168 REG_WRITE(ah, AR_ISR_S5, s5);
169 isr &= ~AR_ISR_GENTMR;
170 }
171
172 }
173
174 *masked |= mask2;
175
176 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
177 REG_WRITE(ah, AR_ISR, isr);
178
179 (void) REG_READ(ah, AR_ISR);
180 }
181 }
182
183 if (sync_cause) {
184 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
185 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
186 REG_WRITE(ah, AR_RC, 0);
187 *masked |= ATH9K_INT_FATAL;
188 }
189
190 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
191 DBG("ath9k: "
192 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
193
194 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
195 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
196
197 }
198 return 1;
199 }
200
ar9003_hw_fill_txdesc(struct ath_hw * ah __unused,void * ds,u32 seglen,int is_firstseg,int is_lastseg,const void * ds0,u32 buf_addr,unsigned int qcu)201 static void ar9003_hw_fill_txdesc(struct ath_hw *ah __unused, void *ds, u32 seglen,
202 int is_firstseg, int is_lastseg,
203 const void *ds0, u32 buf_addr,
204 unsigned int qcu)
205 {
206 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
207 unsigned int descid = 0;
208
209 ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
210 (1 << AR_TxRxDesc_S) |
211 (1 << AR_CtrlStat_S) |
212 (qcu << AR_TxQcuNum_S) | 0x17;
213
214 ads->data0 = buf_addr;
215 ads->data1 = 0;
216 ads->data2 = 0;
217 ads->data3 = 0;
218
219 ads->ctl3 = (seglen << AR_BufLen_S);
220 ads->ctl3 &= AR_BufLen;
221
222 /* Fill in pointer checksum and descriptor id */
223 ads->ctl10 = ar9003_calc_ptr_chksum(ads);
224 ads->ctl10 |= (descid << AR_TxDescId_S);
225
226 if (is_firstseg) {
227 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
228 } else if (is_lastseg) {
229 ads->ctl11 = 0;
230 ads->ctl12 = 0;
231 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
232 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
233 } else {
234 /* XXX Intermediate descriptor in a multi-descriptor frame.*/
235 ads->ctl11 = 0;
236 ads->ctl12 = AR_TxMore;
237 ads->ctl13 = 0;
238 ads->ctl14 = 0;
239 }
240 }
241
ar9003_hw_proc_txdesc(struct ath_hw * ah,void * ds __unused,struct ath_tx_status * ts)242 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds __unused,
243 struct ath_tx_status *ts)
244 {
245 struct ar9003_txs *ads;
246 u32 status;
247
248 ads = &ah->ts_ring[ah->ts_tail];
249
250 status = *(volatile typeof(ads->status8) *)&(ads->status8);
251 if ((status & AR_TxDone) == 0)
252 return -EINPROGRESS;
253
254 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
255
256 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
257 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
258 DBG("ath9k: "
259 "Tx Descriptor error %x\n", ads->ds_info);
260 memset(ads, 0, sizeof(*ads));
261 return -EIO;
262 }
263
264 if (status & AR_TxOpExceeded)
265 ts->ts_status |= ATH9K_TXERR_XTXOP;
266 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
267 ts->ts_seqnum = MS(status, AR_SeqNum);
268 ts->tid = MS(status, AR_TxTid);
269
270 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
271 ts->desc_id = MS(ads->status1, AR_TxDescId);
272 ts->ts_tstamp = ads->status4;
273 ts->ts_status = 0;
274 ts->ts_flags = 0;
275
276 status = *(volatile typeof(ads->status2) *)&(ads->status2);
277 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
278 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
279 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
280 if (status & AR_TxBaStatus) {
281 ts->ts_flags |= ATH9K_TX_BA;
282 ts->ba_low = ads->status5;
283 ts->ba_high = ads->status6;
284 }
285
286 status = *(volatile typeof(ads->status3) *)&(ads->status3);
287 if (status & AR_ExcessiveRetries)
288 ts->ts_status |= ATH9K_TXERR_XRETRY;
289 if (status & AR_Filtered)
290 ts->ts_status |= ATH9K_TXERR_FILT;
291 if (status & AR_FIFOUnderrun) {
292 ts->ts_status |= ATH9K_TXERR_FIFO;
293 ath9k_hw_updatetxtriglevel(ah, 1);
294 }
295 if (status & AR_TxTimerExpired)
296 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
297 if (status & AR_DescCfgErr)
298 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
299 if (status & AR_TxDataUnderrun) {
300 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
301 ath9k_hw_updatetxtriglevel(ah, 1);
302 }
303 if (status & AR_TxDelimUnderrun) {
304 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
305 ath9k_hw_updatetxtriglevel(ah, 1);
306 }
307 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
308 ts->ts_longretry = MS(status, AR_DataFailCnt);
309 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
310
311 status = *(volatile typeof(ads->status7) *)&(ads->status7);
312 ts->ts_rssi = MS(status, AR_TxRSSICombined);
313 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
314 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
315 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
316
317 memset(ads, 0, sizeof(*ads));
318
319 return 0;
320 }
321
ar9003_hw_set11n_txdesc(struct ath_hw * ah,void * ds,u32 pktlen,enum ath9k_pkt_type type,u32 txpower,u32 keyIx,enum ath9k_key_type keyType,u32 flags)322 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
323 u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
324 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
325 {
326 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
327
328 if (txpower > ah->txpower_limit)
329 txpower = ah->txpower_limit;
330
331 if (txpower > 63)
332 txpower = 63;
333
334 ads->ctl11 = (pktlen & AR_FrameLen)
335 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
336 | SM(txpower, AR_XmitPower)
337 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
338 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
339 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
340
341 ads->ctl12 =
342 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
343 | SM(type, AR_FrameType)
344 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
345 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
346 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
347
348 ads->ctl17 = SM(keyType, AR_EncrType) |
349 (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
350 ads->ctl18 = 0;
351 ads->ctl19 = AR_Not_Sounding;
352
353 ads->ctl20 = 0;
354 ads->ctl21 = 0;
355 ads->ctl22 = 0;
356 }
357
ar9003_hw_set_clrdmask(struct ath_hw * ah __unused,void * ds,int val)358 static void ar9003_hw_set_clrdmask(struct ath_hw *ah __unused, void *ds, int val)
359 {
360 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
361
362 if (val)
363 ads->ctl11 |= AR_ClrDestMask;
364 else
365 ads->ctl11 &= ~AR_ClrDestMask;
366 }
367
ar9003_hw_set11n_ratescenario(struct ath_hw * ah __unused,void * ds,void * lastds,u32 durUpdateEn,u32 rtsctsRate,u32 rtsctsDuration __unused,struct ath9k_11n_rate_series series[],u32 nseries __unused,u32 flags)368 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah __unused, void *ds,
369 void *lastds,
370 u32 durUpdateEn, u32 rtsctsRate,
371 u32 rtsctsDuration __unused,
372 struct ath9k_11n_rate_series series[],
373 u32 nseries __unused, u32 flags)
374 {
375 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
376 struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
377 uint32_t ctl11;
378
379 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
380 ctl11 = ads->ctl11;
381
382 if (flags & ATH9K_TXDESC_RTSENA) {
383 ctl11 &= ~AR_CTSEnable;
384 ctl11 |= AR_RTSEnable;
385 } else {
386 ctl11 &= ~AR_RTSEnable;
387 ctl11 |= AR_CTSEnable;
388 }
389
390 ads->ctl11 = ctl11;
391 } else {
392 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
393 }
394
395 ads->ctl13 = set11nTries(series, 0)
396 | set11nTries(series, 1)
397 | set11nTries(series, 2)
398 | set11nTries(series, 3)
399 | (durUpdateEn ? AR_DurUpdateEna : 0)
400 | SM(0, AR_BurstDur);
401
402 ads->ctl14 = set11nRate(series, 0)
403 | set11nRate(series, 1)
404 | set11nRate(series, 2)
405 | set11nRate(series, 3);
406
407 ads->ctl15 = set11nPktDurRTSCTS(series, 0)
408 | set11nPktDurRTSCTS(series, 1);
409
410 ads->ctl16 = set11nPktDurRTSCTS(series, 2)
411 | set11nPktDurRTSCTS(series, 3);
412
413 ads->ctl18 = set11nRateFlags(series, 0)
414 | set11nRateFlags(series, 1)
415 | set11nRateFlags(series, 2)
416 | set11nRateFlags(series, 3)
417 | SM(rtsctsRate, AR_RTSCTSRate);
418 ads->ctl19 = AR_Not_Sounding;
419
420 last_ads->ctl13 = ads->ctl13;
421 last_ads->ctl14 = ads->ctl14;
422 }
423
ar9003_hw_set11n_aggr_first(struct ath_hw * ah,void * ds,u32 aggrLen)424 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
425 u32 aggrLen)
426 {
427 #define FIRST_DESC_NDELIMS 60
428 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
429
430 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
431
432 if (ah->ent_mode & AR_ENT_OTP_MPSD) {
433 u32 ctl17, ndelim;
434 /*
435 * Add delimiter when using RTS/CTS with aggregation
436 * and non enterprise AR9003 card
437 */
438 ctl17 = ads->ctl17;
439 ndelim = MS(ctl17, AR_PadDelim);
440
441 if (ndelim < FIRST_DESC_NDELIMS) {
442 aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
443 ndelim = FIRST_DESC_NDELIMS;
444 }
445
446 ctl17 &= ~AR_AggrLen;
447 ctl17 |= SM(aggrLen, AR_AggrLen);
448
449 ctl17 &= ~AR_PadDelim;
450 ctl17 |= SM(ndelim, AR_PadDelim);
451
452 ads->ctl17 = ctl17;
453 } else {
454 ads->ctl17 &= ~AR_AggrLen;
455 ads->ctl17 |= SM(aggrLen, AR_AggrLen);
456 }
457 }
458
ar9003_hw_set11n_aggr_middle(struct ath_hw * ah __unused,void * ds,u32 numDelims)459 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah __unused, void *ds,
460 u32 numDelims)
461 {
462 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
463 unsigned int ctl17;
464
465 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
466
467 /*
468 * We use a stack variable to manipulate ctl6 to reduce uncached
469 * read modify, modfiy, write.
470 */
471 ctl17 = ads->ctl17;
472 ctl17 &= ~AR_PadDelim;
473 ctl17 |= SM(numDelims, AR_PadDelim);
474 ads->ctl17 = ctl17;
475 }
476
ar9003_hw_set11n_aggr_last(struct ath_hw * ah __unused,void * ds)477 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah __unused, void *ds)
478 {
479 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
480
481 ads->ctl12 |= AR_IsAggr;
482 ads->ctl12 &= ~AR_MoreAggr;
483 ads->ctl17 &= ~AR_PadDelim;
484 }
485
ar9003_hw_clr11n_aggr(struct ath_hw * ah __unused,void * ds)486 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah __unused, void *ds)
487 {
488 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
489
490 ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
491 }
492
ar9003_hw_set_paprd_txdesc(struct ath_hw * ah __unused,void * ds,u8 chains)493 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah __unused, void *ds, u8 chains)
494 {
495 struct ar9003_txc *ads = ds;
496
497 ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
498 }
499
ar9003_hw_attach_mac_ops(struct ath_hw * hw)500 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
501 {
502 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
503
504 ops->rx_enable = ar9003_hw_rx_enable;
505 ops->set_desc_link = ar9003_hw_set_desc_link;
506 ops->get_desc_link = ar9003_hw_get_desc_link;
507 ops->get_isr = ar9003_hw_get_isr;
508 ops->fill_txdesc = ar9003_hw_fill_txdesc;
509 ops->proc_txdesc = ar9003_hw_proc_txdesc;
510 ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
511 ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
512 ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
513 ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
514 ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
515 ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
516 ops->set_clrdmask = ar9003_hw_set_clrdmask;
517 }
518
ath9k_hw_set_rx_bufsize(struct ath_hw * ah,u16 buf_size)519 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
520 {
521 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
522 }
523
ath9k_hw_addrxbuf_edma(struct ath_hw * ah,u32 rxdp,enum ath9k_rx_qtype qtype)524 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
525 enum ath9k_rx_qtype qtype)
526 {
527 if (qtype == ATH9K_RX_QUEUE_HP)
528 REG_WRITE(ah, AR_HP_RXDP, rxdp);
529 else
530 REG_WRITE(ah, AR_LP_RXDP, rxdp);
531 }
532
ath9k_hw_process_rxdesc_edma(struct ath_hw * ah __unused,struct ath_rx_status * rxs,void * buf_addr)533 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah __unused, struct ath_rx_status *rxs,
534 void *buf_addr)
535 {
536 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
537 unsigned int phyerr;
538
539 /* TODO: byte swap on big endian for ar9300_10 */
540
541 if ((rxsp->status11 & AR_RxDone) == 0)
542 return -EINPROGRESS;
543
544 if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
545 return -EINVAL;
546
547 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
548 return -EINPROGRESS;
549
550 if (!rxs)
551 return 0;
552
553 rxs->rs_status = 0;
554 rxs->rs_flags = 0;
555
556 rxs->rs_datalen = rxsp->status2 & AR_DataLen;
557 rxs->rs_tstamp = rxsp->status3;
558
559 /* XXX: Keycache */
560 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
561 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
562 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
563 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
564 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
565 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
566 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
567
568 if (rxsp->status11 & AR_RxKeyIdxValid)
569 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
570 else
571 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
572
573 rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
574 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
575
576 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
577 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
578 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
579 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
580 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
581
582 rxs->evm0 = rxsp->status6;
583 rxs->evm1 = rxsp->status7;
584 rxs->evm2 = rxsp->status8;
585 rxs->evm3 = rxsp->status9;
586 rxs->evm4 = (rxsp->status10 & 0xffff);
587
588 if (rxsp->status11 & AR_PreDelimCRCErr)
589 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
590
591 if (rxsp->status11 & AR_PostDelimCRCErr)
592 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
593
594 if (rxsp->status11 & AR_DecryptBusyErr)
595 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
596
597 if ((rxsp->status11 & AR_RxFrameOK) == 0) {
598 /*
599 * AR_CRCErr will bet set to true if we're on the last
600 * subframe and the AR_PostDelimCRCErr is caught.
601 * In a way this also gives us a guarantee that when
602 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
603 * possibly be reviewing the last subframe. AR_CRCErr
604 * is the CRC of the actual data.
605 */
606 if (rxsp->status11 & AR_CRCErr)
607 rxs->rs_status |= ATH9K_RXERR_CRC;
608 else if (rxsp->status11 & AR_PHYErr) {
609 phyerr = MS(rxsp->status11, AR_PHYErrCode);
610 /*
611 * If we reach a point here where AR_PostDelimCRCErr is
612 * true it implies we're *not* on the last subframe. In
613 * in that case that we know already that the CRC of
614 * the frame was OK, and MAC would send an ACK for that
615 * subframe, even if we did get a phy error of type
616 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
617 * to frame that are prior to the last subframe.
618 * The AR_PostDelimCRCErr is the CRC for the MPDU
619 * delimiter, which contains the 4 reserved bits,
620 * the MPDU length (12 bits), and follows the MPDU
621 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
622 */
623 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
624 (rxsp->status11 & AR_PostDelimCRCErr)) {
625 rxs->rs_phyerr = 0;
626 } else {
627 rxs->rs_status |= ATH9K_RXERR_PHY;
628 rxs->rs_phyerr = phyerr;
629 }
630
631 } else if (rxsp->status11 & AR_DecryptCRCErr)
632 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
633 else if (rxsp->status11 & AR_MichaelErr)
634 rxs->rs_status |= ATH9K_RXERR_MIC;
635 else if (rxsp->status11 & AR_KeyMiss)
636 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
637 }
638
639 return 0;
640 }
641
ath9k_hw_reset_txstatus_ring(struct ath_hw * ah)642 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
643 {
644 ah->ts_tail = 0;
645
646 memset((void *) ah->ts_ring, 0,
647 ah->ts_size * sizeof(struct ar9003_txs));
648
649 DBG2("ath9k: "
650 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
651 ah->ts_paddr_start, ah->ts_paddr_end,
652 ah->ts_ring, ah->ts_size);
653
654 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
655 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
656 }
657
ath9k_hw_setup_statusring(struct ath_hw * ah,void * ts_start,u32 ts_paddr_start,u8 size)658 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
659 u32 ts_paddr_start,
660 u8 size)
661 {
662
663 ah->ts_paddr_start = ts_paddr_start;
664 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
665 ah->ts_size = size;
666 ah->ts_ring = (struct ar9003_txs *) ts_start;
667
668 ath9k_hw_reset_txstatus_ring(ah);
669 }
670