1`timescale 1ns / 1ps 2/* 3 * This software is Copyright (c) 2016 Denis Burykin 4 * [denis_burykin yahoo com], [denis-burykin2014 yandex ru] 5 * and it is hereby released to the general public under the following terms: 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted. 8 * 9 */ 10 11// 12// 13module extra_reg_afull #( 14 parameter WIDTH = -1 15 )( 16 input CLK, 17 input [WIDTH-1:0] din, 18 input wr_en, 19 (* SHREG_EXTRACT="false" *) output reg full = 1, 20 21 (* SHREG_EXTRACT="false" *) output reg [WIDTH-1:0] dout, 22 input afull, 23 input rd_en, 24 (* SHREG_EXTRACT="false" *) output reg empty = 1 25 ); 26 27 always @(posedge CLK) begin 28 full <= afull; 29 30 if (wr_en) begin 31 empty <= 0; 32 dout <= din; 33 end 34 else if (rd_en) 35 empty <= 1; 36 end 37 38endmodule 39 40