1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_pcd.h 4 * @author MCD Application Team 5 * @version V1.2.0 6 * @date 01-July-2016 7 * @brief Header file of PCD HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32L1xx_HAL_PCD_H 40 #define __STM32L1xx_HAL_PCD_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l1xx_hal_def.h" 48 49 /** @addtogroup STM32L1xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup PCD 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup PCD_Exported_Types PCD Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief PCD State structure definition 64 */ 65 typedef enum 66 { 67 HAL_PCD_STATE_RESET = 0x00, 68 HAL_PCD_STATE_READY = 0x01, 69 HAL_PCD_STATE_ERROR = 0x02, 70 HAL_PCD_STATE_BUSY = 0x03, 71 HAL_PCD_STATE_TIMEOUT = 0x04 72 } PCD_StateTypeDef; 73 74 /** 75 * @brief PCD double buffered endpoint direction 76 */ 77 typedef enum 78 { 79 PCD_EP_DBUF_OUT, 80 PCD_EP_DBUF_IN, 81 PCD_EP_DBUF_ERR, 82 }PCD_EP_DBUF_DIR; 83 84 /** 85 * @brief PCD endpoint buffer number 86 */ 87 typedef enum 88 { 89 PCD_EP_NOBUF, 90 PCD_EP_BUF0, 91 PCD_EP_BUF1 92 }PCD_EP_BUF_NUM; 93 94 /** 95 * @brief PCD Initialization Structure definition 96 */ 97 typedef struct 98 { 99 uint32_t dev_endpoints; /*!< Device Endpoints number. 100 This parameter depends on the used USB core. 101 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 102 103 uint32_t speed; /*!< USB Core speed. 104 This parameter can be any value of @ref PCD_Core_Speed */ 105 106 uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. 107 This parameter can be any value of @ref PCD_EP0_MPS */ 108 109 uint32_t phy_itface; /*!< Select the used PHY interface. 110 This parameter can be any value of @ref PCD_Core_PHY */ 111 112 uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. 113 This parameter can be set to ENABLE or DISABLE */ 114 115 uint32_t low_power_enable; /*!< Enable or disable Low Power mode 116 This parameter can be set to ENABLE or DISABLE */ 117 118 uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . 119 This parameter can be set to ENABLE or DISABLE */ 120 121 uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. 122 This parameter can be set to ENABLE or DISABLE */ 123 124 }PCD_InitTypeDef; 125 126 typedef struct 127 { 128 uint8_t num; /*!< Endpoint number 129 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 130 131 uint8_t is_in; /*!< Endpoint direction 132 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 133 134 uint8_t is_stall; /*!< Endpoint stall condition 135 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 136 137 uint8_t type; /*!< Endpoint type 138 This parameter can be any value of @ref PCD_EP_Type */ 139 140 uint16_t pmaadress; /*!< PMA Address 141 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 142 143 144 uint16_t pmaaddr0; /*!< PMA Address0 145 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 146 147 148 uint16_t pmaaddr1; /*!< PMA Address1 149 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 150 151 152 uint8_t doublebuffer; /*!< Double buffer enable 153 This parameter can be 0 or 1 */ 154 155 uint32_t maxpacket; /*!< Endpoint Max packet size 156 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 157 158 uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ 159 160 161 uint32_t xfer_len; /*!< Current transfer length */ 162 163 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ 164 165 }PCD_EPTypeDef; 166 167 typedef USB_TypeDef PCD_TypeDef; 168 169 /** 170 * @brief PCD Handle Structure definition 171 */ 172 typedef struct 173 { 174 PCD_TypeDef *Instance; /*!< Register base address */ 175 PCD_InitTypeDef Init; /*!< PCD required parameters */ 176 __IO uint8_t USB_Address; /*!< USB Address */ 177 PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ 178 PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ 179 HAL_LockTypeDef Lock; /*!< PCD peripheral status */ 180 __IO PCD_StateTypeDef State; /*!< PCD communication state */ 181 uint32_t Setup[12]; /*!< Setup packet buffer */ 182 void *pData; /*!< Pointer to upper stack Handler */ 183 184 } PCD_HandleTypeDef; 185 186 /** 187 * @} 188 */ 189 190 /* Include PCD HAL Extension module */ 191 #include "stm32l1xx_hal_pcd_ex.h" 192 /* Exported constants --------------------------------------------------------*/ 193 /** @defgroup PCD_Exported_Constants PCD Exported Constants 194 * @{ 195 */ 196 197 /** @defgroup PCD_Exti_Line_Wakeup PCD_Exti_Line_Wakeup 198 * @{ 199 */ 200 201 #define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ 202 /** 203 * @} 204 */ 205 206 207 /** @defgroup PCD_Core_Speed PCD Core Speed 208 * @{ 209 */ 210 #define PCD_SPEED_HIGH 0 /* Not Supported */ 211 #define PCD_SPEED_FULL 2 212 /** 213 * @} 214 */ 215 216 /** @defgroup PCD_Core_PHY PCD Core PHY 217 * @{ 218 */ 219 #define PCD_PHY_EMBEDDED 2 220 /** 221 * @} 222 */ 223 224 /** @defgroup PCD_EP0_MPS PCD EP0 MPS 225 * @{ 226 */ 227 #define DEP0CTL_MPS_64 0 228 #define DEP0CTL_MPS_32 1 229 #define DEP0CTL_MPS_16 2 230 #define DEP0CTL_MPS_8 3 231 232 #define PCD_EP0MPS_64 DEP0CTL_MPS_64 233 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 234 #define PCD_EP0MPS_16 DEP0CTL_MPS_16 235 #define PCD_EP0MPS_08 DEP0CTL_MPS_8 236 /** 237 * @} 238 */ 239 240 /** @defgroup PCD_EP_Type PCD EP Type 241 * @{ 242 */ 243 #define PCD_EP_TYPE_CTRL 0 244 #define PCD_EP_TYPE_ISOC 1 245 #define PCD_EP_TYPE_BULK 2 246 #define PCD_EP_TYPE_INTR 3 247 /** 248 * @} 249 */ 250 251 /** @defgroup PCD_ENDP PCD ENDP 252 * @{ 253 */ 254 255 #define PCD_ENDP0 ((uint8_t)0) 256 #define PCD_ENDP1 ((uint8_t)1) 257 #define PCD_ENDP2 ((uint8_t)2) 258 #define PCD_ENDP3 ((uint8_t)3) 259 #define PCD_ENDP4 ((uint8_t)4) 260 #define PCD_ENDP5 ((uint8_t)5) 261 #define PCD_ENDP6 ((uint8_t)6) 262 #define PCD_ENDP7 ((uint8_t)7) 263 264 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE 265 266 /** 267 * @} 268 */ 269 270 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind 271 * @{ 272 */ 273 #define PCD_SNG_BUF 0 274 #define PCD_DBL_BUF 1 275 /** 276 * @} 277 */ 278 279 /** 280 * @} 281 */ 282 283 /* Exported macros -----------------------------------------------------------*/ 284 285 /** @defgroup PCD_Exported_Macros PCD Exported Macros 286 * @brief macros to handle interrupts and specific clock configurations 287 * @{ 288 */ 289 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) 290 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) 291 292 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE 293 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) 294 #define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE) 295 #define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE 296 297 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ 298 do{ \ 299 EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ 300 EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ 301 } while(0) 302 303 304 #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \ 305 do{ \ 306 EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \ 307 EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \ 308 } while(0) 309 310 311 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \ 312 do{ \ 313 EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \ 314 EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ 315 EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ 316 EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \ 317 } while(0) 318 319 /** 320 * @} 321 */ 322 323 /* Internal macros -----------------------------------------------------------*/ 324 325 /** @defgroup PCD_Private_Macros PCD Private Macros 326 * @brief macros to handle interrupts and specific clock configurations 327 * @{ 328 */ 329 330 /* SetENDPOINT */ 331 #define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) 332 333 /* GetENDPOINT */ 334 #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) 335 336 337 338 /** 339 * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) 340 * @param USBx: USB peripheral instance register address. 341 * @param bEpNum: Endpoint Number. 342 * @param wType: Endpoint Type. 343 * @retval None 344 */ 345 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ 346 ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) 347 348 /** 349 * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) 350 * @param USBx: USB peripheral instance register address. 351 * @param bEpNum: Endpoint Number. 352 * @retval Endpoint Type 353 */ 354 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) 355 356 357 /** 358 * @brief free buffer used from the application realizing it to the line 359 toggles bit SW_BUF in the double buffered endpoint register 360 * @param USBx: USB peripheral instance register address. 361 * @param bEpNum: Endpoint Number. 362 * @param bDir: Direction 363 * @retval None 364 */ 365 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ 366 {\ 367 if ((bDir) == PCD_EP_DBUF_OUT)\ 368 { /* OUT double buffered endpoint */\ 369 PCD_TX_DTOG((USBx), (bEpNum));\ 370 }\ 371 else if ((bDir) == PCD_EP_DBUF_IN)\ 372 { /* IN double buffered endpoint */\ 373 PCD_RX_DTOG((USBx), (bEpNum));\ 374 }\ 375 } 376 377 /** 378 * @brief gets direction of the double buffered endpoint 379 * @param USBx: USB peripheral instance register address. 380 * @param bEpNum: Endpoint Number. 381 * @retval EP_DBUF_OUT, EP_DBUF_IN, 382 * EP_DBUF_ERR if the endpoint counter not yet programmed. 383 */ 384 #define PCD_GET_DB_DIR(USBx, bEpNum)\ 385 {\ 386 if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ 387 return(PCD_EP_DBUF_OUT);\ 388 else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ 389 return(PCD_EP_DBUF_IN);\ 390 else\ 391 return(PCD_EP_DBUF_ERR);\ 392 } 393 394 /** 395 * @brief sets the status for tx transfer (bits STAT_TX[1:0]). 396 * @param USBx: USB peripheral instance register address. 397 * @param bEpNum: Endpoint Number. 398 * @param wState: new state 399 * @retval None 400 */ 401 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ 402 \ 403 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ 404 /* toggle first bit ? */ \ 405 if((USB_EPTX_DTOG1 & (wState))!= 0) \ 406 { \ 407 _wRegVal ^= USB_EPTX_DTOG1; \ 408 } \ 409 /* toggle second bit ? */ \ 410 if((USB_EPTX_DTOG2 & (wState))!= 0) \ 411 { \ 412 _wRegVal ^= USB_EPTX_DTOG2; \ 413 } \ 414 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ 415 } /* PCD_SET_EP_TX_STATUS */ 416 417 /** 418 * @brief sets the status for rx transfer (bits STAT_TX[1:0]) 419 * @param USBx: USB peripheral instance register address. 420 * @param bEpNum: Endpoint Number. 421 * @param wState: new state 422 * @retval None 423 */ 424 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ 425 register uint16_t _wRegVal; \ 426 \ 427 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ 428 /* toggle first bit ? */ \ 429 if((USB_EPRX_DTOG1 & (wState))!= 0) \ 430 { \ 431 _wRegVal ^= USB_EPRX_DTOG1; \ 432 } \ 433 /* toggle second bit ? */ \ 434 if((USB_EPRX_DTOG2 & (wState))!= 0) \ 435 { \ 436 _wRegVal ^= USB_EPRX_DTOG2; \ 437 } \ 438 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ 439 } /* PCD_SET_EP_RX_STATUS */ 440 441 /** 442 * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) 443 * @param USBx: USB peripheral instance register address. 444 * @param bEpNum: Endpoint Number. 445 * @param wStaterx: new state. 446 * @param wStatetx: new state. 447 * @retval None 448 */ 449 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ 450 register uint32_t _wRegVal; \ 451 \ 452 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ 453 /* toggle first bit ? */ \ 454 if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ 455 { \ 456 _wRegVal ^= USB_EPRX_DTOG1; \ 457 } \ 458 /* toggle second bit ? */ \ 459 if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ 460 { \ 461 _wRegVal ^= USB_EPRX_DTOG2; \ 462 } \ 463 /* toggle first bit ? */ \ 464 if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ 465 { \ 466 _wRegVal ^= USB_EPTX_DTOG1; \ 467 } \ 468 /* toggle second bit ? */ \ 469 if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ 470 { \ 471 _wRegVal ^= USB_EPTX_DTOG2; \ 472 } \ 473 PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ 474 } /* PCD_SET_EP_TXRX_STATUS */ 475 476 /** 477 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] 478 * /STAT_RX[1:0]) 479 * @param USBx: USB peripheral instance register address. 480 * @param bEpNum: Endpoint Number. 481 * @retval status 482 */ 483 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) 484 485 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) 486 487 /** 488 * @brief sets directly the VALID tx/rx-status into the endpoint register 489 * @param USBx: USB peripheral instance register address. 490 * @param bEpNum: Endpoint Number. 491 * @retval None 492 */ 493 #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) 494 495 #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) 496 497 /** 498 * @brief checks stall condition in an endpoint. 499 * @param USBx: USB peripheral instance register address. 500 * @param bEpNum: Endpoint Number. 501 * @retval TRUE = endpoint in stall condition. 502 */ 503 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ 504 == USB_EP_TX_STALL) 505 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ 506 == USB_EP_RX_STALL) 507 508 /** 509 * @brief set & clear EP_KIND bit. 510 * @param USBx: USB peripheral instance register address. 511 * @param bEpNum: Endpoint Number. 512 * @retval None 513 */ 514 #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ 515 (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) 516 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ 517 (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) 518 519 /** 520 * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. 521 * @param USBx: USB peripheral instance register address. 522 * @param bEpNum: Endpoint Number. 523 * @retval None 524 */ 525 #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) 526 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) 527 528 /** 529 * @brief Sets/clears directly EP_KIND bit in the endpoint register. 530 * @param USBx: USB peripheral instance register address. 531 * @param bEpNum: Endpoint Number. 532 * @retval None 533 */ 534 #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) 535 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) 536 537 /** 538 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. 539 * @param USBx: USB peripheral instance register address. 540 * @param bEpNum: Endpoint Number. 541 * @retval None 542 */ 543 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ 544 PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) 545 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ 546 PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) 547 548 /** 549 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 550 * @param USBx: USB peripheral instance register address. 551 * @param bEpNum: Endpoint Number. 552 * @retval None 553 */ 554 #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ 555 USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) 556 #define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ 557 USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) 558 559 /** 560 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. 561 * @param USBx: USB peripheral instance register address. 562 * @param bEpNum: Endpoint Number. 563 * @retval None 564 */ 565 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ 566 { \ 567 PCD_RX_DTOG((USBx), (bEpNum)); \ 568 } 569 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ 570 { \ 571 PCD_TX_DTOG((USBx), (bEpNum)); \ 572 } 573 574 /** 575 * @brief Sets address in an endpoint register. 576 * @param USBx: USB peripheral instance register address. 577 * @param bEpNum: Endpoint Number. 578 * @param bAddr: Address. 579 * @retval None 580 */ 581 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ 582 USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) 583 584 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) 585 586 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400))) 587 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400))) 588 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400))) 589 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400))) 590 591 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ 592 uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ 593 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ 594 } 595 596 /** 597 * @brief sets address of the tx/rx buffer. 598 * @param USBx: USB peripheral instance register address. 599 * @param bEpNum: Endpoint Number. 600 * @param wAddr: address to be set (must be word aligned). 601 * @retval None 602 */ 603 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) 604 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) 605 606 /** 607 * @brief Gets address of the tx/rx buffer. 608 * @param USBx: USB peripheral instance register address. 609 * @param bEpNum: Endpoint Number. 610 * @retval address of the buffer. 611 */ 612 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) 613 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) 614 615 /** 616 * @brief Sets counter of rx buffer with no. of blocks. 617 * @param dwReg: Register 618 * @param wCount: Counter. 619 * @param wNBlocks: no. of Blocks. 620 * @retval None 621 */ 622 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ 623 (wNBlocks) = (wCount) >> 5;\ 624 if(((wCount) & 0x1f) == 0)\ 625 { \ 626 (wNBlocks)--;\ 627 } \ 628 *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ 629 }/* PCD_CALC_BLK32 */ 630 631 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ 632 (wNBlocks) = (wCount) >> 1;\ 633 if(((wCount) & 0x1) != 0)\ 634 { \ 635 (wNBlocks)++;\ 636 } \ 637 *pdwReg = (uint16_t)((wNBlocks) << 10);\ 638 }/* PCD_CALC_BLK2 */ 639 640 #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ 641 uint16_t wNBlocks;\ 642 if((wCount) > 62) \ 643 { \ 644 PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ 645 } \ 646 else \ 647 { \ 648 PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ 649 } \ 650 }/* PCD_SET_EP_CNT_RX_REG */ 651 652 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ 653 uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ 654 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ 655 } 656 /** 657 * @brief sets counter for the tx/rx buffer. 658 * @param USBx: USB peripheral instance register address. 659 * @param bEpNum: Endpoint Number. 660 * @param wCount: Counter value. 661 * @retval None 662 */ 663 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) 664 665 666 /** 667 * @brief gets counter of the tx buffer. 668 * @param USBx: USB peripheral instance register address. 669 * @param bEpNum: Endpoint Number. 670 * @retval Counter value 671 */ 672 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) 673 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) 674 675 /** 676 * @brief Sets buffer 0/1 address in a double buffer endpoint. 677 * @param USBx: USB peripheral instance register address. 678 * @param bEpNum: Endpoint Number. 679 * @param wBuf0Addr: buffer 0 address. 680 * @retval Counter value 681 */ 682 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} 683 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} 684 685 /** 686 * @brief Sets addresses in a double buffer endpoint. 687 * @param USBx: USB peripheral instance register address. 688 * @param bEpNum: Endpoint Number. 689 * @param wBuf0Addr: buffer 0 address. 690 * @param wBuf1Addr = buffer 1 address. 691 * @retval None 692 */ 693 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ 694 PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ 695 PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ 696 } /* PCD_SET_EP_DBUF_ADDR */ 697 698 /** 699 * @brief Gets buffer 0/1 address of a double buffer endpoint. 700 * @param USBx: USB peripheral instance register address. 701 * @param bEpNum: Endpoint Number. 702 * @retval None 703 */ 704 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) 705 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) 706 707 /** 708 * @brief Gets buffer 0/1 address of a double buffer endpoint. 709 * @param USBx: USB peripheral instance register address. 710 * @param bEpNum: Endpoint Number. 711 * @param bDir: endpoint dir EP_DBUF_OUT = OUT 712 * EP_DBUF_IN = IN 713 * @param wCount: Counter value 714 * @retval None 715 */ 716 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ 717 if((bDir) == PCD_EP_DBUF_OUT)\ 718 /* OUT endpoint */ \ 719 {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ 720 else if((bDir) == PCD_EP_DBUF_IN)\ 721 /* IN endpoint */ \ 722 *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ 723 } /* SetEPDblBuf0Count*/ 724 725 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ 726 if((bDir) == PCD_EP_DBUF_OUT)\ 727 {/* OUT endpoint */ \ 728 PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ 729 } \ 730 else if((bDir) == PCD_EP_DBUF_IN)\ 731 {/* IN endpoint */ \ 732 *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ 733 } \ 734 } /* SetEPDblBuf1Count */ 735 736 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ 737 PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ 738 PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ 739 } /* PCD_SET_EP_DBUF_CNT */ 740 741 /** 742 * @brief Gets buffer 0/1 rx/tx counter for double buffering. 743 * @param USBx: USB peripheral instance register address. 744 * @param bEpNum: Endpoint Number. 745 * @retval None 746 */ 747 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) 748 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) 749 750 751 /** 752 * @} 753 */ 754 755 /* Exported functions --------------------------------------------------------*/ 756 757 /** @addtogroup PCD_Exported_Functions 758 * @{ 759 */ 760 761 /* Initialization/de-initialization functions **********************************/ 762 763 764 /** @addtogroup PCD_Exported_Functions_Group1 765 * @{ 766 */ 767 768 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); 769 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); 770 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); 771 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); 772 773 /** 774 * @} 775 */ 776 777 /* I/O operation functions *****************************************************/ 778 /* Non-Blocking mode: Interrupt */ 779 /** @addtogroup PCD_Exported_Functions_Group2 780 * @{ 781 */ 782 783 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); 784 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); 785 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); 786 787 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 788 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 789 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); 790 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); 791 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); 792 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); 793 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); 794 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 795 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 796 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); 797 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); 798 799 /** 800 * @} 801 */ 802 803 /* Peripheral Control functions ************************************************/ 804 /** @addtogroup PCD_Exported_Functions_Group3 805 * @{ 806 */ 807 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); 808 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); 809 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); 810 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); 811 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 812 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); 813 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); 814 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 815 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 816 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 817 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 818 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); 819 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); 820 /** 821 * @} 822 */ 823 824 825 /* Peripheral State functions **************************************************/ 826 /** @addtogroup PCD_Exported_Functions_Group4 827 * @{ 828 */ 829 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); 830 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); 831 /** 832 * @} 833 */ 834 835 836 /** 837 * @} 838 */ 839 840 841 /** 842 * @} 843 */ 844 845 /** 846 * @} 847 */ 848 849 #ifdef __cplusplus 850 } 851 #endif 852 853 854 #endif /* __STM32L1xx_HAL_PCD_H */ 855 856 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 857