1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_rcc.h 4 * @author MCD Application Team 5 * @version V1.2.0 6 * @date 01-July-2016 7 * @brief Header file of RCC HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32L1xx_HAL_RCC_H 40 #define __STM32L1xx_HAL_RCC_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l1xx_hal_def.h" 48 49 /** @addtogroup STM32L1xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup RCC 54 * @{ 55 */ 56 57 /** @addtogroup RCC_Private_Constants 58 * @{ 59 */ 60 61 /** @defgroup RCC_Timeout RCC Timeout 62 * @{ 63 */ 64 65 /* Disable Backup domain write protection state change timeout */ 66 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ 67 /* LSE state change timeout */ 68 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 69 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 70 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 71 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 72 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 73 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 74 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 75 /** 76 * @} 77 */ 78 79 /** @defgroup RCC_Register_Offset Register offsets 80 * @{ 81 */ 82 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 83 #define RCC_CR_OFFSET 0x00 84 #define RCC_CFGR_OFFSET 0x08 85 #define RCC_CIR_OFFSET 0x0C 86 #define RCC_CSR_OFFSET 0x34 87 /** 88 * @} 89 */ 90 91 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 92 * @brief RCC registers bit address in the alias region 93 * @{ 94 */ 95 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) 96 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) 97 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) 98 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) 99 100 /* --- CR Register ---*/ 101 /* Alias word address of HSION bit */ 102 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) 103 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4))) 104 /* Alias word address of MSION bit */ 105 #define RCC_MSION_BIT_NUMBER POSITION_VAL(RCC_CR_MSION) 106 #define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_MSION_BIT_NUMBER * 4))) 107 /* Alias word address of HSEON bit */ 108 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) 109 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4))) 110 /* Alias word address of CSSON bit */ 111 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) 112 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4))) 113 /* Alias word address of PLLON bit */ 114 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) 115 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4))) 116 117 /* --- CSR Register ---*/ 118 /* Alias word address of LSION bit */ 119 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) 120 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4))) 121 122 /* Alias word address of RMVF bit */ 123 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) 124 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4))) 125 126 /* Alias word address of LSEON bit */ 127 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEON) 128 #define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4))) 129 130 /* Alias word address of LSEON bit */ 131 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEBYP) 132 #define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4))) 133 134 /* Alias word address of RTCEN bit */ 135 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCEN) 136 #define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4))) 137 138 /* Alias word address of RTCRST bit */ 139 #define RCC_RTCRST_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCRST) 140 #define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCRST_BIT_NUMBER * 4))) 141 142 /** 143 * @} 144 */ 145 146 /* CR register byte 2 (Bits[23:16]) base address */ 147 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) 148 149 /* CIR register byte 1 (Bits[15:8]) base address */ 150 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) 151 152 /* CIR register byte 2 (Bits[23:16]) base address */ 153 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) 154 155 /* Defines used for Flags */ 156 #define CR_REG_INDEX ((uint8_t)1) 157 #define CSR_REG_INDEX ((uint8_t)2) 158 159 #define RCC_FLAG_MASK ((uint8_t)0x1F) 160 161 /** 162 * @} 163 */ 164 165 /** @addtogroup RCC_Private_Macros 166 * @{ 167 */ 168 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 169 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 170 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 171 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 172 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 173 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 174 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 175 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) 176 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 177 ((__HSE__) == RCC_HSE_BYPASS)) 178 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 179 ((__LSE__) == RCC_LSE_BYPASS)) 180 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 181 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) 182 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF) 183 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 184 ((__RANGE__) == RCC_MSIRANGE_1) || \ 185 ((__RANGE__) == RCC_MSIRANGE_2) || \ 186 ((__RANGE__) == RCC_MSIRANGE_3) || \ 187 ((__RANGE__) == RCC_MSIRANGE_4) || \ 188 ((__RANGE__) == RCC_MSIRANGE_5) || \ 189 ((__RANGE__) == RCC_MSIRANGE_6)) 190 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 191 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 192 193 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 194 ((__PLL__) == RCC_PLL_ON)) 195 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ 196 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) 197 198 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ 199 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ 200 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ 201 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ 202 ((__MUL__) == RCC_PLL_MUL48)) 203 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 204 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 205 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 206 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 207 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 208 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 209 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 210 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 211 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \ 212 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 213 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 214 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 215 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 216 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 217 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 218 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 219 ((__HCLK__) == RCC_SYSCLK_DIV512)) 220 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 221 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 222 ((__PCLK__) == RCC_HCLK_DIV16)) 223 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 224 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 225 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 226 ((__DIV__) == RCC_MCODIV_16)) 227 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ 228 || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ 229 || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ 230 || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 231 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 232 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 233 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 234 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 235 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 236 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 237 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) 238 239 /** 240 * @} 241 */ 242 243 /* Exported types ------------------------------------------------------------*/ 244 245 /** @defgroup RCC_Exported_Types RCC Exported Types 246 * @{ 247 */ 248 249 /** 250 * @brief RCC PLL configuration structure definition 251 */ 252 typedef struct 253 { 254 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 255 This parameter can be a value of @ref RCC_PLL_Config */ 256 257 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 258 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 259 260 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 261 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ 262 263 uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock 264 This parameter must be a value of @ref RCC_PLL_Division_Factor*/ 265 } RCC_PLLInitTypeDef; 266 267 /** 268 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 269 */ 270 typedef struct 271 { 272 uint32_t OscillatorType; /*!< The oscillators to be configured. 273 This parameter can be a value of @ref RCC_Oscillator_Type */ 274 275 uint32_t HSEState; /*!< The new state of the HSE. 276 This parameter can be a value of @ref RCC_HSE_Config */ 277 278 uint32_t LSEState; /*!< The new state of the LSE. 279 This parameter can be a value of @ref RCC_LSE_Config */ 280 281 uint32_t HSIState; /*!< The new state of the HSI. 282 This parameter can be a value of @ref RCC_HSI_Config */ 283 284 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 285 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 286 287 uint32_t LSIState; /*!< The new state of the LSI. 288 This parameter can be a value of @ref RCC_LSI_Config */ 289 290 uint32_t MSIState; /*!< The new state of the MSI. 291 This parameter can be a value of @ref RCC_MSI_Config */ 292 293 uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). 294 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 295 296 uint32_t MSIClockRange; /*!< The MSI frequency range. 297 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 298 299 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 300 301 } RCC_OscInitTypeDef; 302 303 /** 304 * @brief RCC System, AHB and APB busses clock configuration structure definition 305 */ 306 typedef struct 307 { 308 uint32_t ClockType; /*!< The clock to be configured. 309 This parameter can be a value of @ref RCC_System_Clock_Type */ 310 311 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 312 This parameter can be a value of @ref RCC_System_Clock_Source */ 313 314 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 315 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 316 317 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 318 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 319 320 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 321 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 322 } RCC_ClkInitTypeDef; 323 324 /** 325 * @} 326 */ 327 328 /* Exported constants --------------------------------------------------------*/ 329 /** @defgroup RCC_Exported_Constants RCC Exported Constants 330 * @{ 331 */ 332 333 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 334 * @{ 335 */ 336 337 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 338 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 339 340 /** 341 * @} 342 */ 343 344 /** @defgroup RCC_Oscillator_Type Oscillator Type 345 * @{ 346 */ 347 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) 348 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) 349 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) 350 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) 351 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) 352 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCC_HSE_Config HSE Config 358 * @{ 359 */ 360 #define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ 361 #define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */ 362 #define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup RCC_LSE_Config LSE Config 368 * @{ 369 */ 370 #define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ 371 #define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */ 372 #define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */ 373 374 /** 375 * @} 376 */ 377 378 /** @defgroup RCC_HSI_Config HSI Config 379 * @{ 380 */ 381 #define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ 382 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 383 384 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ 385 386 /** 387 * @} 388 */ 389 390 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 391 * @{ 392 */ 393 394 #define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ 395 #define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ 396 #define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ 397 #define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ 398 #define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ 399 #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ 400 #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ 401 402 /** 403 * @} 404 */ 405 406 /** @defgroup RCC_LSI_Config LSI Config 407 * @{ 408 */ 409 #define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ 410 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 411 412 /** 413 * @} 414 */ 415 416 /** @defgroup RCC_MSI_Config MSI Config 417 * @{ 418 */ 419 #define RCC_MSI_OFF ((uint32_t)0x00000000) 420 #define RCC_MSI_ON ((uint32_t)0x00000001) 421 422 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */ 423 424 /** 425 * @} 426 */ 427 428 /** @defgroup RCC_PLL_Config PLL Config 429 * @{ 430 */ 431 #define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ 432 #define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ 433 #define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ 434 435 /** 436 * @} 437 */ 438 439 /** @defgroup RCC_System_Clock_Type System Clock Type 440 * @{ 441 */ 442 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ 443 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ 444 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ 445 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ 446 447 /** 448 * @} 449 */ 450 451 /** @defgroup RCC_System_Clock_Source System Clock Source 452 * @{ 453 */ 454 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */ 455 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 456 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 457 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 458 459 /** 460 * @} 461 */ 462 463 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 464 * @{ 465 */ 466 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 467 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 468 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 469 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 470 471 /** 472 * @} 473 */ 474 475 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 476 * @{ 477 */ 478 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 479 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 480 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 481 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 482 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 483 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 484 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 485 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 486 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 487 488 /** 489 * @} 490 */ 491 492 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 493 * @{ 494 */ 495 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 496 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 497 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 498 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 499 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 500 501 /** 502 * @} 503 */ 504 505 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler 506 * @{ 507 */ 508 #define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */ 509 #define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ 510 #define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ 511 #define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ 512 /** 513 * @} 514 */ 515 516 /** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source 517 * @{ 518 */ 519 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ 520 #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 521 #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 522 #define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */ 523 #define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */ 524 #define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */ 525 #define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */ 526 #define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */ 527 /** 528 * @} 529 */ 530 531 /** @defgroup RCC_PLL_Division_Factor PLL Division Factor 532 * @{ 533 */ 534 535 #define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 536 #define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 537 #define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 538 539 /** 540 * @} 541 */ 542 543 /** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor 544 * @{ 545 */ 546 547 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 548 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 549 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 550 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 551 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 552 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 553 #define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 554 #define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 555 #define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 556 557 /** 558 * @} 559 */ 560 561 /** @defgroup RCC_MCO_Index MCO Index 562 * @{ 563 */ 564 #define RCC_MCO1 ((uint32_t)0x00000000) 565 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 566 567 /** 568 * @} 569 */ 570 571 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 572 * @{ 573 */ 574 #define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1) 575 #define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2) 576 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4) 577 #define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8) 578 #define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16) 579 580 /** 581 * @} 582 */ 583 584 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 585 * @{ 586 */ 587 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK 588 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK 589 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI 590 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI 591 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE 592 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI 593 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE 594 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL 595 596 /** 597 * @} 598 */ 599 /** @defgroup RCC_Interrupt Interrupts 600 * @{ 601 */ 602 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 603 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 604 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 605 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 606 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 607 #define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /*!< MSI Ready Interrupt flag */ 608 #define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /*!< LSE Clock Security System Interrupt flag */ 609 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 610 /** 611 * @} 612 */ 613 614 /** @defgroup RCC_Flag Flags 615 * Elements values convention: XXXYYYYYb 616 * - YYYYY : Flag position in the register 617 * - XXX : Register index 618 * - 001: CR register 619 * - 010: CSR register 620 * @{ 621 */ 622 /* Flags in the CR register */ 623 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ 624 #define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */ 625 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ 626 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ 627 628 /* Flags in the CSR register */ 629 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ 630 #define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */ 631 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ 632 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ 633 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ 634 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ 635 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ 636 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ 637 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ 638 #define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */ 639 640 /** 641 * @} 642 */ 643 644 /** 645 * @} 646 */ 647 648 /* Exported macro ------------------------------------------------------------*/ 649 650 /** @defgroup RCC_Exported_Macros RCC Exported Macros 651 * @{ 652 */ 653 654 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 655 * @brief Enable or disable the AHB1 peripheral clock. 656 * @note After reset, the peripheral clock (used for registers read/write access) 657 * is disabled and the application software has to enable this clock before 658 * using it. 659 * @{ 660 */ 661 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 662 __IO uint32_t tmpreg; \ 663 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 664 /* Delay after an RCC peripheral clock enabling */\ 665 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 666 UNUSED(tmpreg); \ 667 } while(0) 668 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 669 __IO uint32_t tmpreg; \ 670 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 671 /* Delay after an RCC peripheral clock enabling */\ 672 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 673 UNUSED(tmpreg); \ 674 } while(0) 675 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 676 __IO uint32_t tmpreg; \ 677 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 678 /* Delay after an RCC peripheral clock enabling */\ 679 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 680 UNUSED(tmpreg); \ 681 } while(0) 682 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 683 __IO uint32_t tmpreg; \ 684 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 685 /* Delay after an RCC peripheral clock enabling */\ 686 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 687 UNUSED(tmpreg); \ 688 } while(0) 689 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 690 __IO uint32_t tmpreg; \ 691 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ 692 /* Delay after an RCC peripheral clock enabling */\ 693 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ 694 UNUSED(tmpreg); \ 695 } while(0) 696 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 697 __IO uint32_t tmpreg; \ 698 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 699 /* Delay after an RCC peripheral clock enabling */\ 700 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 701 UNUSED(tmpreg); \ 702 } while(0) 703 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 704 __IO uint32_t tmpreg; \ 705 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 706 /* Delay after an RCC peripheral clock enabling */\ 707 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 708 UNUSED(tmpreg); \ 709 } while(0) 710 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 711 __IO uint32_t tmpreg; \ 712 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 713 /* Delay after an RCC peripheral clock enabling */\ 714 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 715 UNUSED(tmpreg); \ 716 } while(0) 717 718 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) 719 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) 720 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) 721 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) 722 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) 723 724 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 725 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 726 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 727 728 /** 729 * @} 730 */ 731 732 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 733 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 734 * @note After reset, the peripheral clock (used for registers read/write access) 735 * is disabled and the application software has to enable this clock before 736 * using it. 737 * @{ 738 */ 739 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 740 __IO uint32_t tmpreg; \ 741 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 742 /* Delay after an RCC peripheral clock enabling */\ 743 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 744 UNUSED(tmpreg); \ 745 } while(0) 746 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 747 __IO uint32_t tmpreg; \ 748 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 749 /* Delay after an RCC peripheral clock enabling */\ 750 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 751 UNUSED(tmpreg); \ 752 } while(0) 753 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 754 __IO uint32_t tmpreg; \ 755 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 756 /* Delay after an RCC peripheral clock enabling */\ 757 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 758 UNUSED(tmpreg); \ 759 } while(0) 760 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 761 __IO uint32_t tmpreg; \ 762 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 763 /* Delay after an RCC peripheral clock enabling */\ 764 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 765 UNUSED(tmpreg); \ 766 } while(0) 767 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 768 __IO uint32_t tmpreg; \ 769 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 770 /* Delay after an RCC peripheral clock enabling */\ 771 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 772 UNUSED(tmpreg); \ 773 } while(0) 774 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 775 __IO uint32_t tmpreg; \ 776 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 777 /* Delay after an RCC peripheral clock enabling */\ 778 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 779 UNUSED(tmpreg); \ 780 } while(0) 781 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 782 __IO uint32_t tmpreg; \ 783 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 784 /* Delay after an RCC peripheral clock enabling */\ 785 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 786 UNUSED(tmpreg); \ 787 } while(0) 788 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 789 __IO uint32_t tmpreg; \ 790 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 791 /* Delay after an RCC peripheral clock enabling */\ 792 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 793 UNUSED(tmpreg); \ 794 } while(0) 795 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 796 __IO uint32_t tmpreg; \ 797 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 798 /* Delay after an RCC peripheral clock enabling */\ 799 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 800 UNUSED(tmpreg); \ 801 } while(0) 802 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 803 __IO uint32_t tmpreg; \ 804 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 805 /* Delay after an RCC peripheral clock enabling */\ 806 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 807 UNUSED(tmpreg); \ 808 } while(0) 809 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 810 __IO uint32_t tmpreg; \ 811 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 812 /* Delay after an RCC peripheral clock enabling */\ 813 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 814 UNUSED(tmpreg); \ 815 } while(0) 816 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 817 __IO uint32_t tmpreg; \ 818 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 819 /* Delay after an RCC peripheral clock enabling */\ 820 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 821 UNUSED(tmpreg); \ 822 } while(0) 823 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 824 __IO uint32_t tmpreg; \ 825 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 826 /* Delay after an RCC peripheral clock enabling */\ 827 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 828 UNUSED(tmpreg); \ 829 } while(0) 830 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 831 __IO uint32_t tmpreg; \ 832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 833 /* Delay after an RCC peripheral clock enabling */\ 834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 835 UNUSED(tmpreg); \ 836 } while(0) 837 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 838 __IO uint32_t tmpreg; \ 839 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ 840 /* Delay after an RCC peripheral clock enabling */\ 841 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ 842 UNUSED(tmpreg); \ 843 } while(0) 844 845 846 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 847 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 848 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 849 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 850 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 851 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 852 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 853 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 854 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 855 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 856 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 857 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 858 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 859 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 860 #define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) 861 862 /** 863 * @} 864 */ 865 866 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 867 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 868 * @note After reset, the peripheral clock (used for registers read/write access) 869 * is disabled and the application software has to enable this clock before 870 * using it. 871 * @{ 872 */ 873 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 874 __IO uint32_t tmpreg; \ 875 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 876 /* Delay after an RCC peripheral clock enabling */\ 877 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 878 UNUSED(tmpreg); \ 879 } while(0) 880 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 881 __IO uint32_t tmpreg; \ 882 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 883 /* Delay after an RCC peripheral clock enabling */\ 884 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 885 UNUSED(tmpreg); \ 886 } while(0) 887 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 888 __IO uint32_t tmpreg; \ 889 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 890 /* Delay after an RCC peripheral clock enabling */\ 891 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 892 UNUSED(tmpreg); \ 893 } while(0) 894 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 895 __IO uint32_t tmpreg; \ 896 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 897 /* Delay after an RCC peripheral clock enabling */\ 898 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 899 UNUSED(tmpreg); \ 900 } while(0) 901 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 902 __IO uint32_t tmpreg; \ 903 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 904 /* Delay after an RCC peripheral clock enabling */\ 905 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 906 UNUSED(tmpreg); \ 907 } while(0) 908 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 909 __IO uint32_t tmpreg; \ 910 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 911 /* Delay after an RCC peripheral clock enabling */\ 912 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 913 UNUSED(tmpreg); \ 914 } while(0) 915 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 916 __IO uint32_t tmpreg; \ 917 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 918 /* Delay after an RCC peripheral clock enabling */\ 919 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 920 UNUSED(tmpreg); \ 921 } while(0) 922 923 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 924 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 925 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 926 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 927 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 928 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 929 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 930 931 /** 932 * @} 933 */ 934 935 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release 936 * @brief Force or release AHB peripheral reset. 937 * @{ 938 */ 939 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 940 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) 941 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) 942 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) 943 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) 944 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) 945 946 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) 947 #define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) 948 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) 949 950 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) 951 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) 952 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) 953 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) 954 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) 955 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) 956 957 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) 958 #define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) 959 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) 960 961 /** 962 * @} 963 */ 964 965 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 966 * @brief Force or release APB1 peripheral reset. 967 * @{ 968 */ 969 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 970 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 971 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 972 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 973 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 974 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 975 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 976 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 977 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 978 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 979 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 980 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 981 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 982 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 983 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 984 #define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) 985 986 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) 987 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 988 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 989 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 990 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 991 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 992 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 993 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 994 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 995 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 996 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 997 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 998 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 999 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 1000 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1001 #define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) 1002 1003 /** 1004 * @} 1005 */ 1006 1007 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 1008 * @brief Force or release APB1 peripheral reset. 1009 * @{ 1010 */ 1011 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 1012 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 1013 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 1014 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1015 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 1016 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 1017 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 1018 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 1019 1020 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) 1021 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 1022 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 1023 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1024 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 1025 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 1026 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 1027 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 1028 1029 /** 1030 * @} 1031 */ 1032 1033 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable 1034 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1035 * power consumption. 1036 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1037 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1038 * @{ 1039 */ 1040 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) 1041 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) 1042 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) 1043 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) 1044 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) 1045 1046 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) 1047 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) 1048 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) 1049 1050 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) 1051 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) 1052 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) 1053 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) 1054 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) 1055 1056 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) 1057 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) 1058 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) 1059 1060 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1061 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1062 * power consumption. 1063 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1064 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1065 */ 1066 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 1067 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 1068 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 1069 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 1070 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 1071 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) 1072 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) 1073 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) 1074 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 1075 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) 1076 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) 1077 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) 1078 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) 1079 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 1080 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) 1081 1082 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 1083 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 1084 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 1085 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 1086 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 1087 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) 1088 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) 1089 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) 1090 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 1091 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) 1092 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) 1093 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) 1094 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) 1095 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 1096 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) 1097 1098 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1099 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1100 * power consumption. 1101 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1102 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1103 */ 1104 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) 1105 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) 1106 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 1107 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) 1108 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) 1109 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) 1110 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) 1111 1112 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) 1113 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) 1114 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 1115 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) 1116 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) 1117 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) 1118 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) 1119 1120 /** 1121 * @} 1122 */ 1123 1124 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 1125 * @brief Get the enable or disable status of the AHB peripheral clock. 1126 * @note After reset, the peripheral clock (used for registers read/write access) 1127 * is disabled and the application software has to enable this clock before 1128 * using it. 1129 * @{ 1130 */ 1131 1132 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) 1133 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) 1134 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) 1135 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) 1136 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET) 1137 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 1138 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 1139 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 1140 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) 1141 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) 1142 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) 1143 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) 1144 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET) 1145 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 1146 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 1147 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 1148 1149 /** 1150 * @} 1151 */ 1152 1153 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 1154 * @brief Get the enable or disable status of the APB1 peripheral clock. 1155 * @note After reset, the peripheral clock (used for registers read/write access) 1156 * is disabled and the application software has to enable this clock before 1157 * using it. 1158 * @{ 1159 */ 1160 1161 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 1162 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 1163 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1164 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1165 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1166 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 1167 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 1168 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 1169 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1170 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 1171 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 1172 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 1173 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 1174 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1175 #define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != RESET) 1176 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 1177 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 1178 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1179 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1180 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1181 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 1182 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 1183 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 1184 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1185 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 1186 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 1187 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 1188 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 1189 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1190 #define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == RESET) 1191 1192 /** 1193 * @} 1194 */ 1195 1196 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1197 * @brief Get the enable or disable status of the APB2 peripheral clock. 1198 * @note After reset, the peripheral clock (used for registers read/write access) 1199 * is disabled and the application software has to enable this clock before 1200 * using it. 1201 * @{ 1202 */ 1203 1204 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 1205 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 1206 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 1207 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 1208 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 1209 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 1210 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 1211 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 1212 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 1213 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 1214 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 1215 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 1216 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 1217 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 1218 1219 /** 1220 * @} 1221 */ 1222 1223 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status 1224 * @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode. 1225 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1226 * power consumption. 1227 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1228 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1229 * @{ 1230 */ 1231 1232 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != RESET) 1233 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != RESET) 1234 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != RESET) 1235 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != RESET) 1236 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != RESET) 1237 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != RESET) 1238 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != RESET) 1239 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != RESET) 1240 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == RESET) 1241 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == RESET) 1242 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == RESET) 1243 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == RESET) 1244 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == RESET) 1245 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == RESET) 1246 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == RESET) 1247 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == RESET) 1248 1249 /** 1250 * @} 1251 */ 1252 1253 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status 1254 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. 1255 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1256 * power consumption. 1257 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1258 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1259 * @{ 1260 */ 1261 1262 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) 1263 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) 1264 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) 1265 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) 1266 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) 1267 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) 1268 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) 1269 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) 1270 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) 1271 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) 1272 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) 1273 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != RESET) 1274 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) 1275 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) 1276 #define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != RESET) 1277 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) 1278 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) 1279 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) 1280 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) 1281 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) 1282 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) 1283 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) 1284 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) 1285 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) 1286 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) 1287 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) 1288 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == RESET) 1289 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) 1290 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) 1291 #define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == RESET) 1292 1293 /** 1294 * @} 1295 */ 1296 1297 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status 1298 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. 1299 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1300 * power consumption. 1301 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1302 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1303 * @{ 1304 */ 1305 1306 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) 1307 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) 1308 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) 1309 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) 1310 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) 1311 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) 1312 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) 1313 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) 1314 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) 1315 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) 1316 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) 1317 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) 1318 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) 1319 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) 1320 1321 /** 1322 * @} 1323 */ 1324 1325 /** @defgroup RCC_HSI_Configuration HSI Configuration 1326 * @{ 1327 */ 1328 1329 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 1330 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1331 * @note HSI can not be stopped if it is used as system clock source. In this case, 1332 * you have to select another source of the system clock then stop the HSI. 1333 * @note After enabling the HSI, the application software should wait on HSIRDY 1334 * flag to be set indicating that HSI clock is stable and can be used as 1335 * system clock source. 1336 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1337 * clock cycles. 1338 */ 1339 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 1340 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 1341 1342 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1343 * @note The calibration is used to compensate for the variations in voltage 1344 * and temperature that influence the frequency of the internal HSI RC. 1345 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 1346 * (default is RCC_HSICALIBRATION_DEFAULT). 1347 * This parameter must be a number between 0 and 0x1F. 1348 */ 1349 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 1350 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM))) 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** @defgroup RCC_LSI_Configuration LSI Configuration 1357 * @{ 1358 */ 1359 1360 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 1361 * @note After enabling the LSI, the application software should wait on 1362 * LSIRDY flag to be set indicating that LSI clock is stable and can 1363 * be used to clock the IWDG and/or the RTC. 1364 */ 1365 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 1366 1367 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 1368 * @note LSI can not be disabled if the IWDG is running. 1369 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1370 * clock cycles. 1371 */ 1372 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 1373 1374 /** 1375 * @} 1376 */ 1377 1378 /** @defgroup RCC_HSE_Configuration HSE Configuration 1379 * @{ 1380 */ 1381 1382 /** 1383 * @brief Macro to configure the External High Speed oscillator (HSE). 1384 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1385 * supported by this macro. User should request a transition to HSE Off 1386 * first and then HSE On or HSE Bypass. 1387 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1388 * software should wait on HSERDY flag to be set indicating that HSE clock 1389 * is stable and can be used to clock the PLL and/or system clock. 1390 * @note HSE state can not be changed if it is used directly or through the 1391 * PLL as system clock. In this case, you have to select another source 1392 * of the system clock then change the HSE state (ex. disable it). 1393 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1394 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1395 * was previously enabled you have to enable it again after calling this 1396 * function. 1397 * @param __STATE__ specifies the new state of the HSE. 1398 * This parameter can be one of the following values: 1399 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 1400 * 6 HSE oscillator clock cycles. 1401 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 1402 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 1403 */ 1404 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1405 do{ \ 1406 if ((__STATE__) == RCC_HSE_ON) \ 1407 { \ 1408 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1409 } \ 1410 else if ((__STATE__) == RCC_HSE_OFF) \ 1411 { \ 1412 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1413 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1414 } \ 1415 else if ((__STATE__) == RCC_HSE_BYPASS) \ 1416 { \ 1417 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1418 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1419 } \ 1420 else \ 1421 { \ 1422 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1423 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1424 } \ 1425 }while(0) 1426 1427 /** 1428 * @} 1429 */ 1430 1431 /** @defgroup RCC_LSE_Configuration LSE Configuration 1432 * @{ 1433 */ 1434 1435 /** 1436 * @brief Macro to configure the External Low Speed oscillator (LSE). 1437 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 1438 * @note As the LSE is in the Backup domain and write access is denied to 1439 * this domain after reset, you have to enable write access using 1440 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1441 * (to be done once after reset). 1442 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1443 * software should wait on LSERDY flag to be set indicating that LSE clock 1444 * is stable and can be used to clock the RTC. 1445 * @param __STATE__ specifies the new state of the LSE. 1446 * This parameter can be one of the following values: 1447 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 1448 * 6 LSE oscillator clock cycles. 1449 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 1450 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1451 */ 1452 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1453 do{ \ 1454 if ((__STATE__) == RCC_LSE_ON) \ 1455 { \ 1456 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1457 } \ 1458 else if ((__STATE__) == RCC_LSE_OFF) \ 1459 { \ 1460 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1461 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1462 } \ 1463 else if ((__STATE__) == RCC_LSE_BYPASS) \ 1464 { \ 1465 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1466 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1467 } \ 1468 else \ 1469 { \ 1470 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1471 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1472 } \ 1473 }while(0) 1474 1475 /** 1476 * @} 1477 */ 1478 1479 /** @defgroup RCC_MSI_Configuration MSI Configuration 1480 * @{ 1481 */ 1482 1483 /** @brief Macro to enable Internal Multi Speed oscillator (MSI). 1484 * @note After enabling the MSI, the application software should wait on MSIRDY 1485 * flag to be set indicating that MSI clock is stable and can be used as 1486 * system clock source. 1487 */ 1488 #define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE) 1489 1490 /** @brief Macro to disable the Internal Multi Speed oscillator (MSI). 1491 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 1492 * It is used (enabled by hardware) as system clock source after startup 1493 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1494 * of the HSE used directly or indirectly as system clock (if the Clock 1495 * Security System CSS is enabled). 1496 * @note MSI can not be stopped if it is used as system clock source. In this case, 1497 * you have to select another source of the system clock then stop the MSI. 1498 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 1499 * clock cycles. 1500 */ 1501 #define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE) 1502 1503 /** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value. 1504 * @note The calibration is used to compensate for the variations in voltage 1505 * and temperature that influence the frequency of the internal MSI RC. 1506 * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value. 1507 * (default is RCC_MSICALIBRATION_DEFAULT). 1508 * This parameter must be a number between 0 and 0xFF. 1509 */ 1510 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ 1511 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM))) 1512 1513 /* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. 1514 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is 1515 * around 2.097 MHz. The MSI clock does not change after wake-up from 1516 * STOP mode. 1517 * @note The MSI clock range can be modified on the fly. 1518 * @param _MSIRANGEVALUE_ specifies the MSI Clock range. 1519 * This parameter must be one of the following values: 1520 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz 1521 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz 1522 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz 1523 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz 1524 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz 1525 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) 1526 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz 1527 */ 1528 #define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \ 1529 RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) 1530 1531 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 1532 * @retval MSI clock range. 1533 * This parameter must be one of the following values: 1534 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz 1535 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz 1536 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz 1537 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz 1538 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz 1539 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) 1540 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz 1541 */ 1542 #define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)) 1543 1544 /** 1545 * @} 1546 */ 1547 1548 /** @defgroup RCC_PLL_Configuration PLL Configuration 1549 * @{ 1550 */ 1551 1552 /** @brief Macro to enable the main PLL. 1553 * @note After enabling the main PLL, the application software should wait on 1554 * PLLRDY flag to be set indicating that PLL clock is stable and can 1555 * be used as system clock source. 1556 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1557 */ 1558 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 1559 1560 /** @brief Macro to disable the main PLL. 1561 * @note The main PLL can not be disabled if it is used as system clock source 1562 */ 1563 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 1564 1565 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 1566 * @note This function must be used only when the main PLL is disabled. 1567 * 1568 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 1569 * This parameter can be one of the following values: 1570 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 1571 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 1572 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 1573 * This parameter can be one of the following values: 1574 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 1575 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 1576 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 1577 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 1578 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 1579 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 1580 * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24 1581 * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32 1582 * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48 1583 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in 1584 * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is 1585 * in Range 3. 1586 * 1587 * @param __PLLDIV__ specifies the division factor for PLL VCO input clock 1588 * This parameter can be one of the following values: 1589 * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2 1590 * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3 1591 * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4 1592 * 1593 */ 1594 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ 1595 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) 1596 1597 /** @brief Get oscillator clock selected as PLL input clock 1598 * @retval The clock source used for PLL entry. The returned value can be one 1599 * of the following: 1600 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock 1601 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 1602 */ 1603 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 1604 1605 /** 1606 * @} 1607 */ 1608 1609 /** @defgroup RCC_Get_Clock_source Get Clock source 1610 * @{ 1611 */ 1612 1613 /** 1614 * @brief Macro to configure the system clock source. 1615 * @param __SYSCLKSOURCE__ specifies the system clock source. 1616 * This parameter can be one of the following values: 1617 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 1618 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1619 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1620 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 1621 */ 1622 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1623 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1624 1625 /** @brief Macro to get the clock source used as system clock. 1626 * @retval The clock source used as system clock. The returned value can be one 1627 * of the following: 1628 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock 1629 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 1630 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 1631 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 1632 */ 1633 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 1634 1635 /** 1636 * @} 1637 */ 1638 1639 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1640 * @{ 1641 */ 1642 1643 /** @brief Macro to configure the MCO clock. 1644 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1645 * This parameter can be one of the following values: 1646 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1647 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1648 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock 1649 * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock 1650 * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock 1651 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock 1652 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock 1653 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock 1654 * @param __MCODIV__ specifies the MCO clock prescaler. 1655 * This parameter can be one of the following values: 1656 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1657 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1658 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1659 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1660 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1661 */ 1662 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1663 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1664 1665 /** 1666 * @} 1667 */ 1668 1669 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1670 * @{ 1671 */ 1672 1673 /** @brief Macro to configure the RTC clock (RTCCLK). 1674 * @note As the RTC clock configuration bits are in the Backup domain and write 1675 * access is denied to this domain after reset, you have to enable write 1676 * access using the Power Backup Access macro before to configure 1677 * the RTC clock source (to be done once after reset). 1678 * @note Once the RTC clock is configured it cannot be changed unless the 1679 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1680 * a Power On Reset (POR). 1681 * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). 1682 * 1683 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1684 * This parameter can be one of the following values: 1685 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1686 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1687 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1688 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock 1689 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock 1690 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock 1691 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock 1692 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1693 * work in STOP and STANDBY modes, and can be used as wakeup source. 1694 * However, when the HSE clock is used as RTC clock source, the RTC 1695 * cannot be used in STOP and STANDBY modes. 1696 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1697 * RTC clock source). 1698 */ 1699 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ 1700 if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ 1701 { \ 1702 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ 1703 } \ 1704 } while (0) 1705 1706 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ 1707 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ 1708 RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ 1709 } while (0) 1710 1711 /** @brief Macro to get the RTC clock source. 1712 * @retval The clock source can be one of the following values: 1713 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1714 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1715 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1716 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 1717 */ 1718 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) 1719 1720 /** 1721 * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). 1722 * 1723 * @retval Returned value can be one of the following values: 1724 * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock 1725 * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock 1726 * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock 1727 * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock 1728 * 1729 */ 1730 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) 1731 1732 /** @brief Macro to enable the the RTC clock. 1733 * @note These macros must be used only after the RTC clock source was selected. 1734 */ 1735 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE) 1736 1737 /** @brief Macro to disable the the RTC clock. 1738 * @note These macros must be used only after the RTC clock source was selected. 1739 */ 1740 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE) 1741 1742 /** @brief Macro to force the Backup domain reset. 1743 * @note This function resets the RTC peripheral (including the backup registers) 1744 * and the RTC clock source selection in RCC_CSR register. 1745 * @note The BKPSRAM is not affected by this reset. 1746 */ 1747 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE) 1748 1749 /** @brief Macros to release the Backup domain reset. 1750 */ 1751 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE) 1752 1753 /** 1754 * @} 1755 */ 1756 1757 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1758 * @brief macros to manage the specified RCC Flags and interrupts. 1759 * @{ 1760 */ 1761 1762 /** @brief Enable RCC interrupt. 1763 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1764 * This parameter can be any combination of the following values: 1765 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1766 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1767 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1768 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1769 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1770 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1771 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) 1772 */ 1773 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1774 1775 /** @brief Disable RCC interrupt. 1776 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1777 * This parameter can be any combination of the following values: 1778 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1779 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1780 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1781 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1782 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1783 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1784 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) 1785 */ 1786 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1787 1788 /** @brief Clear the RCC's interrupt pending bits. 1789 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1790 * This parameter can be any combination of the following values: 1791 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1792 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1793 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1794 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1795 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1796 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1797 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) 1798 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1799 */ 1800 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1801 1802 /** @brief Check the RCC's interrupt has occurred or not. 1803 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1804 * This parameter can be one of the following values: 1805 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1806 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1807 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1808 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1809 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1810 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1811 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) 1812 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1813 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1814 */ 1815 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1816 1817 /** @brief Set RMVF bit to clear the reset flags. 1818 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1819 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1820 */ 1821 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1822 1823 /** @brief Check RCC flag is set or not. 1824 * @param __FLAG__ specifies the flag to check. 1825 * This parameter can be one of the following values: 1826 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 1827 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready. 1828 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 1829 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 1830 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 1831 * @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*) 1832 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 1833 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset 1834 * @arg @ref RCC_FLAG_PINRST Pin reset. 1835 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 1836 * @arg @ref RCC_FLAG_SFTRST Software reset. 1837 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 1838 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 1839 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 1840 * @note (*) This bit is available in high and medium+ density devices only. 1841 * @retval The new state of __FLAG__ (TRUE or FALSE). 1842 */ 1843 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) 1844 1845 /** 1846 * @} 1847 */ 1848 1849 /** 1850 * @} 1851 */ 1852 1853 /* Include RCC HAL Extension module */ 1854 #include "stm32l1xx_hal_rcc_ex.h" 1855 1856 /* Exported functions --------------------------------------------------------*/ 1857 /** @addtogroup RCC_Exported_Functions 1858 * @{ 1859 */ 1860 1861 /** @addtogroup RCC_Exported_Functions_Group1 1862 * @{ 1863 */ 1864 1865 /* Initialization and de-initialization functions ******************************/ 1866 void HAL_RCC_DeInit(void); 1867 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1868 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1869 1870 /** 1871 * @} 1872 */ 1873 1874 /** @addtogroup RCC_Exported_Functions_Group2 1875 * @{ 1876 */ 1877 1878 /* Peripheral Control functions ************************************************/ 1879 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1880 void HAL_RCC_EnableCSS(void); 1881 void HAL_RCC_DisableCSS(void); 1882 uint32_t HAL_RCC_GetSysClockFreq(void); 1883 uint32_t HAL_RCC_GetHCLKFreq(void); 1884 uint32_t HAL_RCC_GetPCLK1Freq(void); 1885 uint32_t HAL_RCC_GetPCLK2Freq(void); 1886 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1887 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1888 1889 /* CSS NMI IRQ handler */ 1890 void HAL_RCC_NMI_IRQHandler(void); 1891 1892 /* User Callbacks in non blocking mode (IT mode) */ 1893 void HAL_RCC_CSSCallback(void); 1894 1895 /** 1896 * @} 1897 */ 1898 1899 /** 1900 * @} 1901 */ 1902 1903 /** 1904 * @} 1905 */ 1906 1907 /** 1908 * @} 1909 */ 1910 1911 #ifdef __cplusplus 1912 } 1913 #endif 1914 1915 #endif /* __STM32L1xx_HAL_RCC_H */ 1916 1917 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1918 1919