1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements. 18These implementations are all weakly defined; they are provided to ease the 19porting effort. Each platform port can override them with its own implementation 20if the default implementation is inadequate. 21 22Some modifications are common to all Boot Loader (BL) stages. Section 2 23discusses these in detail. The subsequent sections discuss the remaining 24modifications for each BL stage in detail. 25 26Please refer to the :ref:`Platform Compatibility Policy` for the policy 27regarding compatibility and deprecation of these porting interfaces. 28 29Only Arm development platforms (such as FVP and Juno) may use the 30functions/definitions in ``include/plat/arm/common/`` and the corresponding 31source files in ``plat/arm/common/``. This is done so that there are no 32dependencies between platforms maintained by different people/companies. If you 33want to use any of the functionality present in ``plat/arm`` files, please 34create a pull request that moves the code to ``plat/common`` so that it can be 35discussed. 36 37Common modifications 38-------------------- 39 40This section covers the modifications that should be made by the platform for 41each BL stage to correctly port the firmware stack. They are categorized as 42either mandatory or optional. 43 44Common mandatory modifications 45------------------------------ 46 47A platform port must enable the Memory Management Unit (MMU) as well as the 48instruction and data caches for each BL stage. Setting up the translation 49tables is the responsibility of the platform port because memory maps differ 50across platforms. A memory translation library (see ``lib/xlat_tables/``) is 51provided to help in this setup. 52 53Note that although this library supports non-identity mappings, this is intended 54only for re-mapping peripheral physical addresses and allows platforms with high 55I/O addresses to reduce their virtual address space. All other addresses 56corresponding to code and data must currently use an identity mapping. 57 58Also, the only translation granule size supported in TF-A is 4KB, as various 59parts of the code assume that is the case. It is not possible to switch to 6016 KB or 64 KB granule sizes at the moment. 61 62In Arm standard platforms, each BL stage configures the MMU in the 63platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 64an identity mapping for all addresses. 65 66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 67block of identity mapped secure memory with Device-nGnRE attributes aligned to 68page boundary (4K) for each BL stage. All sections which allocate coherent 69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 71possible for the firmware to place variables in it using the following C code 72directive: 73 74:: 75 76 __section("bakery_lock") 77 78Or alternatively the following assembler code directive: 79 80:: 81 82 .section bakery_lock 83 84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 85used to allocate any data structures that are accessed both when a CPU is 86executing with its MMU and caches enabled, and when it's running with its MMU 87and caches disabled. Examples are given below. 88 89The following variables, functions and constants must be defined by the platform 90for the firmware to work correctly. 91 92File : platform_def.h [mandatory] 93~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 94 95Each platform must ensure that a header file of this name is in the system 96include path with the following constants defined. This will require updating 97the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 98 99Platform ports may optionally use the file ``include/plat/common/common_def.h``, 100which provides typical values for some of the constants below. These values are 101likely to be suitable for all platform ports. 102 103- **#define : PLATFORM_LINKER_FORMAT** 104 105 Defines the linker format used by the platform, for example 106 ``elf64-littleaarch64``. 107 108- **#define : PLATFORM_LINKER_ARCH** 109 110 Defines the processor architecture for the linker by the platform, for 111 example ``aarch64``. 112 113- **#define : PLATFORM_STACK_SIZE** 114 115 Defines the normal stack memory available to each CPU. This constant is used 116 by ``plat/common/aarch64/platform_mp_stack.S`` and 117 ``plat/common/aarch64/platform_up_stack.S``. 118 119- **#define : CACHE_WRITEBACK_GRANULE** 120 121 Defines the size in bits of the largest cache line across all the cache 122 levels in the platform. 123 124- **#define : FIRMWARE_WELCOME_STR** 125 126 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 127 function. 128 129- **#define : PLATFORM_CORE_COUNT** 130 131 Defines the total number of CPUs implemented by the platform across all 132 clusters in the system. 133 134- **#define : PLAT_NUM_PWR_DOMAINS** 135 136 Defines the total number of nodes in the power domain topology 137 tree at all the power domain levels used by the platform. 138 This macro is used by the PSCI implementation to allocate 139 data structures to represent power domain topology. 140 141- **#define : PLAT_MAX_PWR_LVL** 142 143 Defines the maximum power domain level that the power management operations 144 should apply to. More often, but not always, the power domain level 145 corresponds to affinity level. This macro allows the PSCI implementation 146 to know the highest power domain level that it should consider for power 147 management operations in the system that the platform implements. For 148 example, the Base AEM FVP implements two clusters with a configurable 149 number of CPUs and it reports the maximum power domain level as 1. 150 151- **#define : PLAT_MAX_OFF_STATE** 152 153 Defines the local power state corresponding to the deepest power down 154 possible at every power domain level in the platform. The local power 155 states for each level may be sparsely allocated between 0 and this value 156 with 0 being reserved for the RUN state. The PSCI implementation uses this 157 value to initialize the local power states of the power domain nodes and 158 to specify the requested power state for a PSCI_CPU_OFF call. 159 160- **#define : PLAT_MAX_RET_STATE** 161 162 Defines the local power state corresponding to the deepest retention state 163 possible at every power domain level in the platform. This macro should be 164 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 165 PSCI implementation to distinguish between retention and power down local 166 power states within PSCI_CPU_SUSPEND call. 167 168- **#define : PLAT_MAX_PWR_LVL_STATES** 169 170 Defines the maximum number of local power states per power domain level 171 that the platform supports. The default value of this macro is 2 since 172 most platforms just support a maximum of two local power states at each 173 power domain level (power-down and retention). If the platform needs to 174 account for more local power states, then it must redefine this macro. 175 176 Currently, this macro is used by the Generic PSCI implementation to size 177 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 178 179- **#define : BL1_RO_BASE** 180 181 Defines the base address in secure ROM where BL1 originally lives. Must be 182 aligned on a page-size boundary. 183 184- **#define : BL1_RO_LIMIT** 185 186 Defines the maximum address in secure ROM that BL1's actual content (i.e. 187 excluding any data section allocated at runtime) can occupy. 188 189- **#define : BL1_RW_BASE** 190 191 Defines the base address in secure RAM where BL1's read-write data will live 192 at runtime. Must be aligned on a page-size boundary. 193 194- **#define : BL1_RW_LIMIT** 195 196 Defines the maximum address in secure RAM that BL1's read-write data can 197 occupy at runtime. 198 199- **#define : BL2_BASE** 200 201 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 202 Must be aligned on a page-size boundary. This constant is not applicable 203 when BL2_IN_XIP_MEM is set to '1'. 204 205- **#define : BL2_LIMIT** 206 207 Defines the maximum address in secure RAM that the BL2 image can occupy. 208 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 209 210- **#define : BL2_RO_BASE** 211 212 Defines the base address in secure XIP memory where BL2 RO section originally 213 lives. Must be aligned on a page-size boundary. This constant is only needed 214 when BL2_IN_XIP_MEM is set to '1'. 215 216- **#define : BL2_RO_LIMIT** 217 218 Defines the maximum address in secure XIP memory that BL2's actual content 219 (i.e. excluding any data section allocated at runtime) can occupy. This 220 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 221 222- **#define : BL2_RW_BASE** 223 224 Defines the base address in secure RAM where BL2's read-write data will live 225 at runtime. Must be aligned on a page-size boundary. This constant is only 226 needed when BL2_IN_XIP_MEM is set to '1'. 227 228- **#define : BL2_RW_LIMIT** 229 230 Defines the maximum address in secure RAM that BL2's read-write data can 231 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 232 to '1'. 233 234- **#define : BL31_BASE** 235 236 Defines the base address in secure RAM where BL2 loads the BL31 binary 237 image. Must be aligned on a page-size boundary. 238 239- **#define : BL31_LIMIT** 240 241 Defines the maximum address in secure RAM that the BL31 image can occupy. 242 243For every image, the platform must define individual identifiers that will be 244used by BL1 or BL2 to load the corresponding image into memory from non-volatile 245storage. For the sake of performance, integer numbers will be used as 246identifiers. The platform will use those identifiers to return the relevant 247information about the image to be loaded (file handler, load address, 248authentication information, etc.). The following image identifiers are 249mandatory: 250 251- **#define : BL2_IMAGE_ID** 252 253 BL2 image identifier, used by BL1 to load BL2. 254 255- **#define : BL31_IMAGE_ID** 256 257 BL31 image identifier, used by BL2 to load BL31. 258 259- **#define : BL33_IMAGE_ID** 260 261 BL33 image identifier, used by BL2 to load BL33. 262 263If Trusted Board Boot is enabled, the following certificate identifiers must 264also be defined: 265 266- **#define : TRUSTED_BOOT_FW_CERT_ID** 267 268 BL2 content certificate identifier, used by BL1 to load the BL2 content 269 certificate. 270 271- **#define : TRUSTED_KEY_CERT_ID** 272 273 Trusted key certificate identifier, used by BL2 to load the trusted key 274 certificate. 275 276- **#define : SOC_FW_KEY_CERT_ID** 277 278 BL31 key certificate identifier, used by BL2 to load the BL31 key 279 certificate. 280 281- **#define : SOC_FW_CONTENT_CERT_ID** 282 283 BL31 content certificate identifier, used by BL2 to load the BL31 content 284 certificate. 285 286- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 287 288 BL33 key certificate identifier, used by BL2 to load the BL33 key 289 certificate. 290 291- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 292 293 BL33 content certificate identifier, used by BL2 to load the BL33 content 294 certificate. 295 296- **#define : FWU_CERT_ID** 297 298 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 299 FWU content certificate. 300 301- **#define : PLAT_CRYPTOCELL_BASE** 302 303 This defines the base address of Arm® TrustZone® CryptoCell and must be 304 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 305 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 306 set. 307 308If the AP Firmware Updater Configuration image, BL2U is used, the following 309must also be defined: 310 311- **#define : BL2U_BASE** 312 313 Defines the base address in secure memory where BL1 copies the BL2U binary 314 image. Must be aligned on a page-size boundary. 315 316- **#define : BL2U_LIMIT** 317 318 Defines the maximum address in secure memory that the BL2U image can occupy. 319 320- **#define : BL2U_IMAGE_ID** 321 322 BL2U image identifier, used by BL1 to fetch an image descriptor 323 corresponding to BL2U. 324 325If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 326must also be defined: 327 328- **#define : SCP_BL2U_IMAGE_ID** 329 330 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 331 corresponding to SCP_BL2U. 332 333 .. note:: 334 TF-A does not provide source code for this image. 335 336If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 337also be defined: 338 339- **#define : NS_BL1U_BASE** 340 341 Defines the base address in non-secure ROM where NS_BL1U executes. 342 Must be aligned on a page-size boundary. 343 344 .. note:: 345 TF-A does not provide source code for this image. 346 347- **#define : NS_BL1U_IMAGE_ID** 348 349 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 350 corresponding to NS_BL1U. 351 352If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 353be defined: 354 355- **#define : NS_BL2U_BASE** 356 357 Defines the base address in non-secure memory where NS_BL2U executes. 358 Must be aligned on a page-size boundary. 359 360 .. note:: 361 TF-A does not provide source code for this image. 362 363- **#define : NS_BL2U_IMAGE_ID** 364 365 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 366 corresponding to NS_BL2U. 367 368For the the Firmware update capability of TRUSTED BOARD BOOT, the following 369macros may also be defined: 370 371- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 372 373 Total number of images that can be loaded simultaneously. If the platform 374 doesn't specify any value, it defaults to 10. 375 376If a SCP_BL2 image is supported by the platform, the following constants must 377also be defined: 378 379- **#define : SCP_BL2_IMAGE_ID** 380 381 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 382 from platform storage before being transferred to the SCP. 383 384- **#define : SCP_FW_KEY_CERT_ID** 385 386 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 387 certificate (mandatory when Trusted Board Boot is enabled). 388 389- **#define : SCP_FW_CONTENT_CERT_ID** 390 391 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 392 content certificate (mandatory when Trusted Board Boot is enabled). 393 394If a BL32 image is supported by the platform, the following constants must 395also be defined: 396 397- **#define : BL32_IMAGE_ID** 398 399 BL32 image identifier, used by BL2 to load BL32. 400 401- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 402 403 BL32 key certificate identifier, used by BL2 to load the BL32 key 404 certificate (mandatory when Trusted Board Boot is enabled). 405 406- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 407 408 BL32 content certificate identifier, used by BL2 to load the BL32 content 409 certificate (mandatory when Trusted Board Boot is enabled). 410 411- **#define : BL32_BASE** 412 413 Defines the base address in secure memory where BL2 loads the BL32 binary 414 image. Must be aligned on a page-size boundary. 415 416- **#define : BL32_LIMIT** 417 418 Defines the maximum address that the BL32 image can occupy. 419 420If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 421platform, the following constants must also be defined: 422 423- **#define : TSP_SEC_MEM_BASE** 424 425 Defines the base address of the secure memory used by the TSP image on the 426 platform. This must be at the same address or below ``BL32_BASE``. 427 428- **#define : TSP_SEC_MEM_SIZE** 429 430 Defines the size of the secure memory used by the BL32 image on the 431 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 432 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 433 and ``BL32_LIMIT``. 434 435- **#define : TSP_IRQ_SEC_PHY_TIMER** 436 437 Defines the ID of the secure physical generic timer interrupt used by the 438 TSP's interrupt handling code. 439 440If the platform port uses the translation table library code, the following 441constants must also be defined: 442 443- **#define : PLAT_XLAT_TABLES_DYNAMIC** 444 445 Optional flag that can be set per-image to enable the dynamic allocation of 446 regions even when the MMU is enabled. If not defined, only static 447 functionality will be available, if defined and set to 1 it will also 448 include the dynamic functionality. 449 450- **#define : MAX_XLAT_TABLES** 451 452 Defines the maximum number of translation tables that are allocated by the 453 translation table library code. To minimize the amount of runtime memory 454 used, choose the smallest value needed to map the required virtual addresses 455 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 456 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 457 as well. 458 459- **#define : MAX_MMAP_REGIONS** 460 461 Defines the maximum number of regions that are allocated by the translation 462 table library code. A region consists of physical base address, virtual base 463 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 464 defined in the ``mmap_region_t`` structure. The platform defines the regions 465 that should be mapped. Then, the translation table library will create the 466 corresponding tables and descriptors at runtime. To minimize the amount of 467 runtime memory used, choose the smallest value needed to register the 468 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 469 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 470 the dynamic regions as well. 471 472- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 473 474 Defines the total size of the virtual address space in bytes. For example, 475 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 476 477- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 478 479 Defines the total size of the physical address space in bytes. For example, 480 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 481 482If the platform port uses the IO storage framework, the following constants 483must also be defined: 484 485- **#define : MAX_IO_DEVICES** 486 487 Defines the maximum number of registered IO devices. Attempting to register 488 more devices than this value using ``io_register_device()`` will fail with 489 -ENOMEM. 490 491- **#define : MAX_IO_HANDLES** 492 493 Defines the maximum number of open IO handles. Attempting to open more IO 494 entities than this value using ``io_open()`` will fail with -ENOMEM. 495 496- **#define : MAX_IO_BLOCK_DEVICES** 497 498 Defines the maximum number of registered IO block devices. Attempting to 499 register more devices this value using ``io_dev_open()`` will fail 500 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 501 With this macro, multiple block devices could be supported at the same 502 time. 503 504If the platform needs to allocate data within the per-cpu data framework in 505BL31, it should define the following macro. Currently this is only required if 506the platform decides not to use the coherent memory section by undefining the 507``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 508required memory within the the per-cpu data to minimize wastage. 509 510- **#define : PLAT_PCPU_DATA_SIZE** 511 512 Defines the memory (in bytes) to be reserved within the per-cpu data 513 structure for use by the platform layer. 514 515The following constants are optional. They should be defined when the platform 516memory layout implies some image overlaying like in Arm standard platforms. 517 518- **#define : BL31_PROGBITS_LIMIT** 519 520 Defines the maximum address in secure RAM that the BL31's progbits sections 521 can occupy. 522 523- **#define : TSP_PROGBITS_LIMIT** 524 525 Defines the maximum address that the TSP's progbits sections can occupy. 526 527If the platform port uses the PL061 GPIO driver, the following constant may 528optionally be defined: 529 530- **PLAT_PL061_MAX_GPIOS** 531 Maximum number of GPIOs required by the platform. This allows control how 532 much memory is allocated for PL061 GPIO controllers. The default value is 533 534 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 535 536If the platform port uses the partition driver, the following constant may 537optionally be defined: 538 539- **PLAT_PARTITION_MAX_ENTRIES** 540 Maximum number of partition entries required by the platform. This allows 541 control how much memory is allocated for partition entries. The default 542 value is 128. 543 For example, define the build flag in ``platform.mk``: 544 PLAT_PARTITION_MAX_ENTRIES := 12 545 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 546 547- **PLAT_PARTITION_BLOCK_SIZE** 548 The size of partition block. It could be either 512 bytes or 4096 bytes. 549 The default value is 512. 550 For example, define the build flag in ``platform.mk``: 551 PLAT_PARTITION_BLOCK_SIZE := 4096 552 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 553 554The following constant is optional. It should be defined to override the default 555behaviour of the ``assert()`` function (for example, to save memory). 556 557- **PLAT_LOG_LEVEL_ASSERT** 558 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 559 ``assert()`` prints the name of the file, the line number and the asserted 560 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 561 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 562 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 563 defined, it defaults to ``LOG_LEVEL``. 564 565If the platform port uses the Activity Monitor Unit, the following constant 566may be defined: 567 568- **PLAT_AMU_GROUP1_COUNTERS_MASK** 569 This mask reflects the set of group counters that should be enabled. The 570 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 571 can be at most 0xffff. If the platform does not define this mask, no group 1 572 counters are enabled. 573 574File : plat_macros.S [mandatory] 575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 576 577Each platform must ensure a file of this name is in the system include path with 578the following macro defined. In the Arm development platforms, this file is 579found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 580 581- **Macro : plat_crash_print_regs** 582 583 This macro allows the crash reporting routine to print relevant platform 584 registers in case of an unhandled exception in BL31. This aids in debugging 585 and this macro can be defined to be empty in case register reporting is not 586 desired. 587 588 For instance, GIC or interconnect registers may be helpful for 589 troubleshooting. 590 591Handling Reset 592-------------- 593 594BL1 by default implements the reset vector where execution starts from a cold 595or warm boot. BL31 can be optionally set as a reset vector using the 596``RESET_TO_BL31`` make variable. 597 598For each CPU, the reset vector code is responsible for the following tasks: 599 600#. Distinguishing between a cold boot and a warm boot. 601 602#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 603 the CPU is placed in a platform-specific state until the primary CPU 604 performs the necessary steps to remove it from this state. 605 606#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 607 specific address in the BL31 image in the same processor mode as it was 608 when released from reset. 609 610The following functions need to be implemented by the platform port to enable 611reset vector code to perform the above tasks. 612 613Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 614~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 615 616:: 617 618 Argument : void 619 Return : uintptr_t 620 621This function is called with the MMU and caches disabled 622(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 623distinguishing between a warm and cold reset for the current CPU using 624platform-specific means. If it's a warm reset, then it returns the warm 625reset entrypoint point provided to ``plat_setup_psci_ops()`` during 626BL31 initialization. If it's a cold reset then this function must return zero. 627 628This function does not follow the Procedure Call Standard used by the 629Application Binary Interface for the Arm 64-bit architecture. The caller should 630not assume that callee saved registers are preserved across a call to this 631function. 632 633This function fulfills requirement 1 and 3 listed above. 634 635Note that for platforms that support programming the reset address, it is 636expected that a CPU will start executing code directly at the right address, 637both on a cold and warm reset. In this case, there is no need to identify the 638type of reset nor to query the warm reset entrypoint. Therefore, implementing 639this function is not required on such platforms. 640 641Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 642~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 643 644:: 645 646 Argument : void 647 648This function is called with the MMU and data caches disabled. It is responsible 649for placing the executing secondary CPU in a platform-specific state until the 650primary CPU performs the necessary actions to bring it out of that state and 651allow entry into the OS. This function must not return. 652 653In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 654itself off. The primary CPU is responsible for powering up the secondary CPUs 655when normal world software requires them. When booting an EL3 payload instead, 656they stay powered on and are put in a holding pen until their mailbox gets 657populated. 658 659This function fulfills requirement 2 above. 660 661Note that for platforms that can't release secondary CPUs out of reset, only the 662primary CPU will execute the cold boot code. Therefore, implementing this 663function is not required on such platforms. 664 665Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 667 668:: 669 670 Argument : void 671 Return : unsigned int 672 673This function identifies whether the current CPU is the primary CPU or a 674secondary CPU. A return value of zero indicates that the CPU is not the 675primary CPU, while a non-zero return value indicates that the CPU is the 676primary CPU. 677 678Note that for platforms that can't release secondary CPUs out of reset, only the 679primary CPU will execute the cold boot code. Therefore, there is no need to 680distinguish between primary and secondary CPUs and implementing this function is 681not required. 682 683Function : platform_mem_init() [mandatory] 684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 685 686:: 687 688 Argument : void 689 Return : void 690 691This function is called before any access to data is made by the firmware, in 692order to carry out any essential memory initialization. 693 694Function: plat_get_rotpk_info() 695~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 696 697:: 698 699 Argument : void *, void **, unsigned int *, unsigned int * 700 Return : int 701 702This function is mandatory when Trusted Board Boot is enabled. It returns a 703pointer to the ROTPK stored in the platform (or a hash of it) and its length. 704The ROTPK must be encoded in DER format according to the following ASN.1 705structure: 706 707:: 708 709 AlgorithmIdentifier ::= SEQUENCE { 710 algorithm OBJECT IDENTIFIER, 711 parameters ANY DEFINED BY algorithm OPTIONAL 712 } 713 714 SubjectPublicKeyInfo ::= SEQUENCE { 715 algorithm AlgorithmIdentifier, 716 subjectPublicKey BIT STRING 717 } 718 719In case the function returns a hash of the key: 720 721:: 722 723 DigestInfo ::= SEQUENCE { 724 digestAlgorithm AlgorithmIdentifier, 725 digest OCTET STRING 726 } 727 728The function returns 0 on success. Any other value is treated as error by the 729Trusted Board Boot. The function also reports extra information related 730to the ROTPK in the flags parameter: 731 732:: 733 734 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 735 hash. 736 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 737 verification while the platform ROTPK is not deployed. 738 When this flag is set, the function does not need to 739 return a platform ROTPK, and the authentication 740 framework uses the ROTPK in the certificate without 741 verifying it against the platform value. This flag 742 must not be used in a deployed production environment. 743 744Function: plat_get_nv_ctr() 745~~~~~~~~~~~~~~~~~~~~~~~~~~~ 746 747:: 748 749 Argument : void *, unsigned int * 750 Return : int 751 752This function is mandatory when Trusted Board Boot is enabled. It returns the 753non-volatile counter value stored in the platform in the second argument. The 754cookie in the first argument may be used to select the counter in case the 755platform provides more than one (for example, on platforms that use the default 756TBBR CoT, the cookie will correspond to the OID values defined in 757TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 758 759The function returns 0 on success. Any other value means the counter value could 760not be retrieved from the platform. 761 762Function: plat_set_nv_ctr() 763~~~~~~~~~~~~~~~~~~~~~~~~~~~ 764 765:: 766 767 Argument : void *, unsigned int 768 Return : int 769 770This function is mandatory when Trusted Board Boot is enabled. It sets a new 771counter value in the platform. The cookie in the first argument may be used to 772select the counter (as explained in plat_get_nv_ctr()). The second argument is 773the updated counter value to be written to the NV counter. 774 775The function returns 0 on success. Any other value means the counter value could 776not be updated. 777 778Function: plat_set_nv_ctr2() 779~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 780 781:: 782 783 Argument : void *, const auth_img_desc_t *, unsigned int 784 Return : int 785 786This function is optional when Trusted Board Boot is enabled. If this 787interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 788first argument passed is a cookie and is typically used to 789differentiate between a Non Trusted NV Counter and a Trusted NV 790Counter. The second argument is a pointer to an authentication image 791descriptor and may be used to decide if the counter is allowed to be 792updated or not. The third argument is the updated counter value to 793be written to the NV counter. 794 795The function returns 0 on success. Any other value means the counter value 796either could not be updated or the authentication image descriptor indicates 797that it is not allowed to be updated. 798 799Common mandatory function modifications 800--------------------------------------- 801 802The following functions are mandatory functions which need to be implemented 803by the platform port. 804 805Function : plat_my_core_pos() 806~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 807 808:: 809 810 Argument : void 811 Return : unsigned int 812 813This function returns the index of the calling CPU which is used as a 814CPU-specific linear index into blocks of memory (for example while allocating 815per-CPU stacks). This function will be invoked very early in the 816initialization sequence which mandates that this function should be 817implemented in assembly and should not rely on the availability of a C 818runtime environment. This function can clobber x0 - x8 and must preserve 819x9 - x29. 820 821This function plays a crucial role in the power domain topology framework in 822PSCI and details of this can be found in 823:ref:`PSCI Power Domain Tree Structure`. 824 825Function : plat_core_pos_by_mpidr() 826~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 827 828:: 829 830 Argument : u_register_t 831 Return : int 832 833This function validates the ``MPIDR`` of a CPU and converts it to an index, 834which can be used as a CPU-specific linear index into blocks of memory. In 835case the ``MPIDR`` is invalid, this function returns -1. This function will only 836be invoked by BL31 after the power domain topology is initialized and can 837utilize the C runtime environment. For further details about how TF-A 838represents the power domain topology and how this relates to the linear CPU 839index, please refer :ref:`PSCI Power Domain Tree Structure`. 840 841Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 842~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 843 844:: 845 846 Arguments : void **heap_addr, size_t *heap_size 847 Return : int 848 849This function is invoked during Mbed TLS library initialisation to get a heap, 850by means of a starting address and a size. This heap will then be used 851internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 852must be able to provide a heap to it. 853 854A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 855which a heap is statically reserved during compile time inside every image 856(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 857the function simply returns the address and size of this "pre-allocated" heap. 858For a platform to use this default implementation, only a call to the helper 859from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 860 861However, by writting their own implementation, platforms have the potential to 862optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 863shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 864twice. 865 866On success the function should return 0 and a negative error code otherwise. 867 868Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 869~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 870 871:: 872 873 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 874 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 875 size_t img_id_len 876 Return : int 877 878This function provides a symmetric key (either SSK or BSSK depending on 879fw_enc_status) which is invoked during runtime decryption of encrypted 880firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 881implementation for testing purposes which must be overridden by the platform 882trying to implement a real world firmware encryption use-case. 883 884It also allows the platform to pass symmetric key identifier rather than 885actual symmetric key which is useful in cases where the crypto backend provides 886secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 887flag must be set in ``flags``. 888 889In addition to above a platform may also choose to provide an image specific 890symmetric key/identifier using img_id. 891 892On success the function should return 0 and a negative error code otherwise. 893 894Note that this API depends on ``DECRYPTION_SUPPORT`` build flag which is 895marked as experimental. 896 897Common optional modifications 898----------------------------- 899 900The following are helper functions implemented by the firmware that perform 901common platform-specific tasks. A platform may choose to override these 902definitions. 903 904Function : plat_set_my_stack() 905~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 906 907:: 908 909 Argument : void 910 Return : void 911 912This function sets the current stack pointer to the normal memory stack that 913has been allocated for the current CPU. For BL images that only require a 914stack for the primary CPU, the UP version of the function is used. The size 915of the stack allocated to each CPU is specified by the platform defined 916constant ``PLATFORM_STACK_SIZE``. 917 918Common implementations of this function for the UP and MP BL images are 919provided in ``plat/common/aarch64/platform_up_stack.S`` and 920``plat/common/aarch64/platform_mp_stack.S`` 921 922Function : plat_get_my_stack() 923~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 924 925:: 926 927 Argument : void 928 Return : uintptr_t 929 930This function returns the base address of the normal memory stack that 931has been allocated for the current CPU. For BL images that only require a 932stack for the primary CPU, the UP version of the function is used. The size 933of the stack allocated to each CPU is specified by the platform defined 934constant ``PLATFORM_STACK_SIZE``. 935 936Common implementations of this function for the UP and MP BL images are 937provided in ``plat/common/aarch64/platform_up_stack.S`` and 938``plat/common/aarch64/platform_mp_stack.S`` 939 940Function : plat_report_exception() 941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 942 943:: 944 945 Argument : unsigned int 946 Return : void 947 948A platform may need to report various information about its status when an 949exception is taken, for example the current exception level, the CPU security 950state (secure/non-secure), the exception type, and so on. This function is 951called in the following circumstances: 952 953- In BL1, whenever an exception is taken. 954- In BL2, whenever an exception is taken. 955 956The default implementation doesn't do anything, to avoid making assumptions 957about the way the platform displays its status information. 958 959For AArch64, this function receives the exception type as its argument. 960Possible values for exceptions types are listed in the 961``include/common/bl_common.h`` header file. Note that these constants are not 962related to any architectural exception code; they are just a TF-A convention. 963 964For AArch32, this function receives the exception mode as its argument. 965Possible values for exception modes are listed in the 966``include/lib/aarch32/arch.h`` header file. 967 968Function : plat_reset_handler() 969~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 970 971:: 972 973 Argument : void 974 Return : void 975 976A platform may need to do additional initialization after reset. This function 977allows the platform to do the platform specific initializations. Platform 978specific errata workarounds could also be implemented here. The API should 979preserve the values of callee saved registers x19 to x29. 980 981The default implementation doesn't do anything. If a platform needs to override 982the default implementation, refer to the :ref:`Firmware Design` for general 983guidelines. 984 985Function : plat_disable_acp() 986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 987 988:: 989 990 Argument : void 991 Return : void 992 993This API allows a platform to disable the Accelerator Coherency Port (if 994present) during a cluster power down sequence. The default weak implementation 995doesn't do anything. Since this API is called during the power down sequence, 996it has restrictions for stack usage and it can use the registers x0 - x17 as 997scratch registers. It should preserve the value in x18 register as it is used 998by the caller to store the return address. 999 1000Function : plat_error_handler() 1001~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1002 1003:: 1004 1005 Argument : int 1006 Return : void 1007 1008This API is called when the generic code encounters an error situation from 1009which it cannot continue. It allows the platform to perform error reporting or 1010recovery actions (for example, reset the system). This function must not return. 1011 1012The parameter indicates the type of error using standard codes from ``errno.h``. 1013Possible errors reported by the generic code are: 1014 1015- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1016 Board Boot is enabled) 1017- ``-ENOENT``: the requested image or certificate could not be found or an IO 1018 error was detected 1019- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1020 error is usually an indication of an incorrect array size 1021 1022The default implementation simply spins. 1023 1024Function : plat_panic_handler() 1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1026 1027:: 1028 1029 Argument : void 1030 Return : void 1031 1032This API is called when the generic code encounters an unexpected error 1033situation from which it cannot recover. This function must not return, 1034and must be implemented in assembly because it may be called before the C 1035environment is initialized. 1036 1037.. note:: 1038 The address from where it was called is stored in x30 (Link Register). 1039 The default implementation simply spins. 1040 1041Function : plat_get_bl_image_load_info() 1042~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1043 1044:: 1045 1046 Argument : void 1047 Return : bl_load_info_t * 1048 1049This function returns pointer to the list of images that the platform has 1050populated to load. This function is invoked in BL2 to load the 1051BL3xx images. 1052 1053Function : plat_get_next_bl_params() 1054~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1055 1056:: 1057 1058 Argument : void 1059 Return : bl_params_t * 1060 1061This function returns a pointer to the shared memory that the platform has 1062kept aside to pass TF-A related information that next BL image needs. This 1063function is invoked in BL2 to pass this information to the next BL 1064image. 1065 1066Function : plat_get_stack_protector_canary() 1067~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1068 1069:: 1070 1071 Argument : void 1072 Return : u_register_t 1073 1074This function returns a random value that is used to initialize the canary used 1075when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1076value will weaken the protection as the attacker could easily write the right 1077value as part of the attack most of the time. Therefore, it should return a 1078true random number. 1079 1080.. warning:: 1081 For the protection to be effective, the global data need to be placed at 1082 a lower address than the stack bases. Failure to do so would allow an 1083 attacker to overwrite the canary as part of the stack buffer overflow attack. 1084 1085Function : plat_flush_next_bl_params() 1086~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1087 1088:: 1089 1090 Argument : void 1091 Return : void 1092 1093This function flushes to main memory all the image params that are passed to 1094next image. This function is invoked in BL2 to flush this information 1095to the next BL image. 1096 1097Function : plat_log_get_prefix() 1098~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1099 1100:: 1101 1102 Argument : unsigned int 1103 Return : const char * 1104 1105This function defines the prefix string corresponding to the `log_level` to be 1106prepended to all the log output from TF-A. The `log_level` (argument) will 1107correspond to one of the standard log levels defined in debug.h. The platform 1108can override the common implementation to define a different prefix string for 1109the log output. The implementation should be robust to future changes that 1110increase the number of log levels. 1111 1112Function : plat_get_soc_version() 1113~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1114 1115:: 1116 1117 Argument : void 1118 Return : int32_t 1119 1120This function returns soc version which mainly consist of below fields 1121 1122:: 1123 1124 soc_version[30:24] = JEP-106 continuation code for the SiP 1125 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1126 soc_version[15:0] = Implementation defined SoC ID 1127 1128Function : plat_get_soc_revision() 1129~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1130 1131:: 1132 1133 Argument : void 1134 Return : int32_t 1135 1136This function returns soc revision in below format 1137 1138:: 1139 1140 soc_revision[0:30] = SOC revision of specific SOC 1141 1142Function : plat_is_smccc_feature_available() 1143~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1144 1145:: 1146 1147 Argument : u_register_t 1148 Return : int32_t 1149 1150This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1151the SMCCC function specified in the argument; otherwise returns 1152SMC_ARCH_CALL_NOT_SUPPORTED. 1153 1154Modifications specific to a Boot Loader stage 1155--------------------------------------------- 1156 1157Boot Loader Stage 1 (BL1) 1158------------------------- 1159 1160BL1 implements the reset vector where execution starts from after a cold or 1161warm boot. For each CPU, BL1 is responsible for the following tasks: 1162 1163#. Handling the reset as described in section 2.2 1164 1165#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1166 only this CPU executes the remaining BL1 code, including loading and passing 1167 control to the BL2 stage. 1168 1169#. Identifying and starting the Firmware Update process (if required). 1170 1171#. Loading the BL2 image from non-volatile storage into secure memory at the 1172 address specified by the platform defined constant ``BL2_BASE``. 1173 1174#. Populating a ``meminfo`` structure with the following information in memory, 1175 accessible by BL2 immediately upon entry. 1176 1177 :: 1178 1179 meminfo.total_base = Base address of secure RAM visible to BL2 1180 meminfo.total_size = Size of secure RAM visible to BL2 1181 1182 By default, BL1 places this ``meminfo`` structure at the end of secure 1183 memory visible to BL2. 1184 1185 It is possible for the platform to decide where it wants to place the 1186 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1187 BL2 by overriding the weak default implementation of 1188 ``bl1_plat_handle_post_image_load`` API. 1189 1190The following functions need to be implemented by the platform port to enable 1191BL1 to perform the above tasks. 1192 1193Function : bl1_early_platform_setup() [mandatory] 1194~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1195 1196:: 1197 1198 Argument : void 1199 Return : void 1200 1201This function executes with the MMU and data caches disabled. It is only called 1202by the primary CPU. 1203 1204On Arm standard platforms, this function: 1205 1206- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1207 1208- Initializes a UART (PL011 console), which enables access to the ``printf`` 1209 family of functions in BL1. 1210 1211- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1212 the CCI slave interface corresponding to the cluster that includes the 1213 primary CPU. 1214 1215Function : bl1_plat_arch_setup() [mandatory] 1216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1217 1218:: 1219 1220 Argument : void 1221 Return : void 1222 1223This function performs any platform-specific and architectural setup that the 1224platform requires. Platform-specific setup might include configuration of 1225memory controllers and the interconnect. 1226 1227In Arm standard platforms, this function enables the MMU. 1228 1229This function helps fulfill requirement 2 above. 1230 1231Function : bl1_platform_setup() [mandatory] 1232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1233 1234:: 1235 1236 Argument : void 1237 Return : void 1238 1239This function executes with the MMU and data caches enabled. It is responsible 1240for performing any remaining platform-specific setup that can occur after the 1241MMU and data cache have been enabled. 1242 1243if support for multiple boot sources is required, it initializes the boot 1244sequence used by plat_try_next_boot_source(). 1245 1246In Arm standard platforms, this function initializes the storage abstraction 1247layer used to load the next bootloader image. 1248 1249This function helps fulfill requirement 4 above. 1250 1251Function : bl1_plat_sec_mem_layout() [mandatory] 1252~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1253 1254:: 1255 1256 Argument : void 1257 Return : meminfo * 1258 1259This function should only be called on the cold boot path. It executes with the 1260MMU and data caches enabled. The pointer returned by this function must point to 1261a ``meminfo`` structure containing the extents and availability of secure RAM for 1262the BL1 stage. 1263 1264:: 1265 1266 meminfo.total_base = Base address of secure RAM visible to BL1 1267 meminfo.total_size = Size of secure RAM visible to BL1 1268 1269This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1270populates a similar structure to tell BL2 the extents of memory available for 1271its own use. 1272 1273This function helps fulfill requirements 4 and 5 above. 1274 1275Function : bl1_plat_prepare_exit() [optional] 1276~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1277 1278:: 1279 1280 Argument : entry_point_info_t * 1281 Return : void 1282 1283This function is called prior to exiting BL1 in response to the 1284``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1285platform specific clean up or bookkeeping operations before transferring 1286control to the next image. It receives the address of the ``entry_point_info_t`` 1287structure passed from BL2. This function runs with MMU disabled. 1288 1289Function : bl1_plat_set_ep_info() [optional] 1290~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1291 1292:: 1293 1294 Argument : unsigned int image_id, entry_point_info_t *ep_info 1295 Return : void 1296 1297This function allows platforms to override ``ep_info`` for the given ``image_id``. 1298 1299The default implementation just returns. 1300 1301Function : bl1_plat_get_next_image_id() [optional] 1302~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1303 1304:: 1305 1306 Argument : void 1307 Return : unsigned int 1308 1309This and the following function must be overridden to enable the FWU feature. 1310 1311BL1 calls this function after platform setup to identify the next image to be 1312loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1313with the normal boot sequence, which loads and executes BL2. If the platform 1314returns a different image id, BL1 assumes that Firmware Update is required. 1315 1316The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1317platforms override this function to detect if firmware update is required, and 1318if so, return the first image in the firmware update process. 1319 1320Function : bl1_plat_get_image_desc() [optional] 1321~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1322 1323:: 1324 1325 Argument : unsigned int image_id 1326 Return : image_desc_t * 1327 1328BL1 calls this function to get the image descriptor information ``image_desc_t`` 1329for the provided ``image_id`` from the platform. 1330 1331The default implementation always returns a common BL2 image descriptor. Arm 1332standard platforms return an image descriptor corresponding to BL2 or one of 1333the firmware update images defined in the Trusted Board Boot Requirements 1334specification. 1335 1336Function : bl1_plat_handle_pre_image_load() [optional] 1337~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1338 1339:: 1340 1341 Argument : unsigned int image_id 1342 Return : int 1343 1344This function can be used by the platforms to update/use image information 1345corresponding to ``image_id``. This function is invoked in BL1, both in cold 1346boot and FWU code path, before loading the image. 1347 1348Function : bl1_plat_handle_post_image_load() [optional] 1349~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1350 1351:: 1352 1353 Argument : unsigned int image_id 1354 Return : int 1355 1356This function can be used by the platforms to update/use image information 1357corresponding to ``image_id``. This function is invoked in BL1, both in cold 1358boot and FWU code path, after loading and authenticating the image. 1359 1360The default weak implementation of this function calculates the amount of 1361Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1362structure at the beginning of this free memory and populates it. The address 1363of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1364information to BL2. 1365 1366Function : bl1_plat_fwu_done() [optional] 1367~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1368 1369:: 1370 1371 Argument : unsigned int image_id, uintptr_t image_src, 1372 unsigned int image_size 1373 Return : void 1374 1375BL1 calls this function when the FWU process is complete. It must not return. 1376The platform may override this function to take platform specific action, for 1377example to initiate the normal boot flow. 1378 1379The default implementation spins forever. 1380 1381Function : bl1_plat_mem_check() [mandatory] 1382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1383 1384:: 1385 1386 Argument : uintptr_t mem_base, unsigned int mem_size, 1387 unsigned int flags 1388 Return : int 1389 1390BL1 calls this function while handling FWU related SMCs, more specifically when 1391copying or authenticating an image. Its responsibility is to ensure that the 1392region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1393that this memory corresponds to either a secure or non-secure memory region as 1394indicated by the security state of the ``flags`` argument. 1395 1396This function can safely assume that the value resulting from the addition of 1397``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1398overflow. 1399 1400This function must return 0 on success, a non-null error code otherwise. 1401 1402The default implementation of this function asserts therefore platforms must 1403override it when using the FWU feature. 1404 1405Boot Loader Stage 2 (BL2) 1406------------------------- 1407 1408The BL2 stage is executed only by the primary CPU, which is determined in BL1 1409using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1410``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1411``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1412non-volatile storage to secure/non-secure RAM. After all the images are loaded 1413then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1414images to be passed to the next BL image. 1415 1416The following functions must be implemented by the platform port to enable BL2 1417to perform the above tasks. 1418 1419Function : bl2_early_platform_setup2() [mandatory] 1420~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1421 1422:: 1423 1424 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1425 Return : void 1426 1427This function executes with the MMU and data caches disabled. It is only called 1428by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1429are platform specific. 1430 1431On Arm standard platforms, the arguments received are : 1432 1433 arg0 - Points to load address of FW_CONFIG 1434 1435 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1436 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1437 1438On Arm standard platforms, this function also: 1439 1440- Initializes a UART (PL011 console), which enables access to the ``printf`` 1441 family of functions in BL2. 1442 1443- Initializes the storage abstraction layer used to load further bootloader 1444 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1445 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1446 1447Function : bl2_plat_arch_setup() [mandatory] 1448~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1449 1450:: 1451 1452 Argument : void 1453 Return : void 1454 1455This function executes with the MMU and data caches disabled. It is only called 1456by the primary CPU. 1457 1458The purpose of this function is to perform any architectural initialization 1459that varies across platforms. 1460 1461On Arm standard platforms, this function enables the MMU. 1462 1463Function : bl2_platform_setup() [mandatory] 1464~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1465 1466:: 1467 1468 Argument : void 1469 Return : void 1470 1471This function may execute with the MMU and data caches enabled if the platform 1472port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1473called by the primary CPU. 1474 1475The purpose of this function is to perform any platform initialization 1476specific to BL2. 1477 1478In Arm standard platforms, this function performs security setup, including 1479configuration of the TrustZone controller to allow non-secure masters access 1480to most of DRAM. Part of DRAM is reserved for secure world use. 1481 1482Function : bl2_plat_handle_pre_image_load() [optional] 1483~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1484 1485:: 1486 1487 Argument : unsigned int 1488 Return : int 1489 1490This function can be used by the platforms to update/use image information 1491for given ``image_id``. This function is currently invoked in BL2 before 1492loading each image. 1493 1494Function : bl2_plat_handle_post_image_load() [optional] 1495~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1496 1497:: 1498 1499 Argument : unsigned int 1500 Return : int 1501 1502This function can be used by the platforms to update/use image information 1503for given ``image_id``. This function is currently invoked in BL2 after 1504loading each image. 1505 1506Function : bl2_plat_preload_setup [optional] 1507~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1508 1509:: 1510 1511 Argument : void 1512 Return : void 1513 1514This optional function performs any BL2 platform initialization 1515required before image loading, that is not done later in 1516bl2_platform_setup(). Specifically, if support for multiple 1517boot sources is required, it initializes the boot sequence used by 1518plat_try_next_boot_source(). 1519 1520Function : plat_try_next_boot_source() [optional] 1521~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1522 1523:: 1524 1525 Argument : void 1526 Return : int 1527 1528This optional function passes to the next boot source in the redundancy 1529sequence. 1530 1531This function moves the current boot redundancy source to the next 1532element in the boot sequence. If there are no more boot sources then it 1533must return 0, otherwise it must return 1. The default implementation 1534of this always returns 0. 1535 1536Boot Loader Stage 2 (BL2) at EL3 1537-------------------------------- 1538 1539When the platform has a non-TF-A Boot ROM it is desirable to jump 1540directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1541execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1542document for more information. 1543 1544All mandatory functions of BL2 must be implemented, except the functions 1545bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1546their work is done now by bl2_el3_early_platform_setup and 1547bl2_el3_plat_arch_setup. These functions should generally implement 1548the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1549 1550 1551Function : bl2_el3_early_platform_setup() [mandatory] 1552~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1553 1554:: 1555 1556 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1557 Return : void 1558 1559This function executes with the MMU and data caches disabled. It is only called 1560by the primary CPU. This function receives four parameters which can be used 1561by the platform to pass any needed information from the Boot ROM to BL2. 1562 1563On Arm standard platforms, this function does the following: 1564 1565- Initializes a UART (PL011 console), which enables access to the ``printf`` 1566 family of functions in BL2. 1567 1568- Initializes the storage abstraction layer used to load further bootloader 1569 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1570 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1571 1572- Initializes the private variables that define the memory layout used. 1573 1574Function : bl2_el3_plat_arch_setup() [mandatory] 1575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1576 1577:: 1578 1579 Argument : void 1580 Return : void 1581 1582This function executes with the MMU and data caches disabled. It is only called 1583by the primary CPU. 1584 1585The purpose of this function is to perform any architectural initialization 1586that varies across platforms. 1587 1588On Arm standard platforms, this function enables the MMU. 1589 1590Function : bl2_el3_plat_prepare_exit() [optional] 1591~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1592 1593:: 1594 1595 Argument : void 1596 Return : void 1597 1598This function is called prior to exiting BL2 and run the next image. 1599It should be used to perform platform specific clean up or bookkeeping 1600operations before transferring control to the next image. This function 1601runs with MMU disabled. 1602 1603FWU Boot Loader Stage 2 (BL2U) 1604------------------------------ 1605 1606The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1607process and is executed only by the primary CPU. BL1 passes control to BL2U at 1608``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1609 1610#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 1611 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 1612 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 1613 should be copied from. Subsequent handling of the SCP_BL2U image is 1614 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1615 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1616 1617#. Any platform specific setup required to perform the FWU process. For 1618 example, Arm standard platforms initialize the TZC controller so that the 1619 normal world can access DDR memory. 1620 1621The following functions must be implemented by the platform port to enable 1622BL2U to perform the tasks mentioned above. 1623 1624Function : bl2u_early_platform_setup() [mandatory] 1625~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1626 1627:: 1628 1629 Argument : meminfo *mem_info, void *plat_info 1630 Return : void 1631 1632This function executes with the MMU and data caches disabled. It is only 1633called by the primary CPU. The arguments to this function is the address 1634of the ``meminfo`` structure and platform specific info provided by BL1. 1635 1636The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1637private storage as the original memory may be subsequently overwritten by BL2U. 1638 1639On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1640to extract SCP_BL2U image information, which is then copied into a private 1641variable. 1642 1643Function : bl2u_plat_arch_setup() [mandatory] 1644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1645 1646:: 1647 1648 Argument : void 1649 Return : void 1650 1651This function executes with the MMU and data caches disabled. It is only 1652called by the primary CPU. 1653 1654The purpose of this function is to perform any architectural initialization 1655that varies across platforms, for example enabling the MMU (since the memory 1656map differs across platforms). 1657 1658Function : bl2u_platform_setup() [mandatory] 1659~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1660 1661:: 1662 1663 Argument : void 1664 Return : void 1665 1666This function may execute with the MMU and data caches enabled if the platform 1667port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1668called by the primary CPU. 1669 1670The purpose of this function is to perform any platform initialization 1671specific to BL2U. 1672 1673In Arm standard platforms, this function performs security setup, including 1674configuration of the TrustZone controller to allow non-secure masters access 1675to most of DRAM. Part of DRAM is reserved for secure world use. 1676 1677Function : bl2u_plat_handle_scp_bl2u() [optional] 1678~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1679 1680:: 1681 1682 Argument : void 1683 Return : int 1684 1685This function is used to perform any platform-specific actions required to 1686handle the SCP firmware. Typically it transfers the image into SCP memory using 1687a platform-specific protocol and waits until SCP executes it and signals to the 1688Application Processor (AP) for BL2U execution to continue. 1689 1690This function returns 0 on success, a negative error code otherwise. 1691This function is included if SCP_BL2U_BASE is defined. 1692 1693Boot Loader Stage 3-1 (BL31) 1694---------------------------- 1695 1696During cold boot, the BL31 stage is executed only by the primary CPU. This is 1697determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1698control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1699CPUs. BL31 executes at EL3 and is responsible for: 1700 1701#. Re-initializing all architectural and platform state. Although BL1 performs 1702 some of this initialization, BL31 remains resident in EL3 and must ensure 1703 that EL3 architectural and platform state is completely initialized. It 1704 should make no assumptions about the system state when it receives control. 1705 1706#. Passing control to a normal world BL image, pre-loaded at a platform- 1707 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 1708 populated by BL2 in memory to do this. 1709 1710#. Providing runtime firmware services. Currently, BL31 only implements a 1711 subset of the Power State Coordination Interface (PSCI) API as a runtime 1712 service. See Section 3.3 below for details of porting the PSCI 1713 implementation. 1714 1715#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1716 specific address by BL2. BL31 exports a set of APIs that allow runtime 1717 services to specify the security state in which the next image should be 1718 executed and run the corresponding image. On ARM platforms, BL31 uses the 1719 ``bl_params`` list populated by BL2 in memory to do this. 1720 1721If BL31 is a reset vector, It also needs to handle the reset as specified in 1722section 2.2 before the tasks described above. 1723 1724The following functions must be implemented by the platform port to enable BL31 1725to perform the above tasks. 1726 1727Function : bl31_early_platform_setup2() [mandatory] 1728~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1729 1730:: 1731 1732 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1733 Return : void 1734 1735This function executes with the MMU and data caches disabled. It is only called 1736by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 1737platform specific. 1738 1739In Arm standard platforms, the arguments received are : 1740 1741 arg0 - The pointer to the head of `bl_params_t` list 1742 which is list of executable images following BL31, 1743 1744 arg1 - Points to load address of SOC_FW_CONFIG if present 1745 except in case of Arm FVP and Juno platform. 1746 1747 In case of Arm FVP and Juno platform, points to load address 1748 of FW_CONFIG. 1749 1750 arg2 - Points to load address of HW_CONFIG if present 1751 1752 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 1753 used in release builds. 1754 1755The function runs through the `bl_param_t` list and extracts the entry point 1756information for BL32 and BL33. It also performs the following: 1757 1758- Initialize a UART (PL011 console), which enables access to the ``printf`` 1759 family of functions in BL31. 1760 1761- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1762 CCI slave interface corresponding to the cluster that includes the primary 1763 CPU. 1764 1765Function : bl31_plat_arch_setup() [mandatory] 1766~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1767 1768:: 1769 1770 Argument : void 1771 Return : void 1772 1773This function executes with the MMU and data caches disabled. It is only called 1774by the primary CPU. 1775 1776The purpose of this function is to perform any architectural initialization 1777that varies across platforms. 1778 1779On Arm standard platforms, this function enables the MMU. 1780 1781Function : bl31_platform_setup() [mandatory] 1782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1783 1784:: 1785 1786 Argument : void 1787 Return : void 1788 1789This function may execute with the MMU and data caches enabled if the platform 1790port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1791called by the primary CPU. 1792 1793The purpose of this function is to complete platform initialization so that both 1794BL31 runtime services and normal world software can function correctly. 1795 1796On Arm standard platforms, this function does the following: 1797 1798- Initialize the generic interrupt controller. 1799 1800 Depending on the GIC driver selected by the platform, the appropriate GICv2 1801 or GICv3 initialization will be done, which mainly consists of: 1802 1803 - Enable secure interrupts in the GIC CPU interface. 1804 - Disable the legacy interrupt bypass mechanism. 1805 - Configure the priority mask register to allow interrupts of all priorities 1806 to be signaled to the CPU interface. 1807 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1808 - Target all secure SPIs to CPU0. 1809 - Enable these secure interrupts in the GIC distributor. 1810 - Configure all other interrupts as non-secure. 1811 - Enable signaling of secure interrupts in the GIC distributor. 1812 1813- Enable system-level implementation of the generic timer counter through the 1814 memory mapped interface. 1815 1816- Grant access to the system counter timer module 1817 1818- Initialize the power controller device. 1819 1820 In particular, initialise the locks that prevent concurrent accesses to the 1821 power controller device. 1822 1823Function : bl31_plat_runtime_setup() [optional] 1824~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1825 1826:: 1827 1828 Argument : void 1829 Return : void 1830 1831The purpose of this function is allow the platform to perform any BL31 runtime 1832setup just prior to BL31 exit during cold boot. The default weak 1833implementation of this function will invoke ``console_switch_state()`` to switch 1834console output to consoles marked for use in the ``runtime`` state. 1835 1836Function : bl31_plat_get_next_image_ep_info() [mandatory] 1837~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1838 1839:: 1840 1841 Argument : uint32_t 1842 Return : entry_point_info * 1843 1844This function may execute with the MMU and data caches enabled if the platform 1845port does the necessary initializations in ``bl31_plat_arch_setup()``. 1846 1847This function is called by ``bl31_main()`` to retrieve information provided by 1848BL2 for the next image in the security state specified by the argument. BL31 1849uses this information to pass control to that image in the specified security 1850state. This function must return a pointer to the ``entry_point_info`` structure 1851(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1852should return NULL otherwise. 1853 1854Function : bl31_plat_enable_mmu [optional] 1855~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1856 1857:: 1858 1859 Argument : uint32_t 1860 Return : void 1861 1862This function enables the MMU. The boot code calls this function with MMU and 1863caches disabled. This function should program necessary registers to enable 1864translation, and upon return, the MMU on the calling PE must be enabled. 1865 1866The function must honor flags passed in the first argument. These flags are 1867defined by the translation library, and can be found in the file 1868``include/lib/xlat_tables/xlat_mmu_helpers.h``. 1869 1870On DynamIQ systems, this function must not use stack while enabling MMU, which 1871is how the function in xlat table library version 2 is implemented. 1872 1873Function : plat_init_apkey [optional] 1874~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1875 1876:: 1877 1878 Argument : void 1879 Return : uint128_t 1880 1881This function returns the 128-bit value which can be used to program ARMv8.3 1882pointer authentication keys. 1883 1884The value should be obtained from a reliable source of randomness. 1885 1886This function is only needed if ARMv8.3 pointer authentication is used in the 1887Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. 1888 1889Function : plat_get_syscnt_freq2() [mandatory] 1890~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1891 1892:: 1893 1894 Argument : void 1895 Return : unsigned int 1896 1897This function is used by the architecture setup code to retrieve the counter 1898frequency for the CPU's generic timer. This value will be programmed into the 1899``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 1900of the system counter, which is retrieved from the first entry in the frequency 1901modes table. 1902 1903Function : plat_arm_set_twedel_scr_el3() [optional] 1904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1905 1906:: 1907 1908 Argument : void 1909 Return : uint32_t 1910 1911This function is used in v8.6+ systems to set the WFE trap delay value in 1912SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this 1913feature is not enabled. The only hook provided is to set the TWED fields in 1914SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust 1915the WFE trap delays in lower ELs and these fields should be set by the 1916appropriate EL2 or EL1 code depending on the platform configuration. 1917 1918#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 1919~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1920 1921When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1922bytes) aligned to the cache line boundary that should be allocated per-cpu to 1923accommodate all the bakery locks. 1924 1925If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1926calculates the size of the ``bakery_lock`` input section, aligns it to the 1927nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1928and stores the result in a linker symbol. This constant prevents a platform 1929from relying on the linker and provide a more efficient mechanism for 1930accessing per-cpu bakery lock information. 1931 1932If this constant is defined and its value is not equal to the value 1933calculated by the linker then a link time assertion is raised. A compile time 1934assertion is raised if the value of the constant is not aligned to the cache 1935line boundary. 1936 1937.. _porting_guide_sdei_requirements: 1938 1939SDEI porting requirements 1940~~~~~~~~~~~~~~~~~~~~~~~~~ 1941 1942The |SDEI| dispatcher requires the platform to provide the following macros 1943and functions, of which some are optional, and some others mandatory. 1944 1945Macros 1946...... 1947 1948Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 1949^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1950 1951This macro must be defined to the EL3 exception priority level associated with 1952Normal |SDEI| events on the platform. This must have a higher value 1953(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 1954 1955Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 1956^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1957 1958This macro must be defined to the EL3 exception priority level associated with 1959Critical |SDEI| events on the platform. This must have a lower value 1960(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 1961 1962**Note**: |SDEI| exception priorities must be the lowest among Secure 1963priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 1964be higher than Normal |SDEI| priority. 1965 1966Functions 1967......... 1968 1969Function: int plat_sdei_validate_entry_point() [optional] 1970^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1971 1972:: 1973 1974 Argument: uintptr_t ep, unsigned int client_mode 1975 Return: int 1976 1977This function validates the entry point address of the event handler provided by 1978the client for both event registration and *Complete and Resume* |SDEI| calls. 1979The function ensures that the address is valid in the client translation regime. 1980 1981The second argument is the exception level that the client is executing in. It 1982can be Non-Secure EL1 or Non-Secure EL2. 1983 1984The function must return ``0`` for successful validation, or ``-1`` upon failure. 1985 1986The default implementation always returns ``0``. On Arm platforms, this function 1987translates the entry point address within the client translation regime and 1988further ensures that the resulting physical address is located in Non-secure 1989DRAM. 1990 1991Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 1992^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1993 1994:: 1995 1996 Argument: uint64_t 1997 Argument: unsigned int 1998 Return: void 1999 2000|SDEI| specification requires that a PE comes out of reset with the events 2001masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2002|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2003time. 2004 2005Should a PE receive an interrupt that was bound to an |SDEI| event while the 2006events are masked on the PE, the dispatcher implementation invokes the function 2007``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2008interrupt and the interrupt ID are passed as parameters. 2009 2010The default implementation only prints out a warning message. 2011 2012.. _porting_guide_trng_requirements: 2013 2014TRNG porting requirements 2015~~~~~~~~~~~~~~~~~~~~~~~~~ 2016 2017The |TRNG| backend requires the platform to provide the following values 2018and mandatory functions. 2019 2020Values 2021...... 2022 2023value: uuid_t plat_trng_uuid [mandatory] 2024^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2025 2026This value must be defined to the UUID of the TRNG backend that is specific to 2027the hardware after ``plat_trng_setup`` function is called. This value must 2028conform to the SMCCC calling convention; The most significant 32 bits of the 2029UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2030w0 indicates failure to get a TRNG source. 2031 2032Functions 2033......... 2034 2035Function: void plat_entropy_setup(void) [mandatory] 2036^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2037 2038:: 2039 2040 Argument: none 2041 Return: none 2042 2043This function is expected to do platform-specific initialization of any TRNG 2044hardware. This may include generating a UUID from a hardware-specific seed. 2045 2046Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2047^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2048 2049:: 2050 2051 Argument: uint64_t * 2052 Return: bool 2053 Out : when the return value is true, the entropy has been written into the 2054 storage pointed to 2055 2056This function writes entropy into storage provided by the caller. If no entropy 2057is available, it must return false and the storage must not be written. 2058 2059Power State Coordination Interface (in BL31) 2060-------------------------------------------- 2061 2062The TF-A implementation of the PSCI API is based around the concept of a 2063*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2064share some state on which power management operations can be performed as 2065specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2066a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2067*power domains* are arranged in a hierarchical tree structure and each 2068*power domain* can be identified in a system by the cpu index of any CPU that 2069is part of that domain and a *power domain level*. A processing element (for 2070example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2071logical grouping of CPUs that share some state, then level 1 is that group of 2072CPUs (for example, a cluster), and level 2 is a group of clusters (for 2073example, the system). More details on the power domain topology and its 2074organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2075 2076BL31's platform initialization code exports a pointer to the platform-specific 2077power management operations required for the PSCI implementation to function 2078correctly. This information is populated in the ``plat_psci_ops`` structure. The 2079PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2080power management operations on the power domains. For example, the target 2081CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2082handler (if present) is called for the CPU power domain. 2083 2084The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2085describe composite power states specific to a platform. The PSCI implementation 2086defines a generic representation of the power-state parameter, which is an 2087array of local power states where each index corresponds to a power domain 2088level. Each entry contains the local power state the power domain at that power 2089level could enter. It depends on the ``validate_power_state()`` handler to 2090convert the power-state parameter (possibly encoding a composite power state) 2091passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2092 2093The following functions form part of platform port of PSCI functionality. 2094 2095Function : plat_psci_stat_accounting_start() [optional] 2096~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2097 2098:: 2099 2100 Argument : const psci_power_state_t * 2101 Return : void 2102 2103This is an optional hook that platforms can implement for residency statistics 2104accounting before entering a low power state. The ``pwr_domain_state`` field of 2105``state_info`` (first argument) can be inspected if stat accounting is done 2106differently at CPU level versus higher levels. As an example, if the element at 2107index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2108state, special hardware logic may be programmed in order to keep track of the 2109residency statistics. For higher levels (array indices > 0), the residency 2110statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2111default implementation will use PMF to capture timestamps. 2112 2113Function : plat_psci_stat_accounting_stop() [optional] 2114~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2115 2116:: 2117 2118 Argument : const psci_power_state_t * 2119 Return : void 2120 2121This is an optional hook that platforms can implement for residency statistics 2122accounting after exiting from a low power state. The ``pwr_domain_state`` field 2123of ``state_info`` (first argument) can be inspected if stat accounting is done 2124differently at CPU level versus higher levels. As an example, if the element at 2125index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2126state, special hardware logic may be programmed in order to keep track of the 2127residency statistics. For higher levels (array indices > 0), the residency 2128statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2129default implementation will use PMF to capture timestamps. 2130 2131Function : plat_psci_stat_get_residency() [optional] 2132~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2133 2134:: 2135 2136 Argument : unsigned int, const psci_power_state_t *, unsigned int 2137 Return : u_register_t 2138 2139This is an optional interface that is is invoked after resuming from a low power 2140state and provides the time spent resident in that low power state by the power 2141domain at a particular power domain level. When a CPU wakes up from suspend, 2142all its parent power domain levels are also woken up. The generic PSCI code 2143invokes this function for each parent power domain that is resumed and it 2144identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2145argument) describes the low power state that the power domain has resumed from. 2146The current CPU is the first CPU in the power domain to resume from the low 2147power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2148CPU in the power domain to suspend and may be needed to calculate the residency 2149for that power domain. 2150 2151Function : plat_get_target_pwr_state() [optional] 2152~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2153 2154:: 2155 2156 Argument : unsigned int, const plat_local_state_t *, unsigned int 2157 Return : plat_local_state_t 2158 2159The PSCI generic code uses this function to let the platform participate in 2160state coordination during a power management operation. The function is passed 2161a pointer to an array of platform specific local power state ``states`` (second 2162argument) which contains the requested power state for each CPU at a particular 2163power domain level ``lvl`` (first argument) within the power domain. The function 2164is expected to traverse this array of upto ``ncpus`` (third argument) and return 2165a coordinated target power state by the comparing all the requested power 2166states. The target power state should not be deeper than any of the requested 2167power states. 2168 2169A weak definition of this API is provided by default wherein it assumes 2170that the platform assigns a local state value in order of increasing depth 2171of the power state i.e. for two power states X & Y, if X < Y 2172then X represents a shallower power state than Y. As a result, the 2173coordinated target local power state for a power domain will be the minimum 2174of the requested local power state values. 2175 2176Function : plat_get_power_domain_tree_desc() [mandatory] 2177~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2178 2179:: 2180 2181 Argument : void 2182 Return : const unsigned char * 2183 2184This function returns a pointer to the byte array containing the power domain 2185topology tree description. The format and method to construct this array are 2186described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2187initialization code requires this array to be described by the platform, either 2188statically or dynamically, to initialize the power domain topology tree. In case 2189the array is populated dynamically, then plat_core_pos_by_mpidr() and 2190plat_my_core_pos() should also be implemented suitably so that the topology tree 2191description matches the CPU indices returned by these APIs. These APIs together 2192form the platform interface for the PSCI topology framework. 2193 2194Function : plat_setup_psci_ops() [mandatory] 2195~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2196 2197:: 2198 2199 Argument : uintptr_t, const plat_psci_ops ** 2200 Return : int 2201 2202This function may execute with the MMU and data caches enabled if the platform 2203port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2204called by the primary CPU. 2205 2206This function is called by PSCI initialization code. Its purpose is to let 2207the platform layer know about the warm boot entrypoint through the 2208``sec_entrypoint`` (first argument) and to export handler routines for 2209platform-specific psci power management actions by populating the passed 2210pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2211 2212A description of each member of this structure is given below. Please refer to 2213the Arm FVP specific implementation of these handlers in 2214``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2215platform wants to support, the associated operation or operations in this 2216structure must be provided and implemented (Refer section 4 of 2217:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2218function in a platform port, the operation should be removed from this 2219structure instead of providing an empty implementation. 2220 2221plat_psci_ops.cpu_standby() 2222........................... 2223 2224Perform the platform-specific actions to enter the standby state for a cpu 2225indicated by the passed argument. This provides a fast path for CPU standby 2226wherein overheads of PSCI state management and lock acquisition is avoided. 2227For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2228the suspend state type specified in the ``power-state`` parameter should be 2229STANDBY and the target power domain level specified should be the CPU. The 2230handler should put the CPU into a low power retention state (usually by 2231issuing a wfi instruction) and ensure that it can be woken up from that 2232state by a normal interrupt. The generic code expects the handler to succeed. 2233 2234plat_psci_ops.pwr_domain_on() 2235............................. 2236 2237Perform the platform specific actions to power on a CPU, specified 2238by the ``MPIDR`` (first argument). The generic code expects the platform to 2239return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2240 2241plat_psci_ops.pwr_domain_off() 2242.............................. 2243 2244Perform the platform specific actions to prepare to power off the calling CPU 2245and its higher parent power domain levels as indicated by the ``target_state`` 2246(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2247 2248The ``target_state`` encodes the platform coordinated target local power states 2249for the CPU power domain and its parent power domain levels. The handler 2250needs to perform power management operation corresponding to the local state 2251at each power level. 2252 2253For this handler, the local power state for the CPU power domain will be a 2254power down state where as it could be either power down, retention or run state 2255for the higher power domain levels depending on the result of state 2256coordination. The generic code expects the handler to succeed. 2257 2258plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2259........................................................... 2260 2261This optional function may be used as a performance optimization to replace 2262or complement pwr_domain_suspend() on some platforms. Its calling semantics 2263are identical to pwr_domain_suspend(), except the PSCI implementation only 2264calls this function when suspending to a power down state, and it guarantees 2265that data caches are enabled. 2266 2267When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2268before calling pwr_domain_suspend(). If the target_state corresponds to a 2269power down state and it is safe to perform some or all of the platform 2270specific actions in that function with data caches enabled, it may be more 2271efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2272= 1, data caches remain enabled throughout, and so there is no advantage to 2273moving platform specific actions to this function. 2274 2275plat_psci_ops.pwr_domain_suspend() 2276.................................. 2277 2278Perform the platform specific actions to prepare to suspend the calling 2279CPU and its higher parent power domain levels as indicated by the 2280``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2281API implementation. 2282 2283The ``target_state`` has a similar meaning as described in 2284the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2285target local power states for the CPU power domain and its parent 2286power domain levels. The handler needs to perform power management operation 2287corresponding to the local state at each power level. The generic code 2288expects the handler to succeed. 2289 2290The difference between turning a power domain off versus suspending it is that 2291in the former case, the power domain is expected to re-initialize its state 2292when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2293case, the power domain is expected to save enough state so that it can resume 2294execution by restoring this state when its powered on (see 2295``pwr_domain_suspend_finish()``). 2296 2297When suspending a core, the platform can also choose to power off the GICv3 2298Redistributor and ITS through an implementation-defined sequence. To achieve 2299this safely, the ITS context must be saved first. The architectural part is 2300implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2301sequence is implementation defined and it is therefore the responsibility of 2302the platform code to implement the necessary sequence. Then the GIC 2303Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2304Powering off the Redistributor requires the implementation to support it and it 2305is the responsibility of the platform code to execute the right implementation 2306defined sequence. 2307 2308When a system suspend is requested, the platform can also make use of the 2309``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2310it has saved the context of the Redistributors and ITS of all the cores in the 2311system. The context of the Distributor can be large and may require it to be 2312allocated in a special area if it cannot fit in the platform's global static 2313data, for example in DRAM. The Distributor can then be powered down using an 2314implementation-defined sequence. 2315 2316plat_psci_ops.pwr_domain_pwr_down_wfi() 2317....................................... 2318 2319This is an optional function and, if implemented, is expected to perform 2320platform specific actions including the ``wfi`` invocation which allows the 2321CPU to powerdown. Since this function is invoked outside the PSCI locks, 2322the actions performed in this hook must be local to the CPU or the platform 2323must ensure that races between multiple CPUs cannot occur. 2324 2325The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2326operation and it encodes the platform coordinated target local power states for 2327the CPU power domain and its parent power domain levels. This function must 2328not return back to the caller. 2329 2330If this function is not implemented by the platform, PSCI generic 2331implementation invokes ``psci_power_down_wfi()`` for power down. 2332 2333plat_psci_ops.pwr_domain_on_finish() 2334.................................... 2335 2336This function is called by the PSCI implementation after the calling CPU is 2337powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2338It performs the platform-specific setup required to initialize enough state for 2339this CPU to enter the normal world and also provide secure runtime firmware 2340services. 2341 2342The ``target_state`` (first argument) is the prior state of the power domains 2343immediately before the CPU was turned on. It indicates which power domains 2344above the CPU might require initialization due to having previously been in 2345low power states. The generic code expects the handler to succeed. 2346 2347plat_psci_ops.pwr_domain_on_finish_late() [optional] 2348........................................................... 2349 2350This optional function is called by the PSCI implementation after the calling 2351CPU is fully powered on with respective data caches enabled. The calling CPU and 2352the associated cluster are guaranteed to be participating in coherency. This 2353function gives the flexibility to perform any platform-specific actions safely, 2354such as initialization or modification of shared data structures, without the 2355overhead of explicit cache maintainace operations. 2356 2357The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2358operation. The generic code expects the handler to succeed. 2359 2360plat_psci_ops.pwr_domain_suspend_finish() 2361......................................... 2362 2363This function is called by the PSCI implementation after the calling CPU is 2364powered on and released from reset in response to an asynchronous wakeup 2365event, for example a timer interrupt that was programmed by the CPU during the 2366``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2367setup required to restore the saved state for this CPU to resume execution 2368in the normal world and also provide secure runtime firmware services. 2369 2370The ``target_state`` (first argument) has a similar meaning as described in 2371the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2372to succeed. 2373 2374If the Distributor, Redistributors or ITS have been powered off as part of a 2375suspend, their context must be restored in this function in the reverse order 2376to how they were saved during suspend sequence. 2377 2378plat_psci_ops.system_off() 2379.......................... 2380 2381This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2382call. It performs the platform-specific system poweroff sequence after 2383notifying the Secure Payload Dispatcher. 2384 2385plat_psci_ops.system_reset() 2386............................ 2387 2388This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2389call. It performs the platform-specific system reset sequence after 2390notifying the Secure Payload Dispatcher. 2391 2392plat_psci_ops.validate_power_state() 2393.................................... 2394 2395This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2396call to validate the ``power_state`` parameter of the PSCI API and if valid, 2397populate it in ``req_state`` (second argument) array as power domain level 2398specific local states. If the ``power_state`` is invalid, the platform must 2399return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2400normal world PSCI client. 2401 2402plat_psci_ops.validate_ns_entrypoint() 2403...................................... 2404 2405This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2406``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2407parameter passed by the normal world. If the ``entry_point`` is invalid, 2408the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2409propagated back to the normal world PSCI client. 2410 2411plat_psci_ops.get_sys_suspend_power_state() 2412........................................... 2413 2414This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2415call to get the ``req_state`` parameter from platform which encodes the power 2416domain level specific local states to suspend to system affinity level. The 2417``req_state`` will be utilized to do the PSCI state coordination and 2418``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2419enter system suspend. 2420 2421plat_psci_ops.get_pwr_lvl_state_idx() 2422..................................... 2423 2424This is an optional function and, if implemented, is invoked by the PSCI 2425implementation to convert the ``local_state`` (first argument) at a specified 2426``pwr_lvl`` (second argument) to an index between 0 and 2427``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2428supports more than two local power states at each power domain level, that is 2429``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2430local power states. 2431 2432plat_psci_ops.translate_power_state_by_mpidr() 2433.............................................. 2434 2435This is an optional function and, if implemented, verifies the ``power_state`` 2436(second argument) parameter of the PSCI API corresponding to a target power 2437domain. The target power domain is identified by using both ``MPIDR`` (first 2438argument) and the power domain level encoded in ``power_state``. The power domain 2439level specific local states are to be extracted from ``power_state`` and be 2440populated in the ``output_state`` (third argument) array. The functionality 2441is similar to the ``validate_power_state`` function described above and is 2442envisaged to be used in case the validity of ``power_state`` depend on the 2443targeted power domain. If the ``power_state`` is invalid for the targeted power 2444domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 2445function is not implemented, then the generic implementation relies on 2446``validate_power_state`` function to translate the ``power_state``. 2447 2448This function can also be used in case the platform wants to support local 2449power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 2450APIs as described in Section 5.18 of `PSCI`_. 2451 2452plat_psci_ops.get_node_hw_state() 2453................................. 2454 2455This is an optional function. If implemented this function is intended to return 2456the power state of a node (identified by the first parameter, the ``MPIDR``) in 2457the power domain topology (identified by the second parameter, ``power_level``), 2458as retrieved from a power controller or equivalent component on the platform. 2459Upon successful completion, the implementation must map and return the final 2460status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2461must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2462appropriate. 2463 2464Implementations are not expected to handle ``power_levels`` greater than 2465``PLAT_MAX_PWR_LVL``. 2466 2467plat_psci_ops.system_reset2() 2468............................. 2469 2470This is an optional function. If implemented this function is 2471called during the ``SYSTEM_RESET2`` call to perform a reset 2472based on the first parameter ``reset_type`` as specified in 2473`PSCI`_. The parameter ``cookie`` can be used to pass additional 2474reset information. If the ``reset_type`` is not supported, the 2475function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2476resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2477and vendor reset can return other PSCI error codes as defined 2478in `PSCI`_. On success this function will not return. 2479 2480plat_psci_ops.write_mem_protect() 2481................................. 2482 2483This is an optional function. If implemented it enables or disables the 2484``MEM_PROTECT`` functionality based on the value of ``val``. 2485A non-zero value enables ``MEM_PROTECT`` and a value of zero 2486disables it. Upon encountering failures it must return a negative value 2487and on success it must return 0. 2488 2489plat_psci_ops.read_mem_protect() 2490................................ 2491 2492This is an optional function. If implemented it returns the current 2493state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2494failures it must return a negative value and on success it must 2495return 0. 2496 2497plat_psci_ops.mem_protect_chk() 2498............................... 2499 2500This is an optional function. If implemented it checks if a memory 2501region defined by a base address ``base`` and with a size of ``length`` 2502bytes is protected by ``MEM_PROTECT``. If the region is protected 2503then it must return 0, otherwise it must return a negative number. 2504 2505.. _porting_guide_imf_in_bl31: 2506 2507Interrupt Management framework (in BL31) 2508---------------------------------------- 2509 2510BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2511generated in either security state and targeted to EL1 or EL2 in the non-secure 2512state or EL3/S-EL1 in the secure state. The design of this framework is 2513described in the :ref:`Interrupt Management Framework` 2514 2515A platform should export the following APIs to support the IMF. The following 2516text briefly describes each API and its implementation in Arm standard 2517platforms. The API implementation depends upon the type of interrupt controller 2518present in the platform. Arm standard platform layer supports both 2519`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2520and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2521FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2522``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 2523details). 2524 2525See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 2526 2527Function : plat_interrupt_type_to_line() [mandatory] 2528~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2529 2530:: 2531 2532 Argument : uint32_t, uint32_t 2533 Return : uint32_t 2534 2535The Arm processor signals an interrupt exception either through the IRQ or FIQ 2536interrupt line. The specific line that is signaled depends on how the interrupt 2537controller (IC) reports different interrupt types from an execution context in 2538either security state. The IMF uses this API to determine which interrupt line 2539the platform IC uses to signal each type of interrupt supported by the framework 2540from a given security state. This API must be invoked at EL3. 2541 2542The first parameter will be one of the ``INTR_TYPE_*`` values (see 2543:ref:`Interrupt Management Framework`) indicating the target type of the 2544interrupt, the second parameter is the security state of the originating 2545execution context. The return result is the bit position in the ``SCR_EL3`` 2546register of the respective interrupt trap: IRQ=1, FIQ=2. 2547 2548In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2549configured as FIQs and Non-secure interrupts as IRQs from either security 2550state. 2551 2552In the case of Arm standard platforms using GICv3, the interrupt line to be 2553configured depends on the security state of the execution context when the 2554interrupt is signalled and are as follows: 2555 2556- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2557 NS-EL0/1/2 context. 2558- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2559 in the NS-EL0/1/2 context. 2560- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2561 context. 2562 2563Function : plat_ic_get_pending_interrupt_type() [mandatory] 2564~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2565 2566:: 2567 2568 Argument : void 2569 Return : uint32_t 2570 2571This API returns the type of the highest priority pending interrupt at the 2572platform IC. The IMF uses the interrupt type to retrieve the corresponding 2573handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2574pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2575``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2576 2577In the case of Arm standard platforms using GICv2, the *Highest Priority 2578Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2579the pending interrupt. The type of interrupt depends upon the id value as 2580follows. 2581 2582#. id < 1022 is reported as a S-EL1 interrupt 2583#. id = 1022 is reported as a Non-secure interrupt. 2584#. id = 1023 is reported as an invalid interrupt type. 2585 2586In the case of Arm standard platforms using GICv3, the system register 2587``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2588is read to determine the id of the pending interrupt. The type of interrupt 2589depends upon the id value as follows. 2590 2591#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2592#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2593#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2594#. All other interrupt id's are reported as EL3 interrupt. 2595 2596Function : plat_ic_get_pending_interrupt_id() [mandatory] 2597~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2598 2599:: 2600 2601 Argument : void 2602 Return : uint32_t 2603 2604This API returns the id of the highest priority pending interrupt at the 2605platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2606pending. 2607 2608In the case of Arm standard platforms using GICv2, the *Highest Priority 2609Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2610pending interrupt. The id that is returned by API depends upon the value of 2611the id read from the interrupt controller as follows. 2612 2613#. id < 1022. id is returned as is. 2614#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2615 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2616 This id is returned by the API. 2617#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2618 2619In the case of Arm standard platforms using GICv3, if the API is invoked from 2620EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2621group 0 Register*, is read to determine the id of the pending interrupt. The id 2622that is returned by API depends upon the value of the id read from the 2623interrupt controller as follows. 2624 2625#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2626#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2627 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2628 Register* is read to determine the id of the group 1 interrupt. This id 2629 is returned by the API as long as it is a valid interrupt id 2630#. If the id is any of the special interrupt identifiers, 2631 ``INTR_ID_UNAVAILABLE`` is returned. 2632 2633When the API invoked from S-EL1 for GICv3 systems, the id read from system 2634register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2635Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 2636``INTR_ID_UNAVAILABLE`` is returned. 2637 2638Function : plat_ic_acknowledge_interrupt() [mandatory] 2639~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2640 2641:: 2642 2643 Argument : void 2644 Return : uint32_t 2645 2646This API is used by the CPU to indicate to the platform IC that processing of 2647the highest pending interrupt has begun. It should return the raw, unmodified 2648value obtained from the interrupt controller when acknowledging an interrupt. 2649The actual interrupt number shall be extracted from this raw value using the API 2650`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 2651 2652This function in Arm standard platforms using GICv2, reads the *Interrupt 2653Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2654priority pending interrupt from pending to active in the interrupt controller. 2655It returns the value read from the ``GICC_IAR``, unmodified. 2656 2657In the case of Arm standard platforms using GICv3, if the API is invoked 2658from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2659Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2660reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2661group 1*. The read changes the state of the highest pending interrupt from 2662pending to active in the interrupt controller. The value read is returned 2663unmodified. 2664 2665The TSP uses this API to start processing of the secure physical timer 2666interrupt. 2667 2668Function : plat_ic_end_of_interrupt() [mandatory] 2669~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2670 2671:: 2672 2673 Argument : uint32_t 2674 Return : void 2675 2676This API is used by the CPU to indicate to the platform IC that processing of 2677the interrupt corresponding to the id (passed as the parameter) has 2678finished. The id should be the same as the id returned by the 2679``plat_ic_acknowledge_interrupt()`` API. 2680 2681Arm standard platforms write the id to the *End of Interrupt Register* 2682(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2683system register in case of GICv3 depending on where the API is invoked from, 2684EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2685controller. 2686 2687The TSP uses this API to finish processing of the secure physical timer 2688interrupt. 2689 2690Function : plat_ic_get_interrupt_type() [mandatory] 2691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2692 2693:: 2694 2695 Argument : uint32_t 2696 Return : uint32_t 2697 2698This API returns the type of the interrupt id passed as the parameter. 2699``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2700interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2701returned depending upon how the interrupt has been configured by the platform 2702IC. This API must be invoked at EL3. 2703 2704Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2705and Non-secure interrupts as Group1 interrupts. It reads the group value 2706corresponding to the interrupt id from the relevant *Interrupt Group Register* 2707(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2708 2709In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2710Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2711(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2712as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2713 2714Crash Reporting mechanism (in BL31) 2715----------------------------------- 2716 2717BL31 implements a crash reporting mechanism which prints the various registers 2718of the CPU to enable quick crash analysis and debugging. This mechanism relies 2719on the platform implementing ``plat_crash_console_init``, 2720``plat_crash_console_putc`` and ``plat_crash_console_flush``. 2721 2722The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 2723implementation of all of them. Platforms may include this file to their 2724makefiles in order to benefit from them. By default, they will cause the crash 2725output to be routed over the normal console infrastructure and get printed on 2726consoles configured to output in crash state. ``console_set_scope()`` can be 2727used to control whether a console is used for crash output. 2728 2729.. note:: 2730 Platforms are responsible for making sure that they only mark consoles for 2731 use in the crash scope that are able to support this, i.e. that are written 2732 in assembly and conform with the register clobber rules for putc() 2733 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 2734 2735In some cases (such as debugging very early crashes that happen before the 2736normal boot console can be set up), platforms may want to control crash output 2737more explicitly. These platforms may instead provide custom implementations for 2738these. They are executed outside of a C environment and without a stack. Many 2739console drivers provide functions named ``console_xxx_core_init/putc/flush`` 2740that are designed to be used by these functions. See Arm platforms (like juno) 2741for an example of this. 2742 2743Function : plat_crash_console_init [mandatory] 2744~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2745 2746:: 2747 2748 Argument : void 2749 Return : int 2750 2751This API is used by the crash reporting mechanism to initialize the crash 2752console. It must only use the general purpose registers x0 through x7 to do the 2753initialization and returns 1 on success. 2754 2755Function : plat_crash_console_putc [mandatory] 2756~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2757 2758:: 2759 2760 Argument : int 2761 Return : int 2762 2763This API is used by the crash reporting mechanism to print a character on the 2764designated crash console. It must only use general purpose registers x1 and 2765x2 to do its work. The parameter and the return value are in general purpose 2766register x0. 2767 2768Function : plat_crash_console_flush [mandatory] 2769~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2770 2771:: 2772 2773 Argument : void 2774 Return : void 2775 2776This API is used by the crash reporting mechanism to force write of all buffered 2777data on the designated crash console. It should only use general purpose 2778registers x0 through x5 to do its work. 2779 2780.. _External Abort handling and RAS Support: 2781 2782External Abort handling and RAS Support 2783--------------------------------------- 2784 2785Function : plat_ea_handler 2786~~~~~~~~~~~~~~~~~~~~~~~~~~ 2787 2788:: 2789 2790 Argument : int 2791 Argument : uint64_t 2792 Argument : void * 2793 Argument : void * 2794 Argument : uint64_t 2795 Return : void 2796 2797This function is invoked by the RAS framework for the platform to handle an 2798External Abort received at EL3. The intention of the function is to attempt to 2799resolve the cause of External Abort and return; if that's not possible, to 2800initiate orderly shutdown of the system. 2801 2802The first parameter (``int ea_reason``) indicates the reason for External Abort. 2803Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2804 2805The second parameter (``uint64_t syndrome``) is the respective syndrome 2806presented to EL3 after having received the External Abort. Depending on the 2807nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2808can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2809 2810The third parameter (``void *cookie``) is unused for now. The fourth parameter 2811(``void *handle``) is a pointer to the preempted context. The fifth parameter 2812(``uint64_t flags``) indicates the preempted security state. These parameters 2813are received from the top-level exception handler. 2814 2815If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2816function iterates through RAS handlers registered by the platform. If any of the 2817RAS handlers resolve the External Abort, no further action is taken. 2818 2819If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2820could resolve the External Abort, the default implementation prints an error 2821message, and panics. 2822 2823Function : plat_handle_uncontainable_ea 2824~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2825 2826:: 2827 2828 Argument : int 2829 Argument : uint64_t 2830 Return : void 2831 2832This function is invoked by the RAS framework when an External Abort of 2833Uncontainable type is received at EL3. Due to the critical nature of 2834Uncontainable errors, the intention of this function is to initiate orderly 2835shutdown of the system, and is not expected to return. 2836 2837This function must be implemented in assembly. 2838 2839The first and second parameters are the same as that of ``plat_ea_handler``. 2840 2841The default implementation of this function calls 2842``report_unhandled_exception``. 2843 2844Function : plat_handle_double_fault 2845~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2846 2847:: 2848 2849 Argument : int 2850 Argument : uint64_t 2851 Return : void 2852 2853This function is invoked by the RAS framework when another External Abort is 2854received at EL3 while one is already being handled. I.e., a call to 2855``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2856this function is to initiate orderly shutdown of the system, and is not expected 2857recover or return. 2858 2859This function must be implemented in assembly. 2860 2861The first and second parameters are the same as that of ``plat_ea_handler``. 2862 2863The default implementation of this function calls 2864``report_unhandled_exception``. 2865 2866Function : plat_handle_el3_ea 2867~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2868 2869:: 2870 2871 Return : void 2872 2873This function is invoked when an External Abort is received while executing in 2874EL3. Due to its critical nature, the intention of this function is to initiate 2875orderly shutdown of the system, and is not expected recover or return. 2876 2877This function must be implemented in assembly. 2878 2879The default implementation of this function calls 2880``report_unhandled_exception``. 2881 2882Build flags 2883----------- 2884 2885There are some build flags which can be defined by the platform to control 2886inclusion or exclusion of certain BL stages from the FIP image. These flags 2887need to be defined in the platform makefile which will get included by the 2888build system. 2889 2890- **NEED_BL33** 2891 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2892 build option should be supplied as a build option. The platform has the 2893 option of excluding the BL33 image in the ``fip`` image by defining this flag 2894 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2895 are used, this flag will be set to ``no`` automatically. 2896 2897Platform include paths 2898---------------------- 2899 2900Platforms are allowed to add more include paths to be passed to the compiler. 2901The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 2902particular for the file ``platform_def.h``. 2903 2904Example: 2905 2906.. code:: c 2907 2908 PLAT_INCLUDES += -Iinclude/plat/myplat/include 2909 2910C Library 2911--------- 2912 2913To avoid subtle toolchain behavioral dependencies, the header files provided 2914by the compiler are not used. The software is built with the ``-nostdinc`` flag 2915to ensure no headers are included from the toolchain inadvertently. Instead the 2916required headers are included in the TF-A source tree. The library only 2917contains those C library definitions required by the local implementation. If 2918more functionality is required, the needed library functions will need to be 2919added to the local implementation. 2920 2921Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 2922been written specifically for TF-A. Some implementation files have been obtained 2923from `FreeBSD`_, others have been written specifically for TF-A as well. The 2924files can be found in ``include/lib/libc`` and ``lib/libc``. 2925 2926SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 2927can be obtained from http://github.com/freebsd/freebsd. 2928 2929Storage abstraction layer 2930------------------------- 2931 2932In order to improve platform independence and portability a storage abstraction 2933layer is used to load data from non-volatile platform storage. Currently 2934storage access is only required by BL1 and BL2 phases and performed inside the 2935``load_image()`` function in ``bl_common.c``. 2936 2937.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml 2938 2939It is mandatory to implement at least one storage driver. For the Arm 2940development platforms the Firmware Image Package (FIP) driver is provided as 2941the default means to load data from storage (see :ref:`firmware_design_fip`). 2942The storage layer is described in the header file 2943``include/drivers/io/io_storage.h``. The implementation of the common library is 2944in ``drivers/io/io_storage.c`` and the driver files are located in 2945``drivers/io/``. 2946 2947.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml 2948 2949Each IO driver must provide ``io_dev_*`` structures, as described in 2950``drivers/io/io_driver.h``. These are returned via a mandatory registration 2951function that is called on platform initialization. The semi-hosting driver 2952implementation in ``io_semihosting.c`` can be used as an example. 2953 2954Each platform should register devices and their drivers via the storage 2955abstraction layer. These drivers then need to be initialized by bootloader 2956phases as required in their respective ``blx_platform_setup()`` functions. 2957 2958.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml 2959 2960The storage abstraction layer provides mechanisms (``io_dev_init()``) to 2961initialize storage devices before IO operations are called. 2962 2963.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml 2964 2965The basic operations supported by the layer 2966include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2967Drivers do not have to implement all operations, but each platform must 2968provide at least one driver for a device capable of supporting generic 2969operations such as loading a bootloader image. 2970 2971The current implementation only allows for known images to be loaded by the 2972firmware. These images are specified by using their identifiers, as defined in 2973``include/plat/common/common_def.h`` (or a separate header file included from 2974there). The platform layer (``plat_get_image_source()``) then returns a reference 2975to a device and a driver-specific ``spec`` which will be understood by the driver 2976to allow access to the image data. 2977 2978The layer is designed in such a way that is it possible to chain drivers with 2979other drivers. For example, file-system drivers may be implemented on top of 2980physical block devices, both represented by IO devices with corresponding 2981drivers. In such a case, the file-system "binding" with the block device may 2982be deferred until the file-system device is initialised. 2983 2984The abstraction currently depends on structures being statically allocated 2985by the drivers and callers, as the system does not yet provide a means of 2986dynamically allocating memory. This may also have the affect of limiting the 2987amount of open resources per driver. 2988 2989-------------- 2990 2991*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.* 2992 2993.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2994.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2995.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2996.. _FreeBSD: https://www.freebsd.org 2997.. _SCC: http://www.simple-cc.org/ 2998