1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <drivers/arm/cci.h>
9
10 #include "plat_ls.h"
11 #include "fsl_csu.h"
12
13 /* slave interfaces according to the RM */
14 static const int cci_map[] = {
15 4,
16 };
17
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)18 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
19 u_register_t arg2, u_register_t arg3)
20 {
21 #ifdef LS_BL2_IN_OCRAM
22 unsigned long romem_base = (unsigned long)(&__TEXT_START__);
23 unsigned long romem_size = (unsigned long)(&__RODATA_END__)
24 - romem_base;
25
26 /* Check the Text and RO-Data region size */
27 if (romem_size > BL31_TEXT_RODATA_SIZE) {
28 ERROR("BL31 Text and RO-Data region size exceed reserved memory size\n");
29 panic();
30 }
31 #endif
32
33 /*
34 * Initialize system level generic timer for Layerscape Socs.
35 */
36 ls_delay_timer_init();
37
38 ls_bl31_early_platform_setup((void *)arg0, (void *)arg3);
39
40 /*
41 * Initialize the correct interconnect for this cluster during cold
42 * boot. No need for locks as no other CPU is active.
43 */
44 cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
45
46 /*
47 * Enable coherency in interconnect for the primary CPU's cluster.
48 * Earlier bootloader stages might already do this (e.g. Trusted
49 * Firmware's BL1 does it) but we can't assume so. There is no harm in
50 * executing this code twice anyway.
51 */
52 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
53
54 /* Init CSU to enable non-secure access to peripherals */
55 enable_layerscape_ns_access();
56 }
57