1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef XLAT_TABLES_AARCH64_H 8 #define XLAT_TABLES_AARCH64_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 14 #if !defined(PAGE_SIZE) 15 #error "PAGE_SIZE is not defined." 16 #endif 17 18 /* 19 * Encode a Physical Address Space size for its use in TCR_ELx. 20 */ 21 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr); 22 23 /* 24 * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page 25 * granularity. For 4KB granularity, a level 0 table descriptor doesn't support 26 * block translation. For 16KB, the same thing happens to levels 0 and 1. For 27 * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture 28 * Reference Manual (DDI 0487A.k) for more information. 29 * 30 * The define below specifies the first table level that allows block 31 * descriptors. 32 */ 33 #if PAGE_SIZE == PAGE_SIZE_4KB 34 # define MIN_LVL_BLOCK_DESC U(1) 35 #elif (PAGE_SIZE == PAGE_SIZE_16KB) || (PAGE_SIZE == PAGE_SIZE_64KB) 36 # define MIN_LVL_BLOCK_DESC U(2) 37 #endif 38 39 #define XLAT_TABLE_LEVEL_MIN U(0) 40 41 /* 42 * Define the architectural limits of the virtual address space in AArch64 43 * state. 44 * 45 * TCR.TxSZ is calculated as 64 minus the width of said address space. 46 * The value of TCR.TxSZ must be in the range 16 to 39 [1] or 48 [2], 47 * depending on Small Translation Table Support which means that 48 * the virtual address space width must be in the range 48 to 25 or 16 bits. 49 * 50 * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 51 * information: 52 * Page 1730: 'Input address size', 'For all translation stages'. 53 * [2] See section 12.2.55 in the ARMv8-A Architecture Reference Manual 54 * (DDI 0487D.a) 55 */ 56 /* Maximum value of TCR_ELx.T(0,1)SZ is 39 */ 57 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MAX)) 58 59 /* Maximum value of TCR_ELx.T(0,1)SZ is 48 */ 60 #define MIN_VIRT_ADDR_SPACE_SIZE_TTST \ 61 (ULL(1) << (U(64) - TCR_TxSZ_MAX_TTST)) 62 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MIN)) 63 64 /* 65 * Here we calculate the initial lookup level from the value of the given 66 * virtual address space size. For a 4 KB page size, 67 * - level 0 supports virtual address spaces of widths 48 to 40 bits; 68 * - level 1 from 39 to 31; 69 * - level 2 from 30 to 22. 70 * - level 3 from 21 to 16. 71 * 72 * Small Translation Table (Armv8.4-TTST) support allows the starting level 73 * of the translation table from 3 for 4KB granularity. See section 12.2.55 in 74 * the ARMv8-A Architecture Reference Manual (DDI 0487D.a). In Armv8.3 and below 75 * wider or narrower address spaces are not supported. As a result, level 3 76 * cannot be used as initial lookup level with 4 KB granularity. See section 77 * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 78 * information. 79 * 80 * For example, for a 35-bit address space (i.e. virt_addr_space_size == 81 * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table 82 * D4-11 in the ARM ARM, the initial lookup level for an address space like that 83 * is 1. 84 * 85 * Note that this macro assumes that the given virtual address space size is 86 * valid. 87 */ 88 #define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz) \ 89 (((_virt_addr_space_sz) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \ 90 ? 0U \ 91 : (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \ 92 ? 1U \ 93 : (((_virt_addr_space_sz) > (ULL(1) << L2_XLAT_ADDRESS_SHIFT)) \ 94 ? 2U : 3U))) 95 96 #endif /* XLAT_TABLES_AARCH64_H */ 97