1 /** @file 2 Definition of the MMC Host Protocol 3 4 Copyright (c) 2011-2014, ARM Limited. All rights reserved. 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef __MMC_HOST_H__ 11 #define __MMC_HOST_H__ 12 13 /// 14 /// Global ID for the MMC Host Protocol 15 /// 16 #define EMBEDDED_MMC_HOST_PROTOCOL_GUID \ 17 { 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xD5, 0xC5, 0x1B } } 18 19 #define MMC_RESPONSE_TYPE_R1 0 20 #define MMC_RESPONSE_TYPE_R1b 0 21 #define MMC_RESPONSE_TYPE_R2 1 22 #define MMC_RESPONSE_TYPE_R3 0 23 #define MMC_RESPONSE_TYPE_R6 0 24 #define MMC_RESPONSE_TYPE_R7 0 25 #define MMC_RESPONSE_TYPE_OCR 0 26 #define MMC_RESPONSE_TYPE_CID 1 27 #define MMC_RESPONSE_TYPE_CSD 1 28 #define MMC_RESPONSE_TYPE_RCA 0 29 30 typedef UINT32 MMC_RESPONSE_TYPE; 31 32 typedef UINT32 MMC_CMD; 33 34 #define MMC_CMD_WAIT_RESPONSE (1 << 16) 35 #define MMC_CMD_LONG_RESPONSE (1 << 17) 36 #define MMC_CMD_NO_CRC_RESPONSE (1 << 18) 37 38 #define MMC_INDX(Index) ((Index) & 0xFFFF) 39 #define MMC_GET_INDX(MmcCmd) ((MmcCmd) & 0xFFFF) 40 41 #define MMC_CMD0 (MMC_INDX(0) | MMC_CMD_NO_CRC_RESPONSE) 42 #define MMC_CMD1 (MMC_INDX(1) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE) 43 #define MMC_CMD2 (MMC_INDX(2) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE) 44 #define MMC_CMD3 (MMC_INDX(3) | MMC_CMD_WAIT_RESPONSE) 45 #define MMC_CMD5 (MMC_INDX(5) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE) 46 #define MMC_CMD6 (MMC_INDX(6) | MMC_CMD_WAIT_RESPONSE) 47 #define MMC_CMD7 (MMC_INDX(7) | MMC_CMD_WAIT_RESPONSE) 48 #define MMC_CMD8 (MMC_INDX(8) | MMC_CMD_WAIT_RESPONSE) 49 #define MMC_CMD9 (MMC_INDX(9) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE) 50 #define MMC_CMD11 (MMC_INDX(11) | MMC_CMD_WAIT_RESPONSE) 51 #define MMC_CMD12 (MMC_INDX(12) | MMC_CMD_WAIT_RESPONSE) 52 #define MMC_CMD13 (MMC_INDX(13) | MMC_CMD_WAIT_RESPONSE) 53 #define MMC_CMD16 (MMC_INDX(16) | MMC_CMD_WAIT_RESPONSE) 54 #define MMC_CMD17 (MMC_INDX(17) | MMC_CMD_WAIT_RESPONSE) 55 #define MMC_CMD18 (MMC_INDX(18) | MMC_CMD_WAIT_RESPONSE) 56 #define MMC_CMD20 (MMC_INDX(20) | MMC_CMD_WAIT_RESPONSE) 57 #define MMC_CMD23 (MMC_INDX(23) | MMC_CMD_WAIT_RESPONSE) 58 #define MMC_CMD24 (MMC_INDX(24) | MMC_CMD_WAIT_RESPONSE) 59 #define MMC_CMD25 (MMC_INDX(25) | MMC_CMD_WAIT_RESPONSE) 60 #define MMC_CMD55 (MMC_INDX(55) | MMC_CMD_WAIT_RESPONSE) 61 #define MMC_ACMD41 (MMC_INDX(41) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE) 62 #define MMC_ACMD51 (MMC_INDX(51) | MMC_CMD_WAIT_RESPONSE) 63 64 // Valid responses for CMD1 in eMMC 65 #define EMMC_CMD1_CAPACITY_LESS_THAN_2GB 0x00FF8080 // Capacity <= 2GB, byte addressing used 66 #define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used 67 68 #define MMC_STATUS_APP_CMD (1 << 5) 69 70 typedef enum _MMC_STATE { 71 MmcInvalidState = 0, 72 MmcHwInitializationState, 73 MmcIdleState, 74 MmcReadyState, 75 MmcIdentificationState, 76 MmcStandByState, 77 MmcTransferState, 78 MmcSendingDataState, 79 MmcReceiveDataState, 80 MmcProgrammingState, 81 MmcDisconnectState, 82 } MMC_STATE; 83 84 #define EMMCBACKWARD (0) 85 #define EMMCHS26 (1 << 0) // High-Speed @26MHz at rated device voltages 86 #define EMMCHS52 (1 << 1) // High-Speed @52MHz at rated device voltages 87 #define EMMCHS52DDR1V8 (1 << 2) // High-Speed Dual Data Rate @52MHz 1.8V or 3V I/O 88 #define EMMCHS52DDR1V2 (1 << 3) // High-Speed Dual Data Rate @52MHz 1.2V I/O 89 #define EMMCHS200SDR1V8 (1 << 4) // HS200 Single Data Rate @200MHz 1.8V I/O 90 #define EMMCHS200SDR1V2 (1 << 5) // HS200 Single Data Rate @200MHz 1.2V I/O 91 #define EMMCHS400DDR1V8 (1 << 6) // HS400 Dual Data Rate @400MHz 1.8V I/O 92 #define EMMCHS400DDR1V2 (1 << 7) // HS400 Dual Data Rate @400MHz 1.2V I/O 93 94 /// 95 /// Forward declaration for EFI_MMC_HOST_PROTOCOL 96 /// 97 typedef struct _EFI_MMC_HOST_PROTOCOL EFI_MMC_HOST_PROTOCOL; 98 99 typedef BOOLEAN (EFIAPI *MMC_ISCARDPRESENT) ( 100 IN EFI_MMC_HOST_PROTOCOL *This 101 ); 102 103 typedef BOOLEAN (EFIAPI *MMC_ISREADONLY) ( 104 IN EFI_MMC_HOST_PROTOCOL *This 105 ); 106 107 typedef EFI_STATUS (EFIAPI *MMC_BUILDDEVICEPATH) ( 108 IN EFI_MMC_HOST_PROTOCOL *This, 109 OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath 110 ); 111 112 typedef EFI_STATUS (EFIAPI *MMC_NOTIFYSTATE) ( 113 IN EFI_MMC_HOST_PROTOCOL *This, 114 IN MMC_STATE State 115 ); 116 117 typedef EFI_STATUS (EFIAPI *MMC_SENDCOMMAND) ( 118 IN EFI_MMC_HOST_PROTOCOL *This, 119 IN MMC_CMD Cmd, 120 IN UINT32 Argument 121 ); 122 123 typedef EFI_STATUS (EFIAPI *MMC_RECEIVERESPONSE) ( 124 IN EFI_MMC_HOST_PROTOCOL *This, 125 IN MMC_RESPONSE_TYPE Type, 126 IN UINT32 *Buffer 127 ); 128 129 typedef EFI_STATUS (EFIAPI *MMC_READBLOCKDATA) ( 130 IN EFI_MMC_HOST_PROTOCOL *This, 131 IN EFI_LBA Lba, 132 IN UINTN Length, 133 OUT UINT32 *Buffer 134 ); 135 136 typedef EFI_STATUS (EFIAPI *MMC_WRITEBLOCKDATA) ( 137 IN EFI_MMC_HOST_PROTOCOL *This, 138 IN EFI_LBA Lba, 139 IN UINTN Length, 140 IN UINT32 *Buffer 141 ); 142 143 typedef EFI_STATUS (EFIAPI *MMC_SETIOS) ( 144 IN EFI_MMC_HOST_PROTOCOL *This, 145 IN UINT32 BusClockFreq, 146 IN UINT32 BusWidth, 147 IN UINT32 TimingMode 148 ); 149 150 typedef BOOLEAN (EFIAPI *MMC_ISMULTIBLOCK) ( 151 IN EFI_MMC_HOST_PROTOCOL *This 152 ); 153 154 struct _EFI_MMC_HOST_PROTOCOL { 155 156 UINT32 Revision; 157 MMC_ISCARDPRESENT IsCardPresent; 158 MMC_ISREADONLY IsReadOnly; 159 MMC_BUILDDEVICEPATH BuildDevicePath; 160 161 MMC_NOTIFYSTATE NotifyState; 162 163 MMC_SENDCOMMAND SendCommand; 164 MMC_RECEIVERESPONSE ReceiveResponse; 165 166 MMC_READBLOCKDATA ReadBlockData; 167 MMC_WRITEBLOCKDATA WriteBlockData; 168 169 MMC_SETIOS SetIos; 170 MMC_ISMULTIBLOCK IsMultiBlock; 171 172 }; 173 174 #define MMC_HOST_PROTOCOL_REVISION 0x00010002 // 1.2 175 176 #define MMC_HOST_HAS_SETIOS(Host) (Host->Revision >= MMC_HOST_PROTOCOL_REVISION && \ 177 Host->SetIos != NULL) 178 #define MMC_HOST_HAS_ISMULTIBLOCK(Host) (Host->Revision >= MMC_HOST_PROTOCOL_REVISION && \ 179 Host->IsMultiBlock != NULL) 180 181 extern EFI_GUID gEmbeddedMmcHostProtocolGuid; 182 183 #endif 184 185