1 /** @file 2 3 The definition for UHCI register operation routines. 4 5 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _EFI_UHCI_REG_H_ 11 #define _EFI_UHCI_REG_H_ 12 13 // 14 // UHCI register offset 15 // 16 17 #define UHCI_FRAME_NUM 1024 18 19 // 20 // Register offset and PCI related staff 21 // 22 #define USB_BAR_INDEX 4 23 24 #define USBCMD_OFFSET 0 25 #define USBSTS_OFFSET 2 26 #define USBINTR_OFFSET 4 27 #define USBPORTSC_OFFSET 0x10 28 #define USB_FRAME_NO_OFFSET 6 29 #define USB_FRAME_BASE_OFFSET 8 30 #define USB_EMULATION_OFFSET 0xC0 31 32 // 33 // Packet IDs 34 // 35 #define SETUP_PACKET_ID 0x2D 36 #define INPUT_PACKET_ID 0x69 37 #define OUTPUT_PACKET_ID 0xE1 38 #define ERROR_PACKET_ID 0x55 39 40 // 41 // USB port status and control bit definition. 42 // 43 #define USBPORTSC_CCS BIT0 // Current Connect Status 44 #define USBPORTSC_CSC BIT1 // Connect Status Change 45 #define USBPORTSC_PED BIT2 // Port Enable / Disable 46 #define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change 47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT 48 #define USBPORTSC_LSH BIT5 // Line Status High BIT 49 #define USBPORTSC_RD BIT6 // Resume Detect 50 #define USBPORTSC_LSDA BIT8 // Low Speed Device Attached 51 #define USBPORTSC_PR BIT9 // Port Reset 52 #define USBPORTSC_SUSP BIT12 // Suspend 53 54 // 55 // UHCI Spec said it must implement 2 ports each host at least, 56 // and if more, check whether the bit7 of PORTSC is always 1. 57 // So here assume the max of port number each host is 16. 58 // 59 #define USB_MAX_ROOTHUB_PORT 0x0F 60 61 // 62 // Command register bit definitions 63 // 64 #define USBCMD_RS BIT0 // Run/Stop 65 #define USBCMD_HCRESET BIT1 // Host reset 66 #define USBCMD_GRESET BIT2 // Global reset 67 #define USBCMD_EGSM BIT3 // Global Suspend Mode 68 #define USBCMD_FGR BIT4 // Force Global Resume 69 #define USBCMD_SWDBG BIT5 // SW Debug mode 70 #define USBCMD_CF BIT6 // Config Flag (sw only) 71 #define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64) 72 73 // 74 // USB Status register bit definitions 75 // 76 #define USBSTS_USBINT BIT0 // Interrupt due to IOC 77 #define USBSTS_ERROR BIT1 // Interrupt due to error 78 #define USBSTS_RD BIT2 // Resume Detect 79 #define USBSTS_HSE BIT3 // Host System Error 80 #define USBSTS_HCPE BIT4 // Host Controller Process Error 81 #define USBSTS_HCH BIT5 // HC Halted 82 83 #define USBTD_ACTIVE BIT7 // TD is still active 84 #define USBTD_STALLED BIT6 // TD is stalled 85 #define USBTD_BUFFERR BIT5 // Buffer underflow or overflow 86 #define USBTD_BABBLE BIT4 // Babble condition 87 #define USBTD_NAK BIT3 // NAK is received 88 #define USBTD_CRC BIT2 // CRC/Time out error 89 #define USBTD_BITSTUFF BIT1 // Bit stuff error 90 91 92 /** 93 Read a UHCI register. 94 95 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 96 @param Offset Register offset to USB_BAR_INDEX. 97 98 @return Content of register. 99 100 **/ 101 UINT16 102 UhciReadReg ( 103 IN EFI_PCI_IO_PROTOCOL *PciIo, 104 IN UINT32 Offset 105 ); 106 107 108 109 /** 110 Write data to UHCI register. 111 112 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 113 @param Offset Register offset to USB_BAR_INDEX. 114 @param Data Data to write. 115 116 @return None. 117 118 **/ 119 VOID 120 UhciWriteReg ( 121 IN EFI_PCI_IO_PROTOCOL *PciIo, 122 IN UINT32 Offset, 123 IN UINT16 Data 124 ); 125 126 127 128 /** 129 Set a bit of the UHCI Register. 130 131 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 132 @param Offset Register offset to USB_BAR_INDEX. 133 @param Bit The bit to set. 134 135 @return None. 136 137 **/ 138 VOID 139 UhciSetRegBit ( 140 IN EFI_PCI_IO_PROTOCOL *PciIo, 141 IN UINT32 Offset, 142 IN UINT16 Bit 143 ); 144 145 146 147 /** 148 Clear a bit of the UHCI Register. 149 150 @param PciIo The PCI_IO protocol to access the PCI. 151 @param Offset Register offset to USB_BAR_INDEX. 152 @param Bit The bit to clear. 153 154 @return None. 155 156 **/ 157 VOID 158 UhciClearRegBit ( 159 IN EFI_PCI_IO_PROTOCOL *PciIo, 160 IN UINT32 Offset, 161 IN UINT16 Bit 162 ); 163 164 165 /** 166 Clear all the interrutp status bits, these bits 167 are Write-Clean. 168 169 @param Uhc The UHCI device. 170 171 @return None. 172 173 **/ 174 VOID 175 UhciAckAllInterrupt ( 176 IN USB_HC_DEV *Uhc 177 ); 178 179 180 /** 181 Stop the host controller. 182 183 @param Uhc The UHCI device. 184 @param Timeout Max time allowed. 185 186 @retval EFI_SUCCESS The host controller is stopped. 187 @retval EFI_TIMEOUT Failed to stop the host controller. 188 189 **/ 190 EFI_STATUS 191 UhciStopHc ( 192 IN USB_HC_DEV *Uhc, 193 IN UINTN Timeout 194 ); 195 196 197 198 /** 199 Check whether the host controller operates well. 200 201 @param PciIo The PCI_IO protocol to use. 202 203 @retval TRUE Host controller is working. 204 @retval FALSE Host controller is halted or system error. 205 206 **/ 207 BOOLEAN 208 UhciIsHcWorking ( 209 IN EFI_PCI_IO_PROTOCOL *PciIo 210 ); 211 212 213 /** 214 Set the UHCI frame list base address. It can't use 215 UhciWriteReg which access memory in UINT16. 216 217 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 218 @param Addr Address to set. 219 220 @return None. 221 222 **/ 223 VOID 224 UhciSetFrameListBaseAddr ( 225 IN EFI_PCI_IO_PROTOCOL *PciIo, 226 IN VOID *Addr 227 ); 228 229 230 /** 231 Disable USB Emulation. 232 233 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use. 234 235 @return None. 236 237 **/ 238 VOID 239 UhciTurnOffUsbEmulation ( 240 IN EFI_PCI_IO_PROTOCOL *PciIo 241 ); 242 #endif 243