1 /** @file 2 3 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> 4 SPDX-License-Identifier: BSD-2-Clause-Patent 5 6 **/ 7 8 #ifndef _SD_HCI_H_ 9 #define _SD_HCI_H_ 10 11 // 12 // SD Host Controller MMIO Register Offset 13 // 14 #define SD_HC_SDMA_ADDR 0x00 15 #define SD_HC_ARG2 0x00 16 #define SD_HC_BLK_SIZE 0x04 17 #define SD_HC_BLK_COUNT 0x06 18 #define SD_HC_ARG1 0x08 19 #define SD_HC_TRANS_MOD 0x0C 20 #define SD_HC_COMMAND 0x0E 21 #define SD_HC_RESPONSE 0x10 22 #define SD_HC_BUF_DAT_PORT 0x20 23 #define SD_HC_PRESENT_STATE 0x24 24 #define SD_HC_HOST_CTRL1 0x28 25 #define SD_HC_POWER_CTRL 0x29 26 #define SD_HC_BLK_GAP_CTRL 0x2A 27 #define SD_HC_WAKEUP_CTRL 0x2B 28 #define SD_HC_CLOCK_CTRL 0x2C 29 #define SD_HC_TIMEOUT_CTRL 0x2E 30 #define SD_HC_SW_RST 0x2F 31 #define SD_HC_NOR_INT_STS 0x30 32 #define SD_HC_ERR_INT_STS 0x32 33 #define SD_HC_NOR_INT_STS_EN 0x34 34 #define SD_HC_ERR_INT_STS_EN 0x36 35 #define SD_HC_NOR_INT_SIG_EN 0x38 36 #define SD_HC_ERR_INT_SIG_EN 0x3A 37 #define SD_HC_AUTO_CMD_ERR_STS 0x3C 38 #define SD_HC_HOST_CTRL2 0x3E 39 #define SD_HC_CAP 0x40 40 #define SD_HC_MAX_CURRENT_CAP 0x48 41 #define SD_HC_FORCE_EVT_AUTO_CMD 0x50 42 #define SD_HC_FORCE_EVT_ERR_INT 0x52 43 #define SD_HC_ADMA_ERR_STS 0x54 44 #define SD_HC_ADMA_SYS_ADDR 0x58 45 #define SD_HC_PRESET_VAL 0x60 46 #define SD_HC_SHARED_BUS_CTRL 0xE0 47 #define SD_HC_SLOT_INT_STS 0xFC 48 #define SD_HC_CTRL_VER 0xFE 49 50 // 51 // The transfer modes supported by SD Host Controller 52 // Simplified Spec 3.0 Table 1-2 53 // 54 typedef enum { 55 SdNoData, 56 SdPioMode, 57 SdSdmaMode, 58 SdAdmaMode 59 } SD_HC_TRANSFER_MODE; 60 61 // 62 // The maximum data length of each descriptor line 63 // 64 #define ADMA_MAX_DATA_PER_LINE 0x10000 65 #define SD_SDMA_BOUNDARY 512 * 1024 66 #define SD_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) 67 68 typedef enum { 69 SdCommandTypeBc, // Broadcast commands, no response 70 SdCommandTypeBcr, // Broadcast commands with response 71 SdCommandTypeAc, // Addressed(point-to-point) commands 72 SdCommandTypeAdtc // Addressed(point-to-point) data transfer commands 73 } SD_COMMAND_TYPE; 74 75 typedef enum { 76 SdResponseTypeR1, 77 SdResponseTypeR1b, 78 SdResponseTypeR2, 79 SdResponseTypeR3, 80 SdResponseTypeR4, 81 SdResponseTypeR5, 82 SdResponseTypeR5b, 83 SdResponseTypeR6, 84 SdResponseTypeR7 85 } SD_RESPONSE_TYPE; 86 87 typedef struct _SD_COMMAND_BLOCK { 88 UINT16 CommandIndex; 89 UINT32 CommandArgument; 90 UINT32 CommandType; // One of the SD_COMMAND_TYPE values 91 UINT32 ResponseType; // One of the SD_RESPONSE_TYPE values 92 } SD_COMMAND_BLOCK; 93 94 typedef struct _SD_STATUS_BLOCK { 95 UINT32 Resp0; 96 UINT32 Resp1; 97 UINT32 Resp2; 98 UINT32 Resp3; 99 } SD_STATUS_BLOCK; 100 101 typedef struct _SD_COMMAND_PACKET { 102 UINT64 Timeout; 103 SD_COMMAND_BLOCK *SdCmdBlk; 104 SD_STATUS_BLOCK *SdStatusBlk; 105 VOID *InDataBuffer; 106 VOID *OutDataBuffer; 107 UINT32 InTransferLength; 108 UINT32 OutTransferLength; 109 } SD_COMMAND_PACKET; 110 111 #pragma pack(1) 112 113 typedef struct { 114 UINT32 Valid:1; 115 UINT32 End:1; 116 UINT32 Int:1; 117 UINT32 Reserved:1; 118 UINT32 Act:2; 119 UINT32 Reserved1:10; 120 UINT32 Length:16; 121 UINT32 Address; 122 } SD_HC_ADMA_DESC_LINE; 123 124 typedef struct { 125 UINT32 TimeoutFreq:6; // bit 0:5 126 UINT32 Reserved:1; // bit 6 127 UINT32 TimeoutUnit:1; // bit 7 128 UINT32 BaseClkFreq:8; // bit 8:15 129 UINT32 MaxBlkLen:2; // bit 16:17 130 UINT32 BusWidth8:1; // bit 18 131 UINT32 Adma2:1; // bit 19 132 UINT32 Reserved2:1; // bit 20 133 UINT32 HighSpeed:1; // bit 21 134 UINT32 Sdma:1; // bit 22 135 UINT32 SuspRes:1; // bit 23 136 UINT32 Voltage33:1; // bit 24 137 UINT32 Voltage30:1; // bit 25 138 UINT32 Voltage18:1; // bit 26 139 UINT32 Reserved3:1; // bit 27 140 UINT32 SysBus64:1; // bit 28 141 UINT32 AsyncInt:1; // bit 29 142 UINT32 SlotType:2; // bit 30:31 143 UINT32 Sdr50:1; // bit 32 144 UINT32 Sdr104:1; // bit 33 145 UINT32 Ddr50:1; // bit 34 146 UINT32 Reserved4:1; // bit 35 147 UINT32 DriverTypeA:1; // bit 36 148 UINT32 DriverTypeC:1; // bit 37 149 UINT32 DriverTypeD:1; // bit 38 150 UINT32 DriverType4:1; // bit 39 151 UINT32 TimerCount:4; // bit 40:43 152 UINT32 Reserved5:1; // bit 44 153 UINT32 TuningSDR50:1; // bit 45 154 UINT32 RetuningMod:2; // bit 46:47 155 UINT32 ClkMultiplier:8; // bit 48:55 156 UINT32 Reserved6:7; // bit 56:62 157 UINT32 Hs400:1; // bit 63 158 } SD_HC_SLOT_CAP; 159 160 #pragma pack() 161 162 /** 163 Software reset the specified SD host controller and enable all interrupts. 164 165 @param[in] Bar The mmio base address of the slot to be accessed. 166 167 @retval EFI_SUCCESS The software reset executes successfully. 168 @retval Others The software reset fails. 169 170 **/ 171 EFI_STATUS 172 SdPeimHcReset ( 173 IN UINTN Bar 174 ); 175 176 /** 177 Set all interrupt status bits in Normal and Error Interrupt Status Enable 178 register. 179 180 @param[in] Bar The mmio base address of the slot to be accessed. 181 182 @retval EFI_SUCCESS The operation executes successfully. 183 @retval Others The operation fails. 184 185 **/ 186 EFI_STATUS 187 SdPeimHcEnableInterrupt ( 188 IN UINTN Bar 189 ); 190 191 /** 192 Get the capability data from the specified slot. 193 194 @param[in] Bar The mmio base address of the slot to be accessed. 195 @param[out] Capability The buffer to store the capability data. 196 197 @retval EFI_SUCCESS The operation executes successfully. 198 @retval Others The operation fails. 199 200 **/ 201 EFI_STATUS 202 SdPeimHcGetCapability ( 203 IN UINTN Bar, 204 OUT SD_HC_SLOT_CAP *Capability 205 ); 206 207 /** 208 Detect whether there is a SD card attached at the specified SD host controller 209 slot. 210 211 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. 212 213 @param[in] Bar The mmio base address of the slot to be accessed. 214 215 @retval EFI_SUCCESS There is a SD card attached. 216 @retval EFI_NO_MEDIA There is not a SD card attached. 217 @retval Others The detection fails. 218 219 **/ 220 EFI_STATUS 221 SdPeimHcCardDetect ( 222 IN UINTN Bar 223 ); 224 225 /** 226 Initial SD host controller with lowest clock frequency, max power and max timeout value 227 at initialization. 228 229 @param[in] Bar The mmio base address of the slot to be accessed. 230 231 @retval EFI_SUCCESS The host controller is initialized successfully. 232 @retval Others The host controller isn't initialized successfully. 233 234 **/ 235 EFI_STATUS 236 SdPeimHcInitHost ( 237 IN UINTN Bar 238 ); 239 240 /** 241 Send command SWITCH_FUNC to the SD device to check switchable function or switch card function. 242 243 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. 244 245 @param[in] Slot The slot number of the SD card to send the command to. 246 @param[in] AccessMode The value for access mode group. 247 @param[in] CommandSystem The value for command set group. 248 @param[in] DriveStrength The value for drive length group. 249 @param[in] PowerLimit The value for power limit group. 250 @param[in] Mode Switch or check function. 251 @param[out] SwitchResp The return switch function status. 252 253 @retval EFI_SUCCESS The operation is done correctly. 254 @retval Others The operation fails. 255 256 **/ 257 EFI_STATUS 258 SdPeimSwitch ( 259 IN SD_PEIM_HC_SLOT *Slot, 260 IN UINT8 AccessMode, 261 IN UINT8 CommandSystem, 262 IN UINT8 DriveStrength, 263 IN UINT8 PowerLimit, 264 IN BOOLEAN Mode, 265 OUT UINT8 *SwitchResp 266 ); 267 268 /** 269 Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device 270 to read/write the specified number of blocks. 271 272 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. 273 274 @param[in] Slot The slot number of the SD card to send the command to. 275 @param[in] Lba The logical block address of starting access. 276 @param[in] BlockSize The block size of specified SD device partition. 277 @param[in] Buffer The pointer to the transfer buffer. 278 @param[in] BufferSize The size of transfer buffer. 279 @param[in] IsRead Boolean to show the operation direction. 280 281 @retval EFI_SUCCESS The operation is done correctly. 282 @retval Others The operation fails. 283 284 **/ 285 EFI_STATUS 286 SdPeimRwSingleBlock ( 287 IN SD_PEIM_HC_SLOT *Slot, 288 IN EFI_LBA Lba, 289 IN UINT32 BlockSize, 290 IN VOID *Buffer, 291 IN UINTN BufferSize, 292 IN BOOLEAN IsRead 293 ); 294 295 /** 296 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device 297 to read/write the specified number of blocks. 298 299 Refer to SD Electrical Standard Spec 5.1 Section 6.10.4 for details. 300 301 @param[in] Slot The slot number of the Sd card to send the command to. 302 @param[in] Lba The logical block address of starting access. 303 @param[in] BlockSize The block size of specified SD device partition. 304 @param[in] Buffer The pointer to the transfer buffer. 305 @param[in] BufferSize The size of transfer buffer. 306 @param[in] IsRead Boolean to show the operation direction. 307 308 @retval EFI_SUCCESS The operation is done correctly. 309 @retval Others The operation fails. 310 311 **/ 312 EFI_STATUS 313 SdPeimRwMultiBlocks ( 314 IN SD_PEIM_HC_SLOT *Slot, 315 IN EFI_LBA Lba, 316 IN UINT32 BlockSize, 317 IN VOID *Buffer, 318 IN UINTN BufferSize, 319 IN BOOLEAN IsRead 320 ); 321 322 /** 323 Execute SD device identification procedure. 324 325 Refer to SD Electrical Standard Spec 5.1 Section 6.4 for details. 326 327 @param[in] Slot The slot number of the Sd card to send the command to. 328 329 @retval EFI_SUCCESS There is a SD card. 330 @retval Others There is not a SD card. 331 332 **/ 333 EFI_STATUS 334 SdPeimIdentification ( 335 IN SD_PEIM_HC_SLOT *Slot 336 ); 337 338 /** 339 Free the resource used by the TRB. 340 341 @param[in] Trb The pointer to the SD_TRB instance. 342 343 **/ 344 VOID 345 SdPeimFreeTrb ( 346 IN SD_TRB *Trb 347 ); 348 349 #endif 350 351