1 /** @file 2 This file contains definitions for SPD DDR4. 3 4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 7 @par Revision Reference: 8 - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4 9 http://www.jedec.org/standards-documents/docs/spd412l-4 10 **/ 11 12 #ifndef _SDRAM_SPD_DDR4_H_ 13 #define _SDRAM_SPD_DDR4_H_ 14 15 #pragma pack (push, 1) 16 17 typedef union { 18 struct { 19 UINT8 BytesUsed : 4; ///< Bits 3:0 20 UINT8 BytesTotal : 3; ///< Bits 6:4 21 UINT8 CrcCoverage : 1; ///< Bits 7:7 22 } Bits; 23 UINT8 Data; 24 } SPD4_DEVICE_DESCRIPTION_STRUCT; 25 26 typedef union { 27 struct { 28 UINT8 Minor : 4; ///< Bits 3:0 29 UINT8 Major : 4; ///< Bits 7:4 30 } Bits; 31 UINT8 Data; 32 } SPD4_REVISION_STRUCT; 33 34 typedef union { 35 struct { 36 UINT8 Type : 8; ///< Bits 7:0 37 } Bits; 38 UINT8 Data; 39 } SPD4_DRAM_DEVICE_TYPE_STRUCT; 40 41 typedef union { 42 struct { 43 UINT8 ModuleType : 4; ///< Bits 3:0 44 UINT8 HybridMedia : 3; ///< Bits 6:4 45 UINT8 Hybrid : 1; ///< Bits 7:7 46 } Bits; 47 UINT8 Data; 48 } SPD4_MODULE_TYPE_STRUCT; 49 50 typedef union { 51 struct { 52 UINT8 Density : 4; ///< Bits 3:0 53 UINT8 BankAddress : 2; ///< Bits 5:4 54 UINT8 BankGroup : 2; ///< Bits 7:6 55 } Bits; 56 UINT8 Data; 57 } SPD4_SDRAM_DENSITY_BANKS_STRUCT; 58 59 typedef union { 60 struct { 61 UINT8 ColumnAddress : 3; ///< Bits 2:0 62 UINT8 RowAddress : 3; ///< Bits 5:3 63 UINT8 Reserved : 2; ///< Bits 7:6 64 } Bits; 65 UINT8 Data; 66 } SPD4_SDRAM_ADDRESSING_STRUCT; 67 68 typedef union { 69 struct { 70 UINT8 SignalLoading : 2; ///< Bits 1:0 71 UINT8 Reserved : 2; ///< Bits 3:2 72 UINT8 DieCount : 3; ///< Bits 6:4 73 UINT8 SdramPackageType : 1; ///< Bits 7:7 74 } Bits; 75 UINT8 Data; 76 } SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT; 77 78 typedef union { 79 struct { 80 UINT8 MaximumActivateCount : 4; ///< Bits 3:0 81 UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 82 UINT8 Reserved : 2; ///< Bits 7:6 83 } Bits; 84 UINT8 Data; 85 } SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT; 86 87 typedef union { 88 struct { 89 UINT8 Reserved : 8; ///< Bits 7:0 90 } Bits; 91 UINT8 Data; 92 } SPD4_SDRAM_THERMAL_REFRESH_STRUCT; 93 94 typedef union { 95 struct { 96 UINT8 Reserved : 5; ///< Bits 4:0 97 UINT8 SoftPPR : 1; ///< Bits 5:5 98 UINT8 PostPackageRepair : 2; ///< Bits 7:6 99 } Bits; 100 UINT8 Data; 101 } SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT; 102 103 typedef union { 104 struct { 105 UINT8 SignalLoading : 2; ///< Bits 1:0 106 UINT8 DRAMDensityRatio : 2; ///< Bits 3:2 107 UINT8 DieCount : 3; ///< Bits 6:4 108 UINT8 SdramPackageType : 1; ///< Bits 7:7 109 } Bits; 110 UINT8 Data; 111 } SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT; 112 113 typedef union { 114 struct { 115 UINT8 OperationAt1_20 : 1; ///< Bits 0:0 116 UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 117 UINT8 Reserved : 6; ///< Bits 7:2 118 } Bits; 119 UINT8 Data; 120 } SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT; 121 122 typedef union { 123 struct { 124 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 125 UINT8 RankCount : 3; ///< Bits 5:3 126 UINT8 RankMix : 1; ///< Bits 6:6 127 UINT8 Reserved : 1; ///< Bits 7:7 128 } Bits; 129 UINT8 Data; 130 } SPD4_MODULE_ORGANIZATION_STRUCT; 131 132 typedef union { 133 struct { 134 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 135 UINT8 BusWidthExtension : 2; ///< Bits 4:3 136 UINT8 Reserved : 3; ///< Bits 7:5 137 } Bits; 138 UINT8 Data; 139 } SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT; 140 141 typedef union { 142 struct { 143 UINT8 Reserved : 7; ///< Bits 6:0 144 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 145 } Bits; 146 UINT8 Data; 147 } SPD4_MODULE_THERMAL_SENSOR_STRUCT; 148 149 typedef union { 150 struct { 151 UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0 152 UINT8 Reserved : 4; ///< Bits 7:4 153 } Bits; 154 UINT8 Data; 155 } SPD4_EXTENDED_MODULE_TYPE_STRUCT; 156 157 typedef union { 158 struct { 159 UINT8 Fine : 2; ///< Bits 1:0 160 UINT8 Medium : 2; ///< Bits 3:2 161 UINT8 Reserved : 4; ///< Bits 7:4 162 } Bits; 163 UINT8 Data; 164 } SPD4_TIMEBASE_STRUCT; 165 166 typedef union { 167 struct { 168 UINT8 tCKmin : 8; ///< Bits 7:0 169 } Bits; 170 UINT8 Data; 171 } SPD4_TCK_MIN_MTB_STRUCT; 172 173 typedef union { 174 struct { 175 UINT8 tCKmax : 8; ///< Bits 7:0 176 } Bits; 177 UINT8 Data; 178 } SPD4_TCK_MAX_MTB_STRUCT; 179 180 typedef union { 181 struct { 182 UINT32 Cl7 : 1; ///< Bits 0:0 183 UINT32 Cl8 : 1; ///< Bits 1:1 184 UINT32 Cl9 : 1; ///< Bits 2:2 185 UINT32 Cl10 : 1; ///< Bits 3:3 186 UINT32 Cl11 : 1; ///< Bits 4:4 187 UINT32 Cl12 : 1; ///< Bits 5:5 188 UINT32 Cl13 : 1; ///< Bits 6:6 189 UINT32 Cl14 : 1; ///< Bits 7:7 190 UINT32 Cl15 : 1; ///< Bits 8:8 191 UINT32 Cl16 : 1; ///< Bits 9:9 192 UINT32 Cl17 : 1; ///< Bits 10:10 193 UINT32 Cl18 : 1; ///< Bits 11:11 194 UINT32 Cl19 : 1; ///< Bits 12:12 195 UINT32 Cl20 : 1; ///< Bits 13:13 196 UINT32 Cl21 : 1; ///< Bits 14:14 197 UINT32 Cl22 : 1; ///< Bits 15:15 198 UINT32 Cl23 : 1; ///< Bits 16:16 199 UINT32 Cl24 : 1; ///< Bits 17:17 200 UINT32 Cl25 : 1; ///< Bits 18:18 201 UINT32 Cl26 : 1; ///< Bits 19:19 202 UINT32 Cl27 : 1; ///< Bits 20:20 203 UINT32 Cl28 : 1; ///< Bits 21:21 204 UINT32 Cl29 : 1; ///< Bits 22:22 205 UINT32 Cl30 : 1; ///< Bits 23:23 206 UINT32 Cl31 : 1; ///< Bits 24:24 207 UINT32 Cl32 : 1; ///< Bits 25:25 208 UINT32 Cl33 : 1; ///< Bits 26:26 209 UINT32 Cl34 : 1; ///< Bits 27:27 210 UINT32 Cl35 : 1; ///< Bits 28:28 211 UINT32 Cl36 : 1; ///< Bits 29:29 212 UINT32 Reserved : 1; ///< Bits 30:30 213 UINT32 ClRange : 1; ///< Bits 31:31 214 } Bits; 215 struct { 216 UINT32 Cl23 : 1; ///< Bits 0:0 217 UINT32 Cl24 : 1; ///< Bits 1:1 218 UINT32 Cl25 : 1; ///< Bits 2:2 219 UINT32 Cl26 : 1; ///< Bits 3:3 220 UINT32 Cl27 : 1; ///< Bits 4:4 221 UINT32 Cl28 : 1; ///< Bits 5:5 222 UINT32 Cl29 : 1; ///< Bits 6:6 223 UINT32 Cl30 : 1; ///< Bits 7:7 224 UINT32 Cl31 : 1; ///< Bits 8:8 225 UINT32 Cl32 : 1; ///< Bits 9:9 226 UINT32 Cl33 : 1; ///< Bits 10:10 227 UINT32 Cl34 : 1; ///< Bits 11:11 228 UINT32 Cl35 : 1; ///< Bits 12:12 229 UINT32 Cl36 : 1; ///< Bits 13:13 230 UINT32 Cl37 : 1; ///< Bits 14:14 231 UINT32 Cl38 : 1; ///< Bits 15:15 232 UINT32 Cl39 : 1; ///< Bits 16:16 233 UINT32 Cl40 : 1; ///< Bits 17:17 234 UINT32 Cl41 : 1; ///< Bits 18:18 235 UINT32 Cl42 : 1; ///< Bits 19:19 236 UINT32 Cl43 : 1; ///< Bits 20:20 237 UINT32 Cl44 : 1; ///< Bits 21:21 238 UINT32 Cl45 : 1; ///< Bits 22:22 239 UINT32 Cl46 : 1; ///< Bits 23:23 240 UINT32 Cl47 : 1; ///< Bits 24:24 241 UINT32 Cl48 : 1; ///< Bits 25:25 242 UINT32 Cl49 : 1; ///< Bits 26:26 243 UINT32 Cl50 : 1; ///< Bits 27:27 244 UINT32 Cl51 : 1; ///< Bits 28:28 245 UINT32 Cl52 : 1; ///< Bits 29:29 246 UINT32 Reserved : 1; ///< Bits 30:30 247 UINT32 ClRange : 1; ///< Bits 31:31 248 } HighRangeBits; 249 UINT32 Data; 250 UINT16 Data16[2]; 251 UINT8 Data8[4]; 252 } SPD4_CAS_LATENCIES_SUPPORTED_STRUCT; 253 254 typedef union { 255 struct { 256 UINT8 tAAmin : 8; ///< Bits 7:0 257 } Bits; 258 UINT8 Data; 259 } SPD4_TAA_MIN_MTB_STRUCT; 260 261 typedef union { 262 struct { 263 UINT8 tRCDmin : 8; ///< Bits 7:0 264 } Bits; 265 UINT8 Data; 266 } SPD4_TRCD_MIN_MTB_STRUCT; 267 268 typedef union { 269 struct { 270 UINT8 tRPmin : 8; ///< Bits 7:0 271 } Bits; 272 UINT8 Data; 273 } SPD4_TRP_MIN_MTB_STRUCT; 274 275 typedef union { 276 struct { 277 UINT8 tRASminUpper : 4; ///< Bits 3:0 278 UINT8 tRCminUpper : 4; ///< Bits 7:4 279 } Bits; 280 UINT8 Data; 281 } SPD4_TRAS_TRC_MIN_MTB_STRUCT; 282 283 typedef union { 284 struct { 285 UINT8 tRASmin : 8; ///< Bits 7:0 286 } Bits; 287 UINT8 Data; 288 } SPD4_TRAS_MIN_MTB_STRUCT; 289 290 typedef union { 291 struct { 292 UINT8 tRCmin : 8; ///< Bits 7:0 293 } Bits; 294 UINT8 Data; 295 } SPD4_TRC_MIN_MTB_STRUCT; 296 297 typedef union { 298 struct { 299 UINT16 tRFCmin : 16; ///< Bits 15:0 300 } Bits; 301 UINT16 Data; 302 UINT8 Data8[2]; 303 } SPD4_TRFC_MIN_MTB_STRUCT; 304 305 typedef union { 306 struct { 307 UINT8 tFAWminUpper : 4; ///< Bits 3:0 308 UINT8 Reserved : 4; ///< Bits 7:4 309 } Bits; 310 UINT8 Data; 311 } SPD4_TFAW_MIN_MTB_UPPER_STRUCT; 312 313 typedef union { 314 struct { 315 UINT8 tFAWmin : 8; ///< Bits 7:0 316 } Bits; 317 UINT8 Data; 318 } SPD4_TFAW_MIN_MTB_STRUCT; 319 320 typedef union { 321 struct { 322 UINT8 tRRDmin : 8; ///< Bits 7:0 323 } Bits; 324 UINT8 Data; 325 } SPD4_TRRD_MIN_MTB_STRUCT; 326 327 typedef union { 328 struct { 329 UINT8 tCCDmin : 8; ///< Bits 7:0 330 } Bits; 331 UINT8 Data; 332 } SPD4_TCCD_MIN_MTB_STRUCT; 333 334 typedef union { 335 struct { 336 UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0 337 UINT8 Reserved : 4; ///< Bits 7:4 338 } Bits; 339 UINT8 Data; 340 } SPD4_TWR_UPPER_NIBBLE_STRUCT; 341 342 typedef union { 343 struct { 344 UINT8 tWRmin : 8; ///< Bits 7:0 345 } Bits; 346 UINT8 Data; 347 } SPD4_TWR_MIN_MTB_STRUCT; 348 349 typedef union { 350 struct { 351 UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0 352 UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4 353 } Bits; 354 UINT8 Data; 355 } SPD4_TWTR_UPPER_NIBBLE_STRUCT; 356 357 typedef union { 358 struct { 359 UINT8 tWTRmin : 8; ///< Bits 7:0 360 } Bits; 361 UINT8 Data; 362 } SPD4_TWTR_MIN_MTB_STRUCT; 363 364 typedef union { 365 struct { 366 UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0 367 UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5 368 UINT8 PackageRankMap : 2; ///< Bits 7:6 369 } Bits; 370 UINT8 Data; 371 } SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT; 372 373 typedef union { 374 struct { 375 INT8 tCCDminFine : 8; ///< Bits 7:0 376 } Bits; 377 INT8 Data; 378 } SPD4_TCCD_MIN_FTB_STRUCT; 379 380 typedef union { 381 struct { 382 INT8 tRRDminFine : 8; ///< Bits 7:0 383 } Bits; 384 INT8 Data; 385 } SPD4_TRRD_MIN_FTB_STRUCT; 386 387 typedef union { 388 struct { 389 INT8 tRCminFine : 8; ///< Bits 7:0 390 } Bits; 391 INT8 Data; 392 } SPD4_TRC_MIN_FTB_STRUCT; 393 394 typedef union { 395 struct { 396 INT8 tRPminFine : 8; ///< Bits 7:0 397 } Bits; 398 INT8 Data; 399 } SPD4_TRP_MIN_FTB_STRUCT; 400 401 typedef union { 402 struct { 403 INT8 tRCDminFine : 8; ///< Bits 7:0 404 } Bits; 405 INT8 Data; 406 } SPD4_TRCD_MIN_FTB_STRUCT; 407 408 typedef union { 409 struct { 410 INT8 tAAminFine : 8; ///< Bits 7:0 411 } Bits; 412 INT8 Data; 413 } SPD4_TAA_MIN_FTB_STRUCT; 414 415 typedef union { 416 struct { 417 INT8 tCKmaxFine : 8; ///< Bits 7:0 418 } Bits; 419 INT8 Data; 420 } SPD4_TCK_MAX_FTB_STRUCT; 421 422 typedef union { 423 struct { 424 INT8 tCKminFine : 8; ///< Bits 7:0 425 } Bits; 426 INT8 Data; 427 } SPD4_TCK_MIN_FTB_STRUCT; 428 429 typedef union { 430 struct { 431 UINT8 Height : 5; ///< Bits 4:0 432 UINT8 RawCardExtension : 3; ///< Bits 7:5 433 } Bits; 434 UINT8 Data; 435 } SPD4_UNBUF_MODULE_NOMINAL_HEIGHT; 436 437 typedef union { 438 struct { 439 UINT8 FrontThickness : 4; ///< Bits 3:0 440 UINT8 BackThickness : 4; ///< Bits 7:4 441 } Bits; 442 UINT8 Data; 443 } SPD4_UNBUF_MODULE_NOMINAL_THICKNESS; 444 445 typedef union { 446 struct { 447 UINT8 Card : 5; ///< Bits 4:0 448 UINT8 Revision : 2; ///< Bits 6:5 449 UINT8 Extension : 1; ///< Bits 7:7 450 } Bits; 451 UINT8 Data; 452 } SPD4_UNBUF_REFERENCE_RAW_CARD; 453 454 typedef union { 455 struct { 456 UINT8 MappingRank1 : 1; ///< Bits 0:0 457 UINT8 Reserved : 7; ///< Bits 7:1 458 } Bits; 459 UINT8 Data; 460 } SPD4_UNBUF_ADDRESS_MAPPING; 461 462 typedef union { 463 struct { 464 UINT8 Height : 5; ///< Bits 4:0 465 UINT8 Reserved : 3; ///< Bits 7:5 466 } Bits; 467 UINT8 Data; 468 } SPD4_RDIMM_MODULE_NOMINAL_HEIGHT; 469 470 typedef union { 471 struct { 472 UINT8 FrontThickness : 4; ///< Bits 3:0 473 UINT8 BackThickness : 4; ///< Bits 7:4 474 } Bits; 475 UINT8 Data; 476 } SPD4_RDIMM_MODULE_NOMINAL_THICKNESS; 477 478 typedef union { 479 struct { 480 UINT8 Card : 5; ///< Bits 4:0 481 UINT8 Revision : 2; ///< Bits 6:5 482 UINT8 Extension : 1; ///< Bits 7:7 483 } Bits; 484 UINT8 Data; 485 } SPD4_RDIMM_REFERENCE_RAW_CARD; 486 487 typedef union { 488 struct { 489 UINT8 RegisterCount : 2; ///< Bits 1:0 490 UINT8 DramRowCount : 2; ///< Bits 3:2 491 UINT8 RegisterType : 4; ///< Bits 7:4 492 } Bits; 493 UINT8 Data; 494 } SPD4_RDIMM_MODULE_ATTRIBUTES; 495 496 typedef union { 497 struct { 498 UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 499 UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 500 } Bits; 501 UINT8 Data; 502 } SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION; 503 504 typedef union { 505 struct { 506 UINT16 ContinuationCount : 7; ///< Bits 6:0 507 UINT16 ContinuationParity : 1; ///< Bits 7:7 508 UINT16 LastNonZeroByte : 8; ///< Bits 15:8 509 } Bits; 510 UINT16 Data; 511 UINT8 Data8[2]; 512 } SPD4_MANUFACTURER_ID_CODE; 513 514 typedef union { 515 struct { 516 UINT8 RegisterRevisionNumber; ///< Bits 7:0 517 } Bits; 518 UINT8 Data; 519 } SPD4_RDIMM_REGISTER_REVISION_NUMBER; 520 521 typedef union { 522 struct { 523 UINT8 Rank1Mapping : 1; ///< Bits 0:0 524 UINT8 Reserved : 7; ///< Bits 7:1 525 } Bits; 526 UINT8 Data; 527 } SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM; 528 529 typedef union { 530 struct { 531 UINT8 Cke : 2; ///< Bits 1:0 532 UINT8 Odt : 2; ///< Bits 3:2 533 UINT8 CommandAddress : 2; ///< Bits 5:4 534 UINT8 ChipSelect : 2; ///< Bits 7:6 535 } Bits; 536 UINT8 Data; 537 } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS; 538 539 typedef union { 540 struct { 541 UINT8 Y0Y2 : 2; ///< Bits 1:0 542 UINT8 Y1Y3 : 2; ///< Bits 3:2 543 UINT8 Reserved0 : 2; ///< Bits 5:4 544 UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6 545 UINT8 Reserved1 : 1; ///< Bits 7:7 546 } Bits; 547 UINT8 Data; 548 } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK; 549 550 typedef union { 551 struct { 552 UINT8 Height : 5; ///< Bits 4:0 553 UINT8 Reserved : 3; ///< Bits 7:5 554 } Bits; 555 UINT8 Data; 556 } SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT; 557 558 typedef union { 559 struct { 560 UINT8 FrontThickness : 4; ///< Bits 3:0 561 UINT8 BackThickness : 4; ///< Bits 7:4 562 } Bits; 563 UINT8 Data; 564 } SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS; 565 566 typedef union { 567 struct { 568 UINT8 Card : 5; ///< Bits 4:0 569 UINT8 Revision : 2; ///< Bits 6:5 570 UINT8 Extension : 1; ///< Bits 7:7 571 } Bits; 572 UINT8 Data; 573 } SPD4_LRDIMM_REFERENCE_RAW_CARD; 574 575 typedef union { 576 struct { 577 UINT8 RegisterCount : 2; ///< Bits 1:0 578 UINT8 DramRowCount : 2; ///< Bits 3:2 579 UINT8 RegisterType : 4; ///< Bits 7:4 580 } Bits; 581 UINT8 Data; 582 } SPD4_LRDIMM_MODULE_ATTRIBUTES; 583 584 typedef union { 585 struct { 586 UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 587 UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 588 } Bits; 589 UINT8 Data; 590 } SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION; 591 592 typedef union { 593 struct { 594 UINT8 RegisterRevisionNumber; ///< Bits 7:0 595 } Bits; 596 UINT8 Data; 597 } SPD4_LRDIMM_REGISTER_REVISION_NUMBER; 598 599 typedef union { 600 struct { 601 UINT8 Rank1Mapping : 1; ///< Bits 0:0 602 UINT8 Reserved : 7; ///< Bits 7:1 603 } Bits; 604 UINT8 Data; 605 } SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM; 606 607 typedef union { 608 struct { 609 UINT8 Cke : 2; ///< Bits 1:0 610 UINT8 Odt : 2; ///< Bits 3:2 611 UINT8 CommandAddress : 2; ///< Bits 5:4 612 UINT8 ChipSelect : 2; ///< Bits 7:6 613 } Bits; 614 UINT8 Data; 615 } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS; 616 617 typedef union { 618 struct { 619 UINT8 Y0Y2 : 2; ///< Bits 1:0 620 UINT8 Y1Y3 : 2; ///< Bits 3:2 621 UINT8 Reserved0 : 2; ///< Bits 5:4 622 UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6 623 UINT8 Reserved1 : 1; ///< Bits 7:7 624 } Bits; 625 UINT8 Data; 626 } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK; 627 628 typedef struct { 629 UINT8 DataBufferRevisionNumber; 630 } SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER; 631 632 typedef union { 633 struct { 634 UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0 635 UINT8 Reserved : 2; ///< Bits 7:6 636 } Bits; 637 UINT8 Data; 638 } SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK; 639 640 typedef struct { 641 UINT8 DataBufferVrefDQforDramInterface; 642 } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE; 643 644 typedef union { 645 struct { 646 UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0 647 UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4 648 } Bits; 649 UINT8 Data; 650 } SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE; 651 652 typedef union { 653 struct { 654 UINT8 DataRateLe1866 : 2; ///< Bits 1:0 655 UINT8 DataRateLe2400 : 2; ///< Bits 3:2 656 UINT8 DataRateLe3200 : 2; ///< Bits 5:4 657 UINT8 Reserved : 2; ///< Bits 7:6 658 } Bits; 659 UINT8 Data; 660 } SPD4_LRDIMM_DRAM_DRIVE_STRENGTH; 661 662 typedef union { 663 struct { 664 UINT8 Rtt_Nom : 3; ///< Bits 2:0 665 UINT8 Rtt_WR : 3; ///< Bits 5:3 666 UINT8 Reserved : 2; ///< Bits 7:6 667 } Bits; 668 UINT8 Data; 669 } SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE; 670 671 typedef union { 672 struct { 673 UINT8 PackageRanks0_1 : 3; ///< Bits 2:0 674 UINT8 PackageRanks2_3 : 3; ///< Bits 5:3 675 UINT8 Reserved : 2; ///< Bits 7:6 676 } Bits; 677 UINT8 Data; 678 } SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE; 679 680 typedef union { 681 struct { 682 UINT8 Rank0 : 1; ///< Bits 0:0 683 UINT8 Rank1 : 1; ///< Bits 1:1 684 UINT8 Rank2 : 1; ///< Bits 2:2 685 UINT8 Rank3 : 1; ///< Bits 3:3 686 UINT8 DataBuffer : 1; ///< Bits 4:4 687 UINT8 Reserved : 3; ///< Bits 7:5 688 } Bits; 689 UINT8 Data; 690 } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE; 691 692 typedef union { 693 struct { 694 UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0 695 UINT8 DataBufferDfe : 1; ///< Bits 1:1 696 UINT8 Reserved : 6; ///< Bits 7:2 697 } Bits; 698 UINT8 Data; 699 } SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION; 700 701 typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER; 702 703 typedef union { 704 struct { 705 UINT16 ContinuationCount : 7; ///< Bits 6:0 706 UINT16 ContinuationParity : 1; ///< Bits 7:7 707 UINT16 LastNonZeroByte : 8; ///< Bits 15:8 708 } Bits; 709 UINT16 Data; 710 UINT8 Data8[2]; 711 } SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE; 712 713 typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER; 714 715 typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE; 716 717 typedef union { 718 struct { 719 UINT8 Card : 5; ///< Bits 4:0 720 UINT8 Revision : 2; ///< Bits 6:5 721 UINT8 Extension : 1; ///< Bits 7:7 722 } Bits; 723 UINT8 Data; 724 } SPD4_NVDIMM_REFERENCE_RAW_CARD; 725 726 typedef union { 727 struct { 728 UINT8 Reserved : 4; ///< Bits 3:0 729 UINT8 Extension : 4; ///< Bits 7:4 730 } Bits; 731 UINT8 Data; 732 } SPD4_NVDIMM_MODULE_CHARACTERISTICS; 733 734 typedef struct { 735 UINT8 Reserved; 736 UINT8 MediaType; 737 } SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES; 738 739 typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME; 740 741 typedef union { 742 struct { 743 UINT16 FunctionInterface : 5; ///< Bits 4:0 744 UINT16 FunctionClass : 5; ///< Bits 9:5 745 UINT16 BlockOffset : 4; ///< Bits 13:10 746 UINT16 Reserved : 1; ///< Bits 14:14 747 UINT16 Implemented : 1; ///< Bits 15:15 748 } Bits; 749 UINT16 Data; 750 UINT8 Data8[2]; 751 } SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR; 752 753 typedef struct { 754 UINT8 Year; ///< Year represented in BCD (00h = 2000) 755 UINT8 Week; ///< Year represented in BCD (47h = week 47) 756 } SPD4_MANUFACTURING_DATE; 757 758 typedef union { 759 UINT32 Data; 760 UINT16 SerialNumber16[2]; 761 UINT8 SerialNumber8[4]; 762 } SPD4_MANUFACTURER_SERIAL_NUMBER; 763 764 typedef struct { 765 UINT8 Location; ///< Module Manufacturing Location 766 } SPD4_MANUFACTURING_LOCATION; 767 768 typedef struct { 769 SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code 770 SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location 771 SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) 772 SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number 773 } SPD4_UNIQUE_MODULE_ID; 774 775 typedef union { 776 UINT16 Crc[1]; 777 UINT8 Data8[2]; 778 } SPD4_CYCLIC_REDUNDANCY_CODE; 779 780 typedef struct { 781 SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 782 SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision 783 SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type 784 SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type 785 SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks 786 SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing 787 SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type 788 SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features 789 SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options 790 SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features 791 SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type 792 SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD 793 SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization 794 SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width 795 SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor 796 SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type 797 UINT8 Reserved0; ///< 16 Reserved 798 SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases 799 SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) 800 SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) 801 SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported 802 SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) 803 SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin) 804 SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin) 805 SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC 806 SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 807 SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 808 SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min) 809 SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min) 810 SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min) 811 SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW 812 SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin) 813 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group 814 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group 815 SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group 816 SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin 817 SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin) 818 SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin 819 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group 820 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group 821 UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved 822 SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping 823 UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved 824 SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group 825 SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group 826 SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group 827 SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 828 SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin) 829 SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 830 SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) 831 SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax) 832 SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin) 833 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) 834 } SPD4_BASE_SECTION; 835 836 typedef struct { 837 SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 838 SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 839 SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 840 SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM 841 UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved 842 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 843 } SPD4_MODULE_UNBUFFERED; 844 845 typedef struct { 846 SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 847 SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 848 SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 849 SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes 850 SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution 851 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code 852 SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number 853 SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM 854 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address 855 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock 856 UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved 857 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 858 } SPD4_MODULE_REGISTERED; 859 860 typedef struct { 861 SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 862 SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 863 SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 864 SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes 865 SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution 866 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code 867 SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number 868 SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM 869 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address 870 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock 871 SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number 872 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0 873 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1 874 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2 875 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3 876 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface 877 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866 878 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400 879 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200 880 SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength 881 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866 882 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400 883 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200 884 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866 885 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400 886 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200 887 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range 888 SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization 889 UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved 890 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 891 } SPD4_MODULE_LOADREDUCED; 892 893 typedef struct { 894 UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved 895 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier 896 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code 897 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier 898 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code 899 SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used 900 SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics 901 SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types 902 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time 903 SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors 904 UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved 905 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 906 } SPD4_MODULE_NVDIMM; 907 908 typedef union { 909 SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types 910 SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types 911 SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types 912 SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters 913 } SPD4_MODULE_SPECIFIC; 914 915 typedef struct { 916 UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number 917 } SPD4_MODULE_PART_NUMBER; 918 919 typedef struct { 920 UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data 921 } SPD4_MANUFACTURER_SPECIFIC; 922 923 typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code 924 typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping 925 926 typedef struct { 927 SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID 928 SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number 929 SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code 930 SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code 931 SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping 932 SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data 933 UINT8 Reserved[2]; ///< 382-383 Reserved 934 } SPD4_MANUFACTURING_DATA; 935 936 typedef struct { 937 UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types 938 } SPD4_END_USER_SECTION; 939 940 /// 941 /// DDR4 Serial Presence Detect structure 942 /// 943 typedef struct { 944 SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters 945 SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section 946 UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved 947 SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information 948 SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable 949 } SPD_DDR4; 950 951 #pragma pack (pop) 952 #endif 953