1 /** @file
2   MSR Definitions.
3 
4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5   are provided for MSRs that contain one or more bit fields.  If the MSR value
6   returned is a single 32-bit or 64-bit value, then a data structure is not
7   provided for that MSR.
8 
9   Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
10   SPDX-License-Identifier: BSD-2-Clause-Patent
11 
12   @par Specification Reference:
13   AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
14 
15 **/
16 
17 #ifndef __FAM17_MSR_H__
18 #define __FAM17_MSR_H__
19 
20 /**
21   Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register
22 
23 **/
24 #define MSR_SEV_ES_GHCB                    0xc0010130
25 
26 /**
27   MSR information returned for #MSR_SEV_ES_GHCB
28 **/
29 typedef union {
30   struct {
31     UINT32  Function:12;
32     UINT32  Reserved1:20;
33     UINT32  Reserved2:32;
34   } GhcbInfo;
35 
36   struct {
37     UINT8   Reserved[3];
38     UINT8   SevEncryptionBitPos;
39     UINT16  SevEsProtocolMin;
40     UINT16  SevEsProtocolMax;
41   } GhcbProtocol;
42 
43   struct {
44     UINT32  Function:12;
45     UINT32  ReasonCodeSet:4;
46     UINT32  ReasonCode:8;
47     UINT32  Reserved1:8;
48     UINT32  Reserved2:32;
49   } GhcbTerminate;
50 
51   VOID    *Ghcb;
52 
53   UINT64  GhcbPhysicalAddress;
54 } MSR_SEV_ES_GHCB_REGISTER;
55 
56 #define GHCB_INFO_SEV_INFO                 1
57 #define GHCB_INFO_SEV_INFO_GET             2
58 #define GHCB_INFO_CPUID_REQUEST            4
59 #define GHCB_INFO_CPUID_RESPONSE           5
60 #define GHCB_INFO_TERMINATE_REQUEST        256
61 
62 #define GHCB_TERMINATE_GHCB                0
63 #define GHCB_TERMINATE_GHCB_GENERAL        0
64 #define GHCB_TERMINATE_GHCB_PROTOCOL       1
65 
66 /**
67   Secure Encrypted Virtualization (SEV) status register
68 
69 **/
70 #define MSR_SEV_STATUS                     0xc0010131
71 
72 /**
73   MSR information returned for #MSR_SEV_STATUS
74 **/
75 typedef union {
76   ///
77   /// Individual bit fields
78   ///
79   struct {
80     ///
81     /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
82     ///
83     UINT32  SevBit:1;
84 
85     ///
86     /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
87     ///
88     UINT32  SevEsBit:1;
89 
90     UINT32  Reserved:30;
91   } Bits;
92   ///
93   /// All bit fields as a 32-bit value
94   ///
95   UINT32  Uint32;
96   ///
97   /// All bit fields as a 64-bit value
98   ///
99   UINT64  Uint64;
100 } MSR_SEV_STATUS_REGISTER;
101 
102 #endif
103