1 /** @file 2 MSR Definitions for Intel processors based on the Haswell microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> 10 SPDX-License-Identifier: BSD-2-Clause-Patent 11 12 @par Specification Reference: 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 14 May 2018, Volume 4: Model-Specific-Registers (MSR) 15 16 **/ 17 18 #ifndef __HASWELL_MSR_H__ 19 #define __HASWELL_MSR_H__ 20 21 #include <Register/Intel/ArchitecturalMsr.h> 22 23 /** 24 Is Intel processors based on the Haswell microarchitecture? 25 26 @param DisplayFamily Display Family ID 27 @param DisplayModel Display Model ID 28 29 @retval TRUE Yes, it is. 30 @retval FALSE No, it isn't. 31 **/ 32 #define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \ 33 (DisplayFamily == 0x06 && \ 34 ( \ 35 DisplayModel == 0x3C || \ 36 DisplayModel == 0x45 || \ 37 DisplayModel == 0x46 \ 38 ) \ 39 ) 40 41 /** 42 Package. 43 44 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE) 45 @param EAX Lower 32-bits of MSR value. 46 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 47 @param EDX Upper 32-bits of MSR value. 48 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 49 50 <b>Example usage</b> 51 @code 52 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr; 53 54 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO); 55 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64); 56 @endcode 57 @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 58 **/ 59 #define MSR_HASWELL_PLATFORM_INFO 0x000000CE 60 61 /** 62 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO 63 **/ 64 typedef union { 65 /// 66 /// Individual bit fields 67 /// 68 struct { 69 UINT32 Reserved1:8; 70 /// 71 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 72 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 73 /// MHz. 74 /// 75 UINT32 MaximumNonTurboRatio:8; 76 UINT32 Reserved2:12; 77 /// 78 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 79 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 80 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 81 /// Turbo mode is disabled. 82 /// 83 UINT32 RatioLimit:1; 84 /// 85 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 86 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 87 /// and when set to 0, indicates TDP Limit for Turbo mode is not 88 /// programmable. 89 /// 90 UINT32 TDPLimit:1; 91 UINT32 Reserved3:2; 92 /// 93 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, 94 /// indicates that LPM is supported, and when set to 0, indicates LPM is 95 /// not supported. 96 /// 97 UINT32 LowPowerModeSupport:1; 98 /// 99 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base 100 /// TDP level available. 01: One additional TDP level available. 02: Two 101 /// additional TDP level available. 11: Reserved. 102 /// 103 UINT32 ConfigTDPLevels:2; 104 UINT32 Reserved4:5; 105 /// 106 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 107 /// minimum ratio (maximum efficiency) that the processor can operates, in 108 /// units of 100MHz. 109 /// 110 UINT32 MaximumEfficiencyRatio:8; 111 /// 112 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the 113 /// minimum supported operating ratio in units of 100 MHz. 114 /// 115 UINT32 MinimumOperatingRatio:8; 116 UINT32 Reserved5:8; 117 } Bits; 118 /// 119 /// All bit fields as a 64-bit value 120 /// 121 UINT64 Uint64; 122 } MSR_HASWELL_PLATFORM_INFO_REGISTER; 123 124 125 /** 126 Thread. Performance Event Select for Counter n (R/W) Supports all fields 127 described inTable 2-2 and the fields below. 128 129 @param ECX MSR_HASWELL_IA32_PERFEVTSELn 130 @param EAX Lower 32-bits of MSR value. 131 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 132 @param EDX Upper 32-bits of MSR value. 133 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 134 135 <b>Example usage</b> 136 @code 137 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr; 138 139 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0); 140 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64); 141 @endcode 142 @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. 143 MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. 144 MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. 145 @{ 146 **/ 147 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186 148 #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187 149 #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189 150 /// @} 151 152 /** 153 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0, 154 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3. 155 **/ 156 typedef union { 157 /// 158 /// Individual bit fields 159 /// 160 struct { 161 /// 162 /// [Bits 7:0] Event Select: Selects a performance event logic unit. 163 /// 164 UINT32 EventSelect:8; 165 /// 166 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to 167 /// detect on the selected event logic. 168 /// 169 UINT32 UMASK:8; 170 /// 171 /// [Bit 16] USR: Counts while in privilege level is not ring 0. 172 /// 173 UINT32 USR:1; 174 /// 175 /// [Bit 17] OS: Counts while in privilege level is ring 0. 176 /// 177 UINT32 OS:1; 178 /// 179 /// [Bit 18] Edge: Enables edge detection if set. 180 /// 181 UINT32 E:1; 182 /// 183 /// [Bit 19] PC: enables pin control. 184 /// 185 UINT32 PC:1; 186 /// 187 /// [Bit 20] INT: enables interrupt on counter overflow. 188 /// 189 UINT32 INT:1; 190 /// 191 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated 192 /// event conditions occurring across all logical processors sharing a 193 /// processor core. When set to 0, the counter only increments the 194 /// associated event conditions occurring in the logical processor which 195 /// programmed the MSR. 196 /// 197 UINT32 ANY:1; 198 /// 199 /// [Bit 22] EN: enables the corresponding performance counter to commence 200 /// counting when this bit is set. 201 /// 202 UINT32 EN:1; 203 /// 204 /// [Bit 23] INV: invert the CMASK. 205 /// 206 UINT32 INV:1; 207 /// 208 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding 209 /// performance counter increments each cycle if the event count is 210 /// greater than or equal to the CMASK. 211 /// 212 UINT32 CMASK:8; 213 UINT32 Reserved:32; 214 /// 215 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set, 216 /// AnyThread (bit 21) should be cleared to prevent incorrect results. 217 /// 218 UINT32 IN_TX:1; 219 UINT32 Reserved2:31; 220 } Bits; 221 /// 222 /// All bit fields as a 64-bit value 223 /// 224 UINT64 Uint64; 225 } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER; 226 227 228 /** 229 Thread. Performance Event Select for Counter 2 (R/W) Supports all fields 230 described inTable 2-2 and the fields below. 231 232 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188) 233 @param EAX Lower 32-bits of MSR value. 234 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 235 @param EDX Upper 32-bits of MSR value. 236 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 237 238 <b>Example usage</b> 239 @code 240 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr; 241 242 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2); 243 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64); 244 @endcode 245 @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. 246 **/ 247 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188 248 249 /** 250 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2 251 **/ 252 typedef union { 253 /// 254 /// Individual bit fields 255 /// 256 struct { 257 /// 258 /// [Bits 7:0] Event Select: Selects a performance event logic unit. 259 /// 260 UINT32 EventSelect:8; 261 /// 262 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to 263 /// detect on the selected event logic. 264 /// 265 UINT32 UMASK:8; 266 /// 267 /// [Bit 16] USR: Counts while in privilege level is not ring 0. 268 /// 269 UINT32 USR:1; 270 /// 271 /// [Bit 17] OS: Counts while in privilege level is ring 0. 272 /// 273 UINT32 OS:1; 274 /// 275 /// [Bit 18] Edge: Enables edge detection if set. 276 /// 277 UINT32 E:1; 278 /// 279 /// [Bit 19] PC: enables pin control. 280 /// 281 UINT32 PC:1; 282 /// 283 /// [Bit 20] INT: enables interrupt on counter overflow. 284 /// 285 UINT32 INT:1; 286 /// 287 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated 288 /// event conditions occurring across all logical processors sharing a 289 /// processor core. When set to 0, the counter only increments the 290 /// associated event conditions occurring in the logical processor which 291 /// programmed the MSR. 292 /// 293 UINT32 ANY:1; 294 /// 295 /// [Bit 22] EN: enables the corresponding performance counter to commence 296 /// counting when this bit is set. 297 /// 298 UINT32 EN:1; 299 /// 300 /// [Bit 23] INV: invert the CMASK. 301 /// 302 UINT32 INV:1; 303 /// 304 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding 305 /// performance counter increments each cycle if the event count is 306 /// greater than or equal to the CMASK. 307 /// 308 UINT32 CMASK:8; 309 UINT32 Reserved:32; 310 /// 311 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set, 312 /// AnyThread (bit 21) should be cleared to prevent incorrect results. 313 /// 314 UINT32 IN_TX:1; 315 /// 316 /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and 317 /// in sampling, spurious PMI may occur and transactions may continuously 318 /// abort near overflow conditions. Software should favor using IN_TXCP 319 /// for counting over sampling. If sampling, software should use large 320 /// "sample-after" value after clearing the counter configured to use 321 /// IN_TXCP and also always reset the counter even when no overflow 322 /// condition was reported. 323 /// 324 UINT32 IN_TXCP:1; 325 UINT32 Reserved2:30; 326 } Bits; 327 /// 328 /// All bit fields as a 64-bit value 329 /// 330 UINT64 Uint64; 331 } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER; 332 333 334 /** 335 Thread. Last Branch Record Filtering Select Register (R/W). 336 337 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8) 338 @param EAX Lower 32-bits of MSR value. 339 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 340 @param EDX Upper 32-bits of MSR value. 341 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 342 343 <b>Example usage</b> 344 @code 345 MSR_HASWELL_LBR_SELECT_REGISTER Msr; 346 347 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT); 348 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64); 349 @endcode 350 @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. 351 **/ 352 #define MSR_HASWELL_LBR_SELECT 0x000001C8 353 354 /** 355 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT 356 **/ 357 typedef union { 358 /// 359 /// Individual bit fields 360 /// 361 struct { 362 /// 363 /// [Bit 0] CPL_EQ_0. 364 /// 365 UINT32 CPL_EQ_0:1; 366 /// 367 /// [Bit 1] CPL_NEQ_0. 368 /// 369 UINT32 CPL_NEQ_0:1; 370 /// 371 /// [Bit 2] JCC. 372 /// 373 UINT32 JCC:1; 374 /// 375 /// [Bit 3] NEAR_REL_CALL. 376 /// 377 UINT32 NEAR_REL_CALL:1; 378 /// 379 /// [Bit 4] NEAR_IND_CALL. 380 /// 381 UINT32 NEAR_IND_CALL:1; 382 /// 383 /// [Bit 5] NEAR_RET. 384 /// 385 UINT32 NEAR_RET:1; 386 /// 387 /// [Bit 6] NEAR_IND_JMP. 388 /// 389 UINT32 NEAR_IND_JMP:1; 390 /// 391 /// [Bit 7] NEAR_REL_JMP. 392 /// 393 UINT32 NEAR_REL_JMP:1; 394 /// 395 /// [Bit 8] FAR_BRANCH. 396 /// 397 UINT32 FAR_BRANCH:1; 398 /// 399 /// [Bit 9] EN_CALL_STACK. 400 /// 401 UINT32 EN_CALL_STACK:1; 402 UINT32 Reserved1:22; 403 UINT32 Reserved2:32; 404 } Bits; 405 /// 406 /// All bit fields as a 32-bit value 407 /// 408 UINT32 Uint32; 409 /// 410 /// All bit fields as a 64-bit value 411 /// 412 UINT64 Uint64; 413 } MSR_HASWELL_LBR_SELECT_REGISTER; 414 415 416 /** 417 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines 418 the interrupt response time limit used by the processor to manage transition 419 to package C6 or C7 state. The latency programmed in this register is for 420 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state. 421 Note: C-state values are processor specific C-state code names, unrelated to 422 MWAIT extension C-state parameters or ACPI C-States. 423 424 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B) 425 @param EAX Lower 32-bits of MSR value. 426 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER. 427 @param EDX Upper 32-bits of MSR value. 428 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER. 429 430 <b>Example usage</b> 431 @code 432 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr; 433 434 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1); 435 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64); 436 @endcode 437 @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM. 438 **/ 439 #define MSR_HASWELL_PKGC_IRTL1 0x0000060B 440 441 /** 442 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1 443 **/ 444 typedef union { 445 /// 446 /// Individual bit fields 447 /// 448 struct { 449 /// 450 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 451 /// that should be used to decide if the package should be put into a 452 /// package C6 or C7 state. 453 /// 454 UINT32 InterruptResponseTimeLimit:10; 455 /// 456 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit 457 /// of the interrupt response time limit. See Table 2-19 for supported 458 /// time unit encodings. 459 /// 460 UINT32 TimeUnit:3; 461 UINT32 Reserved1:2; 462 /// 463 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 464 /// valid and can be used by the processor for package C-sate management. 465 /// 466 UINT32 Valid:1; 467 UINT32 Reserved2:16; 468 UINT32 Reserved3:32; 469 } Bits; 470 /// 471 /// All bit fields as a 32-bit value 472 /// 473 UINT32 Uint32; 474 /// 475 /// All bit fields as a 64-bit value 476 /// 477 UINT64 Uint64; 478 } MSR_HASWELL_PKGC_IRTL1_REGISTER; 479 480 481 /** 482 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines 483 the interrupt response time limit used by the processor to manage transition 484 to package C6 or C7 state. The latency programmed in this register is for 485 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state. 486 Note: C-state values are processor specific C-state code names, unrelated to 487 MWAIT extension C-state parameters or ACPI C-States. 488 489 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C) 490 @param EAX Lower 32-bits of MSR value. 491 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER. 492 @param EDX Upper 32-bits of MSR value. 493 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER. 494 495 <b>Example usage</b> 496 @code 497 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr; 498 499 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2); 500 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64); 501 @endcode 502 @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM. 503 **/ 504 #define MSR_HASWELL_PKGC_IRTL2 0x0000060C 505 506 /** 507 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2 508 **/ 509 typedef union { 510 /// 511 /// Individual bit fields 512 /// 513 struct { 514 /// 515 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 516 /// that should be used to decide if the package should be put into a 517 /// package C6 or C7 state. 518 /// 519 UINT32 InterruptResponseTimeLimit:10; 520 /// 521 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit 522 /// of the interrupt response time limit. See Table 2-19 for supported 523 /// time unit encodings. 524 /// 525 UINT32 TimeUnit:3; 526 UINT32 Reserved1:2; 527 /// 528 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 529 /// valid and can be used by the processor for package C-sate management. 530 /// 531 UINT32 Valid:1; 532 UINT32 Reserved2:16; 533 UINT32 Reserved3:32; 534 } Bits; 535 /// 536 /// All bit fields as a 32-bit value 537 /// 538 UINT32 Uint32; 539 /// 540 /// All bit fields as a 64-bit value 541 /// 542 UINT64 Uint64; 543 } MSR_HASWELL_PKGC_IRTL2_REGISTER; 544 545 546 /** 547 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 548 549 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613) 550 @param EAX Lower 32-bits of MSR value. 551 @param EDX Upper 32-bits of MSR value. 552 553 <b>Example usage</b> 554 @code 555 UINT64 Msr; 556 557 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS); 558 @endcode 559 @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 560 **/ 561 #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613 562 563 564 /** 565 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 566 567 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619) 568 @param EAX Lower 32-bits of MSR value. 569 @param EDX Upper 32-bits of MSR value. 570 571 <b>Example usage</b> 572 @code 573 UINT64 Msr; 574 575 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS); 576 @endcode 577 @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 578 **/ 579 #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619 580 581 582 /** 583 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 584 RAPL Domain.". 585 586 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B) 587 @param EAX Lower 32-bits of MSR value. 588 @param EDX Upper 32-bits of MSR value. 589 590 <b>Example usage</b> 591 @code 592 UINT64 Msr; 593 594 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS); 595 @endcode 596 @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 597 **/ 598 #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B 599 600 601 /** 602 Package. Base TDP Ratio (R/O). 603 604 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648) 605 @param EAX Lower 32-bits of MSR value. 606 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER. 607 @param EDX Upper 32-bits of MSR value. 608 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER. 609 610 <b>Example usage</b> 611 @code 612 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr; 613 614 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL); 615 @endcode 616 @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. 617 **/ 618 #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648 619 620 /** 621 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL 622 **/ 623 typedef union { 624 /// 625 /// Individual bit fields 626 /// 627 struct { 628 /// 629 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this 630 /// specific processor (in units of 100 MHz). 631 /// 632 UINT32 Config_TDP_Base:8; 633 UINT32 Reserved1:24; 634 UINT32 Reserved2:32; 635 } Bits; 636 /// 637 /// All bit fields as a 32-bit value 638 /// 639 UINT32 Uint32; 640 /// 641 /// All bit fields as a 64-bit value 642 /// 643 UINT64 Uint64; 644 } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER; 645 646 647 /** 648 Package. ConfigTDP Level 1 ratio and power level (R/O). 649 650 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649) 651 @param EAX Lower 32-bits of MSR value. 652 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER. 653 @param EDX Upper 32-bits of MSR value. 654 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER. 655 656 <b>Example usage</b> 657 @code 658 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr; 659 660 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1); 661 @endcode 662 @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. 663 **/ 664 #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649 665 666 /** 667 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1 668 **/ 669 typedef union { 670 /// 671 /// Individual bit fields 672 /// 673 struct { 674 /// 675 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1. 676 /// 677 UINT32 PKG_TDP_LVL1:15; 678 UINT32 Reserved1:1; 679 /// 680 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used 681 /// for this specific processor. 682 /// 683 UINT32 Config_TDP_LVL1_Ratio:8; 684 UINT32 Reserved2:8; 685 /// 686 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP 687 /// Level 1. 688 /// 689 UINT32 PKG_MAX_PWR_LVL1:15; 690 /// 691 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP 692 /// Level 1. 693 /// 694 UINT32 PKG_MIN_PWR_LVL1:16; 695 UINT32 Reserved3:1; 696 } Bits; 697 /// 698 /// All bit fields as a 64-bit value 699 /// 700 UINT64 Uint64; 701 } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER; 702 703 704 /** 705 Package. ConfigTDP Level 2 ratio and power level (R/O). 706 707 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A) 708 @param EAX Lower 32-bits of MSR value. 709 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER. 710 @param EDX Upper 32-bits of MSR value. 711 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER. 712 713 <b>Example usage</b> 714 @code 715 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr; 716 717 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2); 718 @endcode 719 @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. 720 **/ 721 #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A 722 723 /** 724 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2 725 **/ 726 typedef union { 727 /// 728 /// Individual bit fields 729 /// 730 struct { 731 /// 732 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2. 733 /// 734 UINT32 PKG_TDP_LVL2:15; 735 UINT32 Reserved1:1; 736 /// 737 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used 738 /// for this specific processor. 739 /// 740 UINT32 Config_TDP_LVL2_Ratio:8; 741 UINT32 Reserved2:8; 742 /// 743 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP 744 /// Level 2. 745 /// 746 UINT32 PKG_MAX_PWR_LVL2:15; 747 /// 748 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP 749 /// Level 2. 750 /// 751 UINT32 PKG_MIN_PWR_LVL2:16; 752 UINT32 Reserved3:1; 753 } Bits; 754 /// 755 /// All bit fields as a 64-bit value 756 /// 757 UINT64 Uint64; 758 } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER; 759 760 761 /** 762 Package. ConfigTDP Control (R/W). 763 764 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B) 765 @param EAX Lower 32-bits of MSR value. 766 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER. 767 @param EDX Upper 32-bits of MSR value. 768 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER. 769 770 <b>Example usage</b> 771 @code 772 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr; 773 774 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL); 775 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64); 776 @endcode 777 @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. 778 **/ 779 #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B 780 781 /** 782 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL 783 **/ 784 typedef union { 785 /// 786 /// Individual bit fields 787 /// 788 struct { 789 /// 790 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field. 791 /// 792 UINT32 TDP_LEVEL:2; 793 UINT32 Reserved1:29; 794 /// 795 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of 796 /// this register is locked until a reset. 797 /// 798 UINT32 Config_TDP_Lock:1; 799 UINT32 Reserved2:32; 800 } Bits; 801 /// 802 /// All bit fields as a 32-bit value 803 /// 804 UINT32 Uint32; 805 /// 806 /// All bit fields as a 64-bit value 807 /// 808 UINT64 Uint64; 809 } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER; 810 811 812 /** 813 Package. ConfigTDP Control (R/W). 814 815 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C) 816 @param EAX Lower 32-bits of MSR value. 817 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER. 818 @param EDX Upper 32-bits of MSR value. 819 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER. 820 821 <b>Example usage</b> 822 @code 823 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr; 824 825 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO); 826 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64); 827 @endcode 828 @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. 829 **/ 830 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C 831 832 /** 833 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO 834 **/ 835 typedef union { 836 /// 837 /// Individual bit fields 838 /// 839 struct { 840 /// 841 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this 842 /// field. 843 /// 844 UINT32 MAX_NON_TURBO_RATIO:8; 845 UINT32 Reserved1:23; 846 /// 847 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the 848 /// content of this register is locked until a reset. 849 /// 850 UINT32 TURBO_ACTIVATION_RATIO_Lock:1; 851 UINT32 Reserved2:32; 852 } Bits; 853 /// 854 /// All bit fields as a 32-bit value 855 /// 856 UINT32 Uint32; 857 /// 858 /// All bit fields as a 64-bit value 859 /// 860 UINT64 Uint64; 861 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER; 862 863 864 /** 865 Core. C-State Configuration Control (R/W) Note: C-state values are processor 866 specific C-state code names, unrelated to MWAIT extension C-state parameters 867 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__. 868 869 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2) 870 @param EAX Lower 32-bits of MSR value. 871 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER. 872 @param EDX Upper 32-bits of MSR value. 873 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER. 874 875 <b>Example usage</b> 876 @code 877 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 878 879 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL); 880 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 881 @endcode 882 @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 883 **/ 884 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2 885 886 /** 887 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL 888 **/ 889 typedef union { 890 /// 891 /// Individual bit fields 892 /// 893 struct { 894 /// 895 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest 896 /// processor-specific C-state code name (consuming the least power) for 897 /// the package. The default is set as factory-configured package C-state 898 /// limit. The following C-state code name encodings are supported: 0000b: 899 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 900 /// 0100b: C7 0101b: C7s Package C states C7 are not available to 901 /// processor with signature 06_3CH. 902 /// 903 UINT32 Limit:4; 904 UINT32 Reserved1:6; 905 /// 906 /// [Bit 10] I/O MWAIT Redirection Enable (R/W). 907 /// 908 UINT32 IO_MWAIT:1; 909 UINT32 Reserved2:4; 910 /// 911 /// [Bit 15] CFG Lock (R/WO). 912 /// 913 UINT32 CFGLock:1; 914 UINT32 Reserved3:9; 915 /// 916 /// [Bit 25] C3 State Auto Demotion Enable (R/W). 917 /// 918 UINT32 C3AutoDemotion:1; 919 /// 920 /// [Bit 26] C1 State Auto Demotion Enable (R/W). 921 /// 922 UINT32 C1AutoDemotion:1; 923 /// 924 /// [Bit 27] Enable C3 Undemotion (R/W). 925 /// 926 UINT32 C3Undemotion:1; 927 /// 928 /// [Bit 28] Enable C1 Undemotion (R/W). 929 /// 930 UINT32 C1Undemotion:1; 931 UINT32 Reserved4:3; 932 UINT32 Reserved5:32; 933 } Bits; 934 /// 935 /// All bit fields as a 32-bit value 936 /// 937 UINT32 Uint32; 938 /// 939 /// All bit fields as a 64-bit value 940 /// 941 UINT64 Uint64; 942 } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER; 943 944 945 /** 946 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability 947 Enhancement. Accessible only while in SMM. 948 949 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D) 950 @param EAX Lower 32-bits of MSR value. 951 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER. 952 @param EDX Upper 32-bits of MSR value. 953 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER. 954 955 <b>Example usage</b> 956 @code 957 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr; 958 959 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP); 960 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64); 961 @endcode 962 @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. 963 **/ 964 #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D 965 966 /** 967 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP 968 **/ 969 typedef union { 970 /// 971 /// Individual bit fields 972 /// 973 struct { 974 UINT32 Reserved1:32; 975 UINT32 Reserved2:26; 976 /// 977 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the 978 /// SMM code access restriction is supported and the 979 /// MSR_SMM_FEATURE_CONTROL is supported. 980 /// 981 UINT32 SMM_Code_Access_Chk:1; 982 /// 983 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the 984 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is 985 /// supported. 986 /// 987 UINT32 Long_Flow_Indication:1; 988 UINT32 Reserved3:4; 989 } Bits; 990 /// 991 /// All bit fields as a 64-bit value 992 /// 993 UINT64 Uint64; 994 } MSR_HASWELL_SMM_MCA_CAP_REGISTER; 995 996 997 /** 998 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 999 RW if MSR_PLATFORM_INFO.[28] = 1. 1000 1001 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD) 1002 @param EAX Lower 32-bits of MSR value. 1003 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER. 1004 @param EDX Upper 32-bits of MSR value. 1005 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER. 1006 1007 <b>Example usage</b> 1008 @code 1009 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr; 1010 1011 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT); 1012 @endcode 1013 @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 1014 **/ 1015 #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD 1016 1017 /** 1018 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT 1019 **/ 1020 typedef union { 1021 /// 1022 /// Individual bit fields 1023 /// 1024 struct { 1025 /// 1026 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio 1027 /// limit of 1 core active. 1028 /// 1029 UINT32 Maximum1C:8; 1030 /// 1031 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio 1032 /// limit of 2 core active. 1033 /// 1034 UINT32 Maximum2C:8; 1035 /// 1036 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio 1037 /// limit of 3 core active. 1038 /// 1039 UINT32 Maximum3C:8; 1040 /// 1041 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio 1042 /// limit of 4 core active. 1043 /// 1044 UINT32 Maximum4C:8; 1045 UINT32 Reserved:32; 1046 } Bits; 1047 /// 1048 /// All bit fields as a 32-bit value 1049 /// 1050 UINT32 Uint32; 1051 /// 1052 /// All bit fields as a 64-bit value 1053 /// 1054 UINT64 Uint64; 1055 } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER; 1056 1057 1058 /** 1059 Package. Uncore PMU global control. 1060 1061 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391) 1062 @param EAX Lower 32-bits of MSR value. 1063 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER. 1064 @param EDX Upper 32-bits of MSR value. 1065 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER. 1066 1067 <b>Example usage</b> 1068 @code 1069 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; 1070 1071 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL); 1072 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); 1073 @endcode 1074 @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. 1075 **/ 1076 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391 1077 1078 /** 1079 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 1080 **/ 1081 typedef union { 1082 /// 1083 /// Individual bit fields 1084 /// 1085 struct { 1086 /// 1087 /// [Bit 0] Core 0 select. 1088 /// 1089 UINT32 PMI_Sel_Core0:1; 1090 /// 1091 /// [Bit 1] Core 1 select. 1092 /// 1093 UINT32 PMI_Sel_Core1:1; 1094 /// 1095 /// [Bit 2] Core 2 select. 1096 /// 1097 UINT32 PMI_Sel_Core2:1; 1098 /// 1099 /// [Bit 3] Core 3 select. 1100 /// 1101 UINT32 PMI_Sel_Core3:1; 1102 UINT32 Reserved1:15; 1103 UINT32 Reserved2:10; 1104 /// 1105 /// [Bit 29] Enable all uncore counters. 1106 /// 1107 UINT32 EN:1; 1108 /// 1109 /// [Bit 30] Enable wake on PMI. 1110 /// 1111 UINT32 WakePMI:1; 1112 /// 1113 /// [Bit 31] Enable Freezing counter when overflow. 1114 /// 1115 UINT32 FREEZE:1; 1116 UINT32 Reserved3:32; 1117 } Bits; 1118 /// 1119 /// All bit fields as a 32-bit value 1120 /// 1121 UINT32 Uint32; 1122 /// 1123 /// All bit fields as a 64-bit value 1124 /// 1125 UINT64 Uint64; 1126 } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER; 1127 1128 1129 /** 1130 Package. Uncore PMU main status. 1131 1132 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392) 1133 @param EAX Lower 32-bits of MSR value. 1134 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER. 1135 @param EDX Upper 32-bits of MSR value. 1136 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER. 1137 1138 <b>Example usage</b> 1139 @code 1140 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; 1141 1142 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS); 1143 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); 1144 @endcode 1145 @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. 1146 **/ 1147 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392 1148 1149 /** 1150 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 1151 **/ 1152 typedef union { 1153 /// 1154 /// Individual bit fields 1155 /// 1156 struct { 1157 /// 1158 /// [Bit 0] Fixed counter overflowed. 1159 /// 1160 UINT32 Fixed:1; 1161 /// 1162 /// [Bit 1] An ARB counter overflowed. 1163 /// 1164 UINT32 ARB:1; 1165 UINT32 Reserved1:1; 1166 /// 1167 /// [Bit 3] A CBox counter overflowed (on any slice). 1168 /// 1169 UINT32 CBox:1; 1170 UINT32 Reserved2:28; 1171 UINT32 Reserved3:32; 1172 } Bits; 1173 /// 1174 /// All bit fields as a 32-bit value 1175 /// 1176 UINT32 Uint32; 1177 /// 1178 /// All bit fields as a 64-bit value 1179 /// 1180 UINT64 Uint64; 1181 } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER; 1182 1183 1184 /** 1185 Package. Uncore fixed counter control (R/W). 1186 1187 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394) 1188 @param EAX Lower 32-bits of MSR value. 1189 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER. 1190 @param EDX Upper 32-bits of MSR value. 1191 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER. 1192 1193 <b>Example usage</b> 1194 @code 1195 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr; 1196 1197 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL); 1198 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64); 1199 @endcode 1200 @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. 1201 **/ 1202 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394 1203 1204 /** 1205 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL 1206 **/ 1207 typedef union { 1208 /// 1209 /// Individual bit fields 1210 /// 1211 struct { 1212 UINT32 Reserved1:20; 1213 /// 1214 /// [Bit 20] Enable overflow propagation. 1215 /// 1216 UINT32 EnableOverflow:1; 1217 UINT32 Reserved2:1; 1218 /// 1219 /// [Bit 22] Enable counting. 1220 /// 1221 UINT32 EnableCounting:1; 1222 UINT32 Reserved3:9; 1223 UINT32 Reserved4:32; 1224 } Bits; 1225 /// 1226 /// All bit fields as a 32-bit value 1227 /// 1228 UINT32 Uint32; 1229 /// 1230 /// All bit fields as a 64-bit value 1231 /// 1232 UINT64 Uint64; 1233 } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER; 1234 1235 1236 /** 1237 Package. Uncore fixed counter. 1238 1239 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395) 1240 @param EAX Lower 32-bits of MSR value. 1241 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER. 1242 @param EDX Upper 32-bits of MSR value. 1243 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER. 1244 1245 <b>Example usage</b> 1246 @code 1247 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr; 1248 1249 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR); 1250 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64); 1251 @endcode 1252 @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. 1253 **/ 1254 #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395 1255 1256 /** 1257 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR 1258 **/ 1259 typedef union { 1260 /// 1261 /// Individual bit fields 1262 /// 1263 struct { 1264 /// 1265 /// [Bits 31:0] Current count. 1266 /// 1267 UINT32 CurrentCount:32; 1268 /// 1269 /// [Bits 47:32] Current count. 1270 /// 1271 UINT32 CurrentCountHi:16; 1272 UINT32 Reserved:16; 1273 } Bits; 1274 /// 1275 /// All bit fields as a 64-bit value 1276 /// 1277 UINT64 Uint64; 1278 } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER; 1279 1280 1281 /** 1282 Package. Uncore C-Box configuration information (R/O). 1283 1284 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396) 1285 @param EAX Lower 32-bits of MSR value. 1286 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER. 1287 @param EDX Upper 32-bits of MSR value. 1288 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER. 1289 1290 <b>Example usage</b> 1291 @code 1292 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr; 1293 1294 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG); 1295 @endcode 1296 @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. 1297 **/ 1298 #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396 1299 1300 /** 1301 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG 1302 **/ 1303 typedef union { 1304 /// 1305 /// Individual bit fields 1306 /// 1307 struct { 1308 /// 1309 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1". 1310 /// 1311 UINT32 CBox:4; 1312 UINT32 Reserved1:28; 1313 UINT32 Reserved2:32; 1314 } Bits; 1315 /// 1316 /// All bit fields as a 32-bit value 1317 /// 1318 UINT32 Uint32; 1319 /// 1320 /// All bit fields as a 64-bit value 1321 /// 1322 UINT64 Uint64; 1323 } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER; 1324 1325 1326 /** 1327 Package. Uncore Arb unit, performance counter 0. 1328 1329 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0) 1330 @param EAX Lower 32-bits of MSR value. 1331 @param EDX Upper 32-bits of MSR value. 1332 1333 <b>Example usage</b> 1334 @code 1335 UINT64 Msr; 1336 1337 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0); 1338 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr); 1339 @endcode 1340 @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. 1341 **/ 1342 #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0 1343 1344 1345 /** 1346 Package. Uncore Arb unit, performance counter 1. 1347 1348 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1) 1349 @param EAX Lower 32-bits of MSR value. 1350 @param EDX Upper 32-bits of MSR value. 1351 1352 <b>Example usage</b> 1353 @code 1354 UINT64 Msr; 1355 1356 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1); 1357 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr); 1358 @endcode 1359 @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. 1360 **/ 1361 #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1 1362 1363 1364 /** 1365 Package. Uncore Arb unit, counter 0 event select MSR. 1366 1367 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2) 1368 @param EAX Lower 32-bits of MSR value. 1369 @param EDX Upper 32-bits of MSR value. 1370 1371 <b>Example usage</b> 1372 @code 1373 UINT64 Msr; 1374 1375 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0); 1376 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr); 1377 @endcode 1378 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. 1379 **/ 1380 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2 1381 1382 1383 /** 1384 Package. Uncore Arb unit, counter 1 event select MSR. 1385 1386 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3) 1387 @param EAX Lower 32-bits of MSR value. 1388 @param EDX Upper 32-bits of MSR value. 1389 1390 <b>Example usage</b> 1391 @code 1392 UINT64 Msr; 1393 1394 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1); 1395 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr); 1396 @endcode 1397 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM. 1398 **/ 1399 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3 1400 1401 1402 /** 1403 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability 1404 Enhancement. Accessible only while in SMM. 1405 1406 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0) 1407 @param EAX Lower 32-bits of MSR value. 1408 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER. 1409 @param EDX Upper 32-bits of MSR value. 1410 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER. 1411 1412 <b>Example usage</b> 1413 @code 1414 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr; 1415 1416 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL); 1417 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64); 1418 @endcode 1419 @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM. 1420 **/ 1421 #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0 1422 1423 /** 1424 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL 1425 **/ 1426 typedef union { 1427 /// 1428 /// Individual bit fields 1429 /// 1430 struct { 1431 /// 1432 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from 1433 /// further changes. 1434 /// 1435 UINT32 Lock:1; 1436 UINT32 Reserved1:1; 1437 /// 1438 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if 1439 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the 1440 /// logical processors are prevented from executing SMM code outside the 1441 /// ranges defined by the SMRR. When set to '1' any logical processor in 1442 /// the package that attempts to execute SMM code not within the ranges 1443 /// defined by the SMRR will assert an unrecoverable MCE. 1444 /// 1445 UINT32 SMM_Code_Chk_En:1; 1446 UINT32 Reserved2:29; 1447 UINT32 Reserved3:32; 1448 } Bits; 1449 /// 1450 /// All bit fields as a 32-bit value 1451 /// 1452 UINT32 Uint32; 1453 /// 1454 /// All bit fields as a 64-bit value 1455 /// 1456 UINT64 Uint64; 1457 } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER; 1458 1459 1460 /** 1461 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical 1462 processors in the package. Available only while in SMM and 1463 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. 1464 1465 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1466 processor of its state in a long flow of internal operation which 1467 delays servicing an interrupt. The corresponding bit will be set at 1468 the start of long events such as: Microcode Update Load, C6, WBINVD, 1469 Ratio Change, Throttle. The bit is automatically cleared at the end of 1470 each long event. The reset value of this field is 0. Only bit 1471 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be 1472 updated. 1473 1474 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1475 processor of its state in a long flow of internal operation which 1476 delays servicing an interrupt. The corresponding bit will be set at 1477 the start of long events such as: Microcode Update Load, C6, WBINVD, 1478 Ratio Change, Throttle. The bit is automatically cleared at the end of 1479 each long event. The reset value of this field is 0. Only bit 1480 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be 1481 updated. 1482 1483 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2) 1484 @param EAX Lower 32-bits of MSR value. 1485 @param EDX Upper 32-bits of MSR value. 1486 1487 <b>Example usage</b> 1488 @code 1489 UINT64 Msr; 1490 1491 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED); 1492 @endcode 1493 @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM. 1494 **/ 1495 #define MSR_HASWELL_SMM_DELAYED 0x000004E2 1496 1497 1498 /** 1499 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical 1500 processors in the package. Available only while in SMM. 1501 1502 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1503 processor of its blocked state to service an SMI. The corresponding 1504 bit will be set if the logical processor is in one of the following 1505 states: Wait For SIPI or SENTER Sleep. The reset value of this field 1506 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, 1507 ECX=PKG_LVL):EBX[15:0] can be updated. 1508 1509 1510 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1511 processor of its blocked state to service an SMI. The corresponding 1512 bit will be set if the logical processor is in one of the following 1513 states: Wait For SIPI or SENTER Sleep. The reset value of this field 1514 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, 1515 ECX=PKG_LVL):EBX[15:0] can be updated. 1516 1517 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3) 1518 @param EAX Lower 32-bits of MSR value. 1519 @param EDX Upper 32-bits of MSR value. 1520 1521 <b>Example usage</b> 1522 @code 1523 UINT64 Msr; 1524 1525 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED); 1526 @endcode 1527 @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM. 1528 **/ 1529 #define MSR_HASWELL_SMM_BLOCKED 0x000004E3 1530 1531 1532 /** 1533 Package. Unit Multipliers used in RAPL Interfaces (R/O). 1534 1535 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606) 1536 @param EAX Lower 32-bits of MSR value. 1537 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER. 1538 @param EDX Upper 32-bits of MSR value. 1539 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER. 1540 1541 <b>Example usage</b> 1542 @code 1543 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr; 1544 1545 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT); 1546 @endcode 1547 @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 1548 **/ 1549 #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606 1550 1551 /** 1552 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT 1553 **/ 1554 typedef union { 1555 /// 1556 /// Individual bit fields 1557 /// 1558 struct { 1559 /// 1560 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". 1561 /// 1562 UINT32 PowerUnits:4; 1563 UINT32 Reserved1:4; 1564 /// 1565 /// [Bits 12:8] Package. Energy Status Units Energy related information 1566 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an 1567 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 1568 /// micro-joules). 1569 /// 1570 UINT32 EnergyStatusUnits:5; 1571 UINT32 Reserved2:3; 1572 /// 1573 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL 1574 /// Interfaces.". 1575 /// 1576 UINT32 TimeUnits:4; 1577 UINT32 Reserved3:12; 1578 UINT32 Reserved4:32; 1579 } Bits; 1580 /// 1581 /// All bit fields as a 32-bit value 1582 /// 1583 UINT32 Uint32; 1584 /// 1585 /// All bit fields as a 64-bit value 1586 /// 1587 UINT64 Uint64; 1588 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER; 1589 1590 1591 /** 1592 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1593 Domains.". 1594 1595 @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639) 1596 @param EAX Lower 32-bits of MSR value. 1597 @param EDX Upper 32-bits of MSR value. 1598 1599 <b>Example usage</b> 1600 @code 1601 UINT64 Msr; 1602 1603 Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS); 1604 @endcode 1605 @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 1606 **/ 1607 #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639 1608 1609 1610 /** 1611 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 1612 RAPL Domains.". 1613 1614 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640) 1615 @param EAX Lower 32-bits of MSR value. 1616 @param EDX Upper 32-bits of MSR value. 1617 1618 <b>Example usage</b> 1619 @code 1620 UINT64 Msr; 1621 1622 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT); 1623 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr); 1624 @endcode 1625 @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM. 1626 **/ 1627 #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640 1628 1629 1630 /** 1631 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1632 Domains.". 1633 1634 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641) 1635 @param EAX Lower 32-bits of MSR value. 1636 @param EDX Upper 32-bits of MSR value. 1637 1638 <b>Example usage</b> 1639 @code 1640 UINT64 Msr; 1641 1642 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS); 1643 @endcode 1644 @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. 1645 **/ 1646 #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641 1647 1648 1649 /** 1650 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL 1651 Domains.". 1652 1653 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642) 1654 @param EAX Lower 32-bits of MSR value. 1655 @param EDX Upper 32-bits of MSR value. 1656 1657 <b>Example usage</b> 1658 @code 1659 UINT64 Msr; 1660 1661 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY); 1662 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr); 1663 @endcode 1664 @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM. 1665 **/ 1666 #define MSR_HASWELL_PP1_POLICY 0x00000642 1667 1668 1669 /** 1670 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 1671 refers to processor core frequency). 1672 1673 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690) 1674 @param EAX Lower 32-bits of MSR value. 1675 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER. 1676 @param EDX Upper 32-bits of MSR value. 1677 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER. 1678 1679 <b>Example usage</b> 1680 @code 1681 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 1682 1683 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS); 1684 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 1685 @endcode 1686 @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 1687 **/ 1688 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690 1689 1690 /** 1691 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS 1692 **/ 1693 typedef union { 1694 /// 1695 /// Individual bit fields 1696 /// 1697 struct { 1698 /// 1699 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is 1700 /// reduced below the operating system request due to assertion of 1701 /// external PROCHOT. 1702 /// 1703 UINT32 PROCHOT_Status:1; 1704 /// 1705 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 1706 /// operating system request due to a thermal event. 1707 /// 1708 UINT32 ThermalStatus:1; 1709 UINT32 Reserved1:2; 1710 /// 1711 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced 1712 /// below the operating system request due to Processor Graphics driver 1713 /// override. 1714 /// 1715 UINT32 GraphicsDriverStatus:1; 1716 /// 1717 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) 1718 /// When set, frequency is reduced below the operating system request 1719 /// because the processor has detected that utilization is low. 1720 /// 1721 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; 1722 /// 1723 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 1724 /// below the operating system request due to a thermal alert from the 1725 /// Voltage Regulator. 1726 /// 1727 UINT32 VRThermAlertStatus:1; 1728 UINT32 Reserved2:1; 1729 /// 1730 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 1731 /// reduced below the operating system request due to electrical design 1732 /// point constraints (e.g. maximum electrical current consumption). 1733 /// 1734 UINT32 ElectricalDesignPointStatus:1; 1735 /// 1736 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced 1737 /// below the operating system request due to domain-level power limiting. 1738 /// 1739 UINT32 PLStatus:1; 1740 /// 1741 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, 1742 /// frequency is reduced below the operating system request due to 1743 /// package-level power limiting PL1. 1744 /// 1745 UINT32 PL1Status:1; 1746 /// 1747 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, 1748 /// frequency is reduced below the operating system request due to 1749 /// package-level power limiting PL2. 1750 /// 1751 UINT32 PL2Status:1; 1752 /// 1753 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced 1754 /// below the operating system request due to multi-core turbo limits. 1755 /// 1756 UINT32 MaxTurboLimitStatus:1; 1757 /// 1758 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency 1759 /// is reduced below the operating system request due to Turbo transition 1760 /// attenuation. This prevents performance degradation due to frequent 1761 /// operating ratio changes. 1762 /// 1763 UINT32 TurboTransitionAttenuationStatus:1; 1764 UINT32 Reserved3:2; 1765 /// 1766 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 1767 /// has asserted since the log bit was last cleared. This log bit will 1768 /// remain set until cleared by software writing 0. 1769 /// 1770 UINT32 PROCHOT_Log:1; 1771 /// 1772 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 1773 /// has asserted since the log bit was last cleared. This log bit will 1774 /// remain set until cleared by software writing 0. 1775 /// 1776 UINT32 ThermalLog:1; 1777 UINT32 Reserved4:2; 1778 /// 1779 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics 1780 /// Driver Status bit has asserted since the log bit was last cleared. 1781 /// This log bit will remain set until cleared by software writing 0. 1782 /// 1783 UINT32 GraphicsDriverLog:1; 1784 /// 1785 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 1786 /// indicates that the Autonomous Utilization-Based Frequency Control 1787 /// Status bit has asserted since the log bit was last cleared. This log 1788 /// bit will remain set until cleared by software writing 0. 1789 /// 1790 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 1791 /// 1792 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 1793 /// Alert Status bit has asserted since the log bit was last cleared. This 1794 /// log bit will remain set until cleared by software writing 0. 1795 /// 1796 UINT32 VRThermAlertLog:1; 1797 UINT32 Reserved5:1; 1798 /// 1799 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 1800 /// Status bit has asserted since the log bit was last cleared. This log 1801 /// bit will remain set until cleared by software writing 0. 1802 /// 1803 UINT32 ElectricalDesignPointLog:1; 1804 /// 1805 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 1806 /// Power Limiting Status bit has asserted since the log bit was last 1807 /// cleared. This log bit will remain set until cleared by software 1808 /// writing 0. 1809 /// 1810 UINT32 PLLog:1; 1811 /// 1812 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates 1813 /// that the Package Level PL1 Power Limiting Status bit has asserted 1814 /// since the log bit was last cleared. This log bit will remain set until 1815 /// cleared by software writing 0. 1816 /// 1817 UINT32 PL1Log:1; 1818 /// 1819 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that 1820 /// the Package Level PL2 Power Limiting Status bit has asserted since the 1821 /// log bit was last cleared. This log bit will remain set until cleared 1822 /// by software writing 0. 1823 /// 1824 UINT32 PL2Log:1; 1825 /// 1826 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 1827 /// Limit Status bit has asserted since the log bit was last cleared. This 1828 /// log bit will remain set until cleared by software writing 0. 1829 /// 1830 UINT32 MaxTurboLimitLog:1; 1831 /// 1832 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 1833 /// Turbo Transition Attenuation Status bit has asserted since the log bit 1834 /// was last cleared. This log bit will remain set until cleared by 1835 /// software writing 0. 1836 /// 1837 UINT32 TurboTransitionAttenuationLog:1; 1838 UINT32 Reserved6:2; 1839 UINT32 Reserved7:32; 1840 } Bits; 1841 /// 1842 /// All bit fields as a 32-bit value 1843 /// 1844 UINT32 Uint32; 1845 /// 1846 /// All bit fields as a 64-bit value 1847 /// 1848 UINT64 Uint64; 1849 } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER; 1850 1851 1852 /** 1853 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) 1854 (frequency refers to processor graphics frequency). 1855 1856 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) 1857 @param EAX Lower 32-bits of MSR value. 1858 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. 1859 @param EDX Upper 32-bits of MSR value. 1860 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. 1861 1862 <b>Example usage</b> 1863 @code 1864 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr; 1865 1866 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS); 1867 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64); 1868 @endcode 1869 @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM. 1870 **/ 1871 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 1872 1873 /** 1874 MSR information returned for MSR index 1875 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 1876 **/ 1877 typedef union { 1878 /// 1879 /// Individual bit fields 1880 /// 1881 struct { 1882 /// 1883 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the 1884 /// operating system request due to assertion of external PROCHOT. 1885 /// 1886 UINT32 PROCHOT_Status:1; 1887 /// 1888 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 1889 /// operating system request due to a thermal event. 1890 /// 1891 UINT32 ThermalStatus:1; 1892 UINT32 Reserved1:2; 1893 /// 1894 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced 1895 /// below the operating system request due to Processor Graphics driver 1896 /// override. 1897 /// 1898 UINT32 GraphicsDriverStatus:1; 1899 /// 1900 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) 1901 /// When set, frequency is reduced below the operating system request 1902 /// because the processor has detected that utilization is low. 1903 /// 1904 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; 1905 /// 1906 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 1907 /// below the operating system request due to a thermal alert from the 1908 /// Voltage Regulator. 1909 /// 1910 UINT32 VRThermAlertStatus:1; 1911 UINT32 Reserved2:1; 1912 /// 1913 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 1914 /// reduced below the operating system request due to electrical design 1915 /// point constraints (e.g. maximum electrical current consumption). 1916 /// 1917 UINT32 ElectricalDesignPointStatus:1; 1918 /// 1919 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is 1920 /// reduced below the operating system request due to domain-level power 1921 /// limiting. 1922 /// 1923 UINT32 GraphicsPowerLimitingStatus:1; 1924 /// 1925 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, 1926 /// frequency is reduced below the operating system request due to 1927 /// package-level power limiting PL1. 1928 /// 1929 UINT32 PL1STatus:1; 1930 /// 1931 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, 1932 /// frequency is reduced below the operating system request due to 1933 /// package-level power limiting PL2. 1934 /// 1935 UINT32 PL2Status:1; 1936 UINT32 Reserved3:4; 1937 /// 1938 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 1939 /// has asserted since the log bit was last cleared. This log bit will 1940 /// remain set until cleared by software writing 0. 1941 /// 1942 UINT32 PROCHOT_Log:1; 1943 /// 1944 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 1945 /// has asserted since the log bit was last cleared. This log bit will 1946 /// remain set until cleared by software writing 0. 1947 /// 1948 UINT32 ThermalLog:1; 1949 UINT32 Reserved4:2; 1950 /// 1951 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics 1952 /// Driver Status bit has asserted since the log bit was last cleared. 1953 /// This log bit will remain set until cleared by software writing 0. 1954 /// 1955 UINT32 GraphicsDriverLog:1; 1956 /// 1957 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 1958 /// indicates that the Autonomous Utilization-Based Frequency Control 1959 /// Status bit has asserted since the log bit was last cleared. This log 1960 /// bit will remain set until cleared by software writing 0. 1961 /// 1962 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 1963 /// 1964 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 1965 /// Alert Status bit has asserted since the log bit was last cleared. This 1966 /// log bit will remain set until cleared by software writing 0. 1967 /// 1968 UINT32 VRThermAlertLog:1; 1969 UINT32 Reserved5:1; 1970 /// 1971 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 1972 /// Status bit has asserted since the log bit was last cleared. This log 1973 /// bit will remain set until cleared by software writing 0. 1974 /// 1975 UINT32 ElectricalDesignPointLog:1; 1976 /// 1977 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 1978 /// Power Limiting Status bit has asserted since the log bit was last 1979 /// cleared. This log bit will remain set until cleared by software 1980 /// writing 0. 1981 /// 1982 UINT32 CorePowerLimitingLog:1; 1983 /// 1984 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates 1985 /// that the Package Level PL1 Power Limiting Status bit has asserted 1986 /// since the log bit was last cleared. This log bit will remain set until 1987 /// cleared by software writing 0. 1988 /// 1989 UINT32 PL1Log:1; 1990 /// 1991 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that 1992 /// the Package Level PL2 Power Limiting Status bit has asserted since the 1993 /// log bit was last cleared. This log bit will remain set until cleared 1994 /// by software writing 0. 1995 /// 1996 UINT32 PL2Log:1; 1997 /// 1998 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 1999 /// Limit Status bit has asserted since the log bit was last cleared. This 2000 /// log bit will remain set until cleared by software writing 0. 2001 /// 2002 UINT32 MaxTurboLimitLog:1; 2003 /// 2004 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 2005 /// Turbo Transition Attenuation Status bit has asserted since the log bit 2006 /// was last cleared. This log bit will remain set until cleared by 2007 /// software writing 0. 2008 /// 2009 UINT32 TurboTransitionAttenuationLog:1; 2010 UINT32 Reserved6:2; 2011 UINT32 Reserved7:32; 2012 } Bits; 2013 /// 2014 /// All bit fields as a 32-bit value 2015 /// 2016 UINT32 Uint32; 2017 /// 2018 /// All bit fields as a 64-bit value 2019 /// 2020 UINT64 Uint64; 2021 } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER; 2022 2023 2024 /** 2025 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) 2026 (frequency refers to ring interconnect in the uncore). 2027 2028 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1) 2029 @param EAX Lower 32-bits of MSR value. 2030 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER. 2031 @param EDX Upper 32-bits of MSR value. 2032 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER. 2033 2034 <b>Example usage</b> 2035 @code 2036 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr; 2037 2038 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS); 2039 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64); 2040 @endcode 2041 @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM. 2042 **/ 2043 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1 2044 2045 /** 2046 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS 2047 **/ 2048 typedef union { 2049 /// 2050 /// Individual bit fields 2051 /// 2052 struct { 2053 /// 2054 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the 2055 /// operating system request due to assertion of external PROCHOT. 2056 /// 2057 UINT32 PROCHOT_Status:1; 2058 /// 2059 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 2060 /// operating system request due to a thermal event. 2061 /// 2062 UINT32 ThermalStatus:1; 2063 UINT32 Reserved1:4; 2064 /// 2065 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 2066 /// below the operating system request due to a thermal alert from the 2067 /// Voltage Regulator. 2068 /// 2069 UINT32 VRThermAlertStatus:1; 2070 UINT32 Reserved2:1; 2071 /// 2072 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 2073 /// reduced below the operating system request due to electrical design 2074 /// point constraints (e.g. maximum electrical current consumption). 2075 /// 2076 UINT32 ElectricalDesignPointStatus:1; 2077 UINT32 Reserved3:1; 2078 /// 2079 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, 2080 /// frequency is reduced below the operating system request due to 2081 /// package-level power limiting PL1. 2082 /// 2083 UINT32 PL1STatus:1; 2084 /// 2085 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, 2086 /// frequency is reduced below the operating system request due to 2087 /// package-level power limiting PL2. 2088 /// 2089 UINT32 PL2Status:1; 2090 UINT32 Reserved4:4; 2091 /// 2092 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 2093 /// has asserted since the log bit was last cleared. This log bit will 2094 /// remain set until cleared by software writing 0. 2095 /// 2096 UINT32 PROCHOT_Log:1; 2097 /// 2098 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 2099 /// has asserted since the log bit was last cleared. This log bit will 2100 /// remain set until cleared by software writing 0. 2101 /// 2102 UINT32 ThermalLog:1; 2103 UINT32 Reserved5:2; 2104 /// 2105 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics 2106 /// Driver Status bit has asserted since the log bit was last cleared. 2107 /// This log bit will remain set until cleared by software writing 0. 2108 /// 2109 UINT32 GraphicsDriverLog:1; 2110 /// 2111 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 2112 /// indicates that the Autonomous Utilization-Based Frequency Control 2113 /// Status bit has asserted since the log bit was last cleared. This log 2114 /// bit will remain set until cleared by software writing 0. 2115 /// 2116 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 2117 /// 2118 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 2119 /// Alert Status bit has asserted since the log bit was last cleared. This 2120 /// log bit will remain set until cleared by software writing 0. 2121 /// 2122 UINT32 VRThermAlertLog:1; 2123 UINT32 Reserved6:1; 2124 /// 2125 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 2126 /// Status bit has asserted since the log bit was last cleared. This log 2127 /// bit will remain set until cleared by software writing 0. 2128 /// 2129 UINT32 ElectricalDesignPointLog:1; 2130 /// 2131 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 2132 /// Power Limiting Status bit has asserted since the log bit was last 2133 /// cleared. This log bit will remain set until cleared by software 2134 /// writing 0. 2135 /// 2136 UINT32 CorePowerLimitingLog:1; 2137 /// 2138 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates 2139 /// that the Package Level PL1 Power Limiting Status bit has asserted 2140 /// since the log bit was last cleared. This log bit will remain set until 2141 /// cleared by software writing 0. 2142 /// 2143 UINT32 PL1Log:1; 2144 /// 2145 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that 2146 /// the Package Level PL2 Power Limiting Status bit has asserted since the 2147 /// log bit was last cleared. This log bit will remain set until cleared 2148 /// by software writing 0. 2149 /// 2150 UINT32 PL2Log:1; 2151 /// 2152 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 2153 /// Limit Status bit has asserted since the log bit was last cleared. This 2154 /// log bit will remain set until cleared by software writing 0. 2155 /// 2156 UINT32 MaxTurboLimitLog:1; 2157 /// 2158 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 2159 /// Turbo Transition Attenuation Status bit has asserted since the log bit 2160 /// was last cleared. This log bit will remain set until cleared by 2161 /// software writing 0. 2162 /// 2163 UINT32 TurboTransitionAttenuationLog:1; 2164 UINT32 Reserved7:2; 2165 UINT32 Reserved8:32; 2166 } Bits; 2167 /// 2168 /// All bit fields as a 32-bit value 2169 /// 2170 UINT32 Uint32; 2171 /// 2172 /// All bit fields as a 64-bit value 2173 /// 2174 UINT64 Uint64; 2175 } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER; 2176 2177 2178 /** 2179 Package. Uncore C-Box 0, counter 0 event select MSR. 2180 2181 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700) 2182 @param EAX Lower 32-bits of MSR value. 2183 @param EDX Upper 32-bits of MSR value. 2184 2185 <b>Example usage</b> 2186 @code 2187 UINT64 Msr; 2188 2189 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0); 2190 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr); 2191 @endcode 2192 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. 2193 **/ 2194 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700 2195 2196 2197 /** 2198 Package. Uncore C-Box 0, counter 1 event select MSR. 2199 2200 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701) 2201 @param EAX Lower 32-bits of MSR value. 2202 @param EDX Upper 32-bits of MSR value. 2203 2204 <b>Example usage</b> 2205 @code 2206 UINT64 Msr; 2207 2208 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1); 2209 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr); 2210 @endcode 2211 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. 2212 **/ 2213 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701 2214 2215 2216 /** 2217 Package. Uncore C-Box 0, performance counter 0. 2218 2219 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706) 2220 @param EAX Lower 32-bits of MSR value. 2221 @param EDX Upper 32-bits of MSR value. 2222 2223 <b>Example usage</b> 2224 @code 2225 UINT64 Msr; 2226 2227 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0); 2228 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr); 2229 @endcode 2230 @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. 2231 **/ 2232 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706 2233 2234 2235 /** 2236 Package. Uncore C-Box 0, performance counter 1. 2237 2238 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707) 2239 @param EAX Lower 32-bits of MSR value. 2240 @param EDX Upper 32-bits of MSR value. 2241 2242 <b>Example usage</b> 2243 @code 2244 UINT64 Msr; 2245 2246 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1); 2247 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr); 2248 @endcode 2249 @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. 2250 **/ 2251 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707 2252 2253 2254 /** 2255 Package. Uncore C-Box 1, counter 0 event select MSR. 2256 2257 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710) 2258 @param EAX Lower 32-bits of MSR value. 2259 @param EDX Upper 32-bits of MSR value. 2260 2261 <b>Example usage</b> 2262 @code 2263 UINT64 Msr; 2264 2265 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0); 2266 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr); 2267 @endcode 2268 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. 2269 **/ 2270 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710 2271 2272 2273 /** 2274 Package. Uncore C-Box 1, counter 1 event select MSR. 2275 2276 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711) 2277 @param EAX Lower 32-bits of MSR value. 2278 @param EDX Upper 32-bits of MSR value. 2279 2280 <b>Example usage</b> 2281 @code 2282 UINT64 Msr; 2283 2284 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1); 2285 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr); 2286 @endcode 2287 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. 2288 **/ 2289 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711 2290 2291 2292 /** 2293 Package. Uncore C-Box 1, performance counter 0. 2294 2295 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716) 2296 @param EAX Lower 32-bits of MSR value. 2297 @param EDX Upper 32-bits of MSR value. 2298 2299 <b>Example usage</b> 2300 @code 2301 UINT64 Msr; 2302 2303 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0); 2304 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr); 2305 @endcode 2306 @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. 2307 **/ 2308 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716 2309 2310 2311 /** 2312 Package. Uncore C-Box 1, performance counter 1. 2313 2314 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717) 2315 @param EAX Lower 32-bits of MSR value. 2316 @param EDX Upper 32-bits of MSR value. 2317 2318 <b>Example usage</b> 2319 @code 2320 UINT64 Msr; 2321 2322 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1); 2323 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr); 2324 @endcode 2325 @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. 2326 **/ 2327 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717 2328 2329 2330 /** 2331 Package. Uncore C-Box 2, counter 0 event select MSR. 2332 2333 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720) 2334 @param EAX Lower 32-bits of MSR value. 2335 @param EDX Upper 32-bits of MSR value. 2336 2337 <b>Example usage</b> 2338 @code 2339 UINT64 Msr; 2340 2341 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0); 2342 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr); 2343 @endcode 2344 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. 2345 **/ 2346 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720 2347 2348 2349 /** 2350 Package. Uncore C-Box 2, counter 1 event select MSR. 2351 2352 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721) 2353 @param EAX Lower 32-bits of MSR value. 2354 @param EDX Upper 32-bits of MSR value. 2355 2356 <b>Example usage</b> 2357 @code 2358 UINT64 Msr; 2359 2360 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1); 2361 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr); 2362 @endcode 2363 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. 2364 **/ 2365 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721 2366 2367 2368 /** 2369 Package. Uncore C-Box 2, performance counter 0. 2370 2371 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726) 2372 @param EAX Lower 32-bits of MSR value. 2373 @param EDX Upper 32-bits of MSR value. 2374 2375 <b>Example usage</b> 2376 @code 2377 UINT64 Msr; 2378 2379 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0); 2380 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr); 2381 @endcode 2382 @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. 2383 **/ 2384 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726 2385 2386 2387 /** 2388 Package. Uncore C-Box 2, performance counter 1. 2389 2390 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727) 2391 @param EAX Lower 32-bits of MSR value. 2392 @param EDX Upper 32-bits of MSR value. 2393 2394 <b>Example usage</b> 2395 @code 2396 UINT64 Msr; 2397 2398 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1); 2399 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr); 2400 @endcode 2401 @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. 2402 **/ 2403 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727 2404 2405 2406 /** 2407 Package. Uncore C-Box 3, counter 0 event select MSR. 2408 2409 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730) 2410 @param EAX Lower 32-bits of MSR value. 2411 @param EDX Upper 32-bits of MSR value. 2412 2413 <b>Example usage</b> 2414 @code 2415 UINT64 Msr; 2416 2417 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0); 2418 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr); 2419 @endcode 2420 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. 2421 **/ 2422 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730 2423 2424 2425 /** 2426 Package. Uncore C-Box 3, counter 1 event select MSR. 2427 2428 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731) 2429 @param EAX Lower 32-bits of MSR value. 2430 @param EDX Upper 32-bits of MSR value. 2431 2432 <b>Example usage</b> 2433 @code 2434 UINT64 Msr; 2435 2436 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1); 2437 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr); 2438 @endcode 2439 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. 2440 **/ 2441 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731 2442 2443 2444 /** 2445 Package. Uncore C-Box 3, performance counter 0. 2446 2447 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736) 2448 @param EAX Lower 32-bits of MSR value. 2449 @param EDX Upper 32-bits of MSR value. 2450 2451 <b>Example usage</b> 2452 @code 2453 UINT64 Msr; 2454 2455 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0); 2456 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr); 2457 @endcode 2458 @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. 2459 **/ 2460 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736 2461 2462 2463 /** 2464 Package. Uncore C-Box 3, performance counter 1. 2465 2466 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737) 2467 @param EAX Lower 32-bits of MSR value. 2468 @param EDX Upper 32-bits of MSR value. 2469 2470 <b>Example usage</b> 2471 @code 2472 UINT64 Msr; 2473 2474 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1); 2475 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr); 2476 @endcode 2477 @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. 2478 **/ 2479 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737 2480 2481 2482 /** 2483 Package. Note: C-state values are processor specific C-state code names, 2484 unrelated to MWAIT extension C-state parameters or ACPI C-States. 2485 2486 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630) 2487 @param EAX Lower 32-bits of MSR value. 2488 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER. 2489 @param EDX Upper 32-bits of MSR value. 2490 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER. 2491 2492 <b>Example usage</b> 2493 @code 2494 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr; 2495 2496 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY); 2497 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64); 2498 @endcode 2499 @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM. 2500 **/ 2501 #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630 2502 2503 /** 2504 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY 2505 **/ 2506 typedef union { 2507 /// 2508 /// Individual bit fields 2509 /// 2510 struct { 2511 /// 2512 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset 2513 /// that this package is in processor-specific C8 states. Count at the 2514 /// same frequency as the TSC. 2515 /// 2516 UINT32 C8ResidencyCounter:32; 2517 /// 2518 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last 2519 /// reset that this package is in processor-specific C8 states. Count at 2520 /// the same frequency as the TSC. 2521 /// 2522 UINT32 C8ResidencyCounterHi:28; 2523 UINT32 Reserved:4; 2524 } Bits; 2525 /// 2526 /// All bit fields as a 64-bit value 2527 /// 2528 UINT64 Uint64; 2529 } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER; 2530 2531 2532 /** 2533 Package. Note: C-state values are processor specific C-state code names, 2534 unrelated to MWAIT extension C-state parameters or ACPI C-States. 2535 2536 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631) 2537 @param EAX Lower 32-bits of MSR value. 2538 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER. 2539 @param EDX Upper 32-bits of MSR value. 2540 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER. 2541 2542 <b>Example usage</b> 2543 @code 2544 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr; 2545 2546 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY); 2547 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64); 2548 @endcode 2549 @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM. 2550 **/ 2551 #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631 2552 2553 /** 2554 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY 2555 **/ 2556 typedef union { 2557 /// 2558 /// Individual bit fields 2559 /// 2560 struct { 2561 /// 2562 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset 2563 /// that this package is in processor-specific C9 states. Count at the 2564 /// same frequency as the TSC. 2565 /// 2566 UINT32 C9ResidencyCounter:32; 2567 /// 2568 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last 2569 /// reset that this package is in processor-specific C9 states. Count at 2570 /// the same frequency as the TSC. 2571 /// 2572 UINT32 C9ResidencyCounterHi:28; 2573 UINT32 Reserved:4; 2574 } Bits; 2575 /// 2576 /// All bit fields as a 64-bit value 2577 /// 2578 UINT64 Uint64; 2579 } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER; 2580 2581 2582 /** 2583 Package. Note: C-state values are processor specific C-state code names, 2584 unrelated to MWAIT extension C-state parameters or ACPI C-States. 2585 2586 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632) 2587 @param EAX Lower 32-bits of MSR value. 2588 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER. 2589 @param EDX Upper 32-bits of MSR value. 2590 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER. 2591 2592 <b>Example usage</b> 2593 @code 2594 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr; 2595 2596 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY); 2597 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64); 2598 @endcode 2599 @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM. 2600 **/ 2601 #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632 2602 2603 /** 2604 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY 2605 **/ 2606 typedef union { 2607 /// 2608 /// Individual bit fields 2609 /// 2610 struct { 2611 /// 2612 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last 2613 /// reset that this package is in processor-specific C10 states. Count at 2614 /// the same frequency as the TSC. 2615 /// 2616 UINT32 C10ResidencyCounter:32; 2617 /// 2618 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last 2619 /// reset that this package is in processor-specific C10 states. Count at 2620 /// the same frequency as the TSC. 2621 /// 2622 UINT32 C10ResidencyCounterHi:28; 2623 UINT32 Reserved:4; 2624 } Bits; 2625 /// 2626 /// All bit fields as a 64-bit value 2627 /// 2628 UINT64 Uint64; 2629 } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER; 2630 2631 #endif 2632