1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP11x. 6 */ 7 8#include "armada-common.dtsi" 9 10#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) 11 12/ { 13 /* 14 * The contents of the node are defined below, in order to 15 * save one indentation level 16 */ 17 CP11X_NAME: CP11X_NAME { }; 18 19 /* 20 * CPs only have one sensor in the thermal IC. 21 * 22 * The cooling maps are empty as there are no cooling devices. 23 */ 24 thermal-zones { 25 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { 26 polling-delay-passive = <0>; /* Interrupt driven */ 27 polling-delay = <0>; /* Interrupt driven */ 28 29 thermal-sensors = <&CP11X_LABEL(thermal) 0>; 30 31 trips { 32 CP11X_LABEL(crit): crit { 33 temperature = <100000>; /* mC degrees */ 34 hysteresis = <2000>; /* mC degrees */ 35 type = "critical"; 36 }; 37 }; 38 39 cooling-maps { }; 40 }; 41 }; 42}; 43 44&CP11X_NAME { 45 #address-cells = <2>; 46 #size-cells = <2>; 47 compatible = "simple-bus"; 48 interrupt-parent = <&CP11X_LABEL(icu_nsr)>; 49 ranges; 50 51 config-space@CP11X_BASE { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 compatible = "simple-bus"; 55 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; 56 57 CP11X_LABEL(ethernet): ethernet@0 { 58 compatible = "marvell,armada-7k-pp22"; 59 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; 60 clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, 61 <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>, 62 <&CP11X_LABEL(core_clk)>; 63 clock-names = "pp_clk", "gop_clk", 64 "mg_clk", "mg_core_clk", "axi_clk"; 65 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 66 status = "disabled"; 67 dma-coherent; 68 69 CP11X_LABEL(eth0): eth0 { 70 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, 71 <43 IRQ_TYPE_LEVEL_HIGH>, 72 <47 IRQ_TYPE_LEVEL_HIGH>, 73 <51 IRQ_TYPE_LEVEL_HIGH>, 74 <55 IRQ_TYPE_LEVEL_HIGH>, 75 <59 IRQ_TYPE_LEVEL_HIGH>, 76 <63 IRQ_TYPE_LEVEL_HIGH>, 77 <67 IRQ_TYPE_LEVEL_HIGH>, 78 <71 IRQ_TYPE_LEVEL_HIGH>, 79 <129 IRQ_TYPE_LEVEL_HIGH>; 80 interrupt-names = "hif0", "hif1", "hif2", 81 "hif3", "hif4", "hif5", "hif6", "hif7", 82 "hif8", "link"; 83 port-id = <0>; 84 gop-port-id = <0>; 85 status = "disabled"; 86 }; 87 88 CP11X_LABEL(eth1): eth1 { 89 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, 90 <44 IRQ_TYPE_LEVEL_HIGH>, 91 <48 IRQ_TYPE_LEVEL_HIGH>, 92 <52 IRQ_TYPE_LEVEL_HIGH>, 93 <56 IRQ_TYPE_LEVEL_HIGH>, 94 <60 IRQ_TYPE_LEVEL_HIGH>, 95 <64 IRQ_TYPE_LEVEL_HIGH>, 96 <68 IRQ_TYPE_LEVEL_HIGH>, 97 <72 IRQ_TYPE_LEVEL_HIGH>, 98 <128 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-names = "hif0", "hif1", "hif2", 100 "hif3", "hif4", "hif5", "hif6", "hif7", 101 "hif8", "link"; 102 port-id = <1>; 103 gop-port-id = <2>; 104 status = "disabled"; 105 }; 106 107 CP11X_LABEL(eth2): eth2 { 108 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, 109 <45 IRQ_TYPE_LEVEL_HIGH>, 110 <49 IRQ_TYPE_LEVEL_HIGH>, 111 <53 IRQ_TYPE_LEVEL_HIGH>, 112 <57 IRQ_TYPE_LEVEL_HIGH>, 113 <61 IRQ_TYPE_LEVEL_HIGH>, 114 <65 IRQ_TYPE_LEVEL_HIGH>, 115 <69 IRQ_TYPE_LEVEL_HIGH>, 116 <73 IRQ_TYPE_LEVEL_HIGH>, 117 <127 IRQ_TYPE_LEVEL_HIGH>; 118 interrupt-names = "hif0", "hif1", "hif2", 119 "hif3", "hif4", "hif5", "hif6", "hif7", 120 "hif8", "link"; 121 port-id = <2>; 122 gop-port-id = <3>; 123 status = "disabled"; 124 }; 125 }; 126 127 CP11X_LABEL(comphy): phy@120000 { 128 compatible = "marvell,comphy-cp110"; 129 reg = <0x120000 0x6000>; 130 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 131 clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>, 132 <&CP11X_LABEL(core_clk)>; 133 clock-names = "mg_clk", "mg_core_clk", "axi_clk"; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 CP11X_LABEL(comphy0): phy@0 { 138 reg = <0>; 139 #phy-cells = <1>; 140 }; 141 142 CP11X_LABEL(comphy1): phy@1 { 143 reg = <1>; 144 #phy-cells = <1>; 145 }; 146 147 CP11X_LABEL(comphy2): phy@2 { 148 reg = <2>; 149 #phy-cells = <1>; 150 }; 151 152 CP11X_LABEL(comphy3): phy@3 { 153 reg = <3>; 154 #phy-cells = <1>; 155 }; 156 157 CP11X_LABEL(comphy4): phy@4 { 158 reg = <4>; 159 #phy-cells = <1>; 160 }; 161 162 CP11X_LABEL(comphy5): phy@5 { 163 reg = <5>; 164 #phy-cells = <1>; 165 }; 166 }; 167 168 CP11X_LABEL(mdio): mdio@12a200 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "marvell,orion-mdio"; 172 reg = <0x12a200 0x10>; 173 clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, 174 <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(core_clk)>; 175 status = "disabled"; 176 }; 177 178 CP11X_LABEL(xmdio): mdio@12a600 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "marvell,xmdio"; 182 reg = <0x12a600 0x10>; 183 clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, 184 <&CP11X_LABEL(core_clk)>; 185 status = "disabled"; 186 }; 187 188 CP11X_LABEL(icu): interrupt-controller@1e0000 { 189 compatible = "marvell,cp110-icu"; 190 reg = <0x1e0000 0x440>; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 194 CP11X_LABEL(icu_nsr): interrupt-controller@10 { 195 compatible = "marvell,cp110-icu-nsr"; 196 reg = <0x10 0x20>; 197 #interrupt-cells = <2>; 198 interrupt-controller; 199 msi-parent = <&gicp>; 200 }; 201 202 CP11X_LABEL(icu_sei): interrupt-controller@50 { 203 compatible = "marvell,cp110-icu-sei"; 204 reg = <0x50 0x10>; 205 #interrupt-cells = <2>; 206 interrupt-controller; 207 msi-parent = <&sei>; 208 }; 209 }; 210 211 CP11X_LABEL(rtc): rtc@284000 { 212 compatible = "marvell,armada-8k-rtc"; 213 reg = <0x284000 0x20>, <0x284080 0x24>; 214 reg-names = "rtc", "rtc-soc"; 215 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; 216 status = "disabled"; 217 }; 218 219 CP11X_LABEL(syscon0): system-controller@440000 { 220 compatible = "syscon", "simple-mfd"; 221 reg = <0x440000 0x2000>; 222 223 CP11X_LABEL(clk): clock { 224 compatible = "marvell,cp110-clock"; 225 status = "disabled"; 226 #clock-cells = <2>; 227 }; 228 229 CP11X_LABEL(gpio1): gpio@100 { 230 compatible = "marvell,armada-8k-gpio"; 231 offset = <0x100>; 232 ngpios = <32>; 233 gpio-controller; 234 #gpio-cells = <2>; 235 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; 236 marvell,pwm-offset = <0x1f0>; 237 #pwm-cells = <2>; 238 interrupt-controller; 239 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, 240 <85 IRQ_TYPE_LEVEL_HIGH>, 241 <84 IRQ_TYPE_LEVEL_HIGH>, 242 <83 IRQ_TYPE_LEVEL_HIGH>; 243 #interrupt-cells = <2>; 244 clock-names = "core", "axi"; 245 clocks = <&CP11X_LABEL(slow_io_clk)>, 246 <&CP11X_LABEL(x2core_clk)>; 247 status = "disabled"; 248 }; 249 250 CP11X_LABEL(gpio2): gpio@140 { 251 compatible = "marvell,armada-8k-gpio"; 252 offset = <0x140>; 253 ngpios = <31>; 254 gpio-controller; 255 #gpio-cells = <2>; 256 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; 257 marvell,pwm-offset = <0x1f0>; 258 #pwm-cells = <2>; 259 interrupt-controller; 260 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, 261 <81 IRQ_TYPE_LEVEL_HIGH>, 262 <80 IRQ_TYPE_LEVEL_HIGH>, 263 <79 IRQ_TYPE_LEVEL_HIGH>; 264 #interrupt-cells = <2>; 265 clock-names = "core", "axi"; 266 clocks = <&CP11X_LABEL(slow_io_clk)>, 267 <&CP11X_LABEL(x2core_clk)>; 268 status = "disabled"; 269 }; 270 }; 271 272 CP11X_LABEL(syscon1): system-controller@400000 { 273 compatible = "syscon", "simple-mfd"; 274 reg = <0x400000 0x1000>; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 278 CP11X_LABEL(thermal): thermal-sensor@70 { 279 compatible = "marvell,armada-cp110-thermal"; 280 reg = <0x70 0x10>; 281 interrupts-extended = 282 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; 283 #thermal-sensor-cells = <1>; 284 }; 285 }; 286 287 CP11X_LABEL(usb3_0): usb@500000 { 288 compatible = "marvell,armada-8k-xhci", 289 "generic-xhci"; 290 reg = <0x500000 0x4000>; 291 dma-coherent; 292 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; 293 clock-names = "core", "reg"; 294 clocks = <&CP11X_LABEL(core_clk)>, 295 <&CP11X_LABEL(core_clk)>; 296 status = "disabled"; 297 }; 298 299 CP11X_LABEL(usb3_1): usb@510000 { 300 compatible = "marvell,armada-8k-xhci", 301 "generic-xhci"; 302 reg = <0x510000 0x4000>; 303 dma-coherent; 304 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; 305 clock-names = "core", "reg"; 306 clocks = <&CP11X_LABEL(core_clk)>, 307 <&CP11X_LABEL(core_clk)>; 308 status = "disabled"; 309 }; 310 311 CP11X_LABEL(sata0): sata@540000 { 312 compatible = "marvell,armada-8k-ahci", 313 "generic-ahci"; 314 reg = <0x540000 0x30000>; 315 dma-coherent; 316 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&CP11X_LABEL(core_clk)>, 318 <&CP11X_LABEL(core_clk)>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 status = "disabled"; 322 323 sata-port@0 { 324 reg = <0>; 325 }; 326 327 sata-port@1 { 328 reg = <1>; 329 }; 330 }; 331 332 CP11X_LABEL(xor0): xor@6a0000 { 333 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 334 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 335 dma-coherent; 336 msi-parent = <&gic_v2m0>; 337 clock-names = "core", "reg"; 338 clocks = <&CP11X_LABEL(core_clk)>, 339 <&CP11X_LABEL(x2core_clk)>; 340 }; 341 342 CP11X_LABEL(xor1): xor@6c0000 { 343 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 344 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 345 dma-coherent; 346 msi-parent = <&gic_v2m0>; 347 clock-names = "core", "reg"; 348 clocks = <&CP11X_LABEL(core_clk)>, 349 <&CP11X_LABEL(x2core_clk)>; 350 }; 351 352 CP11X_LABEL(spi0): spi@700600 { 353 compatible = "marvell,armada-380-spi"; 354 reg = <0x700600 0x50>; 355 #address-cells = <0x1>; 356 #size-cells = <0x0>; 357 clock-names = "core", "axi"; 358 clocks = <&CP11X_LABEL(slow_io_clk)>, 359 <&CP11X_LABEL(x2core_clk)>; 360 status = "disabled"; 361 }; 362 363 CP11X_LABEL(spi1): spi@700680 { 364 compatible = "marvell,armada-380-spi"; 365 reg = <0x700680 0x50>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clock-names = "core", "axi"; 369 clocks = <&CP11X_LABEL(slow_io_clk)>, 370 <&CP11X_LABEL(x2core_clk)>; 371 status = "disabled"; 372 }; 373 374 CP11X_LABEL(i2c0): i2c@701000 { 375 compatible = "marvell,mv78230-i2c"; 376 reg = <0x701000 0x20>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; 380 clock-names = "core", "reg"; 381 clocks = <&CP11X_LABEL(slow_io_clk)>, 382 <&CP11X_LABEL(x2core_clk)>; 383 status = "disabled"; 384 }; 385 386 CP11X_LABEL(i2c1): i2c@701100 { 387 compatible = "marvell,mv78230-i2c"; 388 reg = <0x701100 0x20>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; 392 clock-names = "core", "reg"; 393 clocks = <&CP11X_LABEL(slow_io_clk)>, 394 <&CP11X_LABEL(x2core_clk)>; 395 status = "disabled"; 396 }; 397 398 CP11X_LABEL(uart0): serial@702000 { 399 compatible = "snps,dw-apb-uart"; 400 reg = <0x702000 0x100>; 401 reg-shift = <2>; 402 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; 403 reg-io-width = <1>; 404 clock-names = "baudclk", "apb_pclk"; 405 clocks = <&CP11X_LABEL(slow_io_clk)>, 406 <&CP11X_LABEL(x2core_clk)>; 407 status = "disabled"; 408 }; 409 410 CP11X_LABEL(uart1): serial@702100 { 411 compatible = "snps,dw-apb-uart"; 412 reg = <0x702100 0x100>; 413 reg-shift = <2>; 414 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; 415 reg-io-width = <1>; 416 clock-names = "baudclk", "apb_pclk"; 417 clocks = <&CP11X_LABEL(slow_io_clk)>, 418 <&CP11X_LABEL(x2core_clk)>; 419 status = "disabled"; 420 }; 421 422 CP11X_LABEL(uart2): serial@702200 { 423 compatible = "snps,dw-apb-uart"; 424 reg = <0x702200 0x100>; 425 reg-shift = <2>; 426 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; 427 reg-io-width = <1>; 428 clock-names = "baudclk", "apb_pclk"; 429 clocks = <&CP11X_LABEL(slow_io_clk)>, 430 <&CP11X_LABEL(x2core_clk)>; 431 status = "disabled"; 432 }; 433 434 CP11X_LABEL(uart3): serial@702300 { 435 compatible = "snps,dw-apb-uart"; 436 reg = <0x702300 0x100>; 437 reg-shift = <2>; 438 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; 439 reg-io-width = <1>; 440 clock-names = "baudclk", "apb_pclk"; 441 clocks = <&CP11X_LABEL(slow_io_clk)>, 442 <&CP11X_LABEL(x2core_clk)>; 443 status = "disabled"; 444 }; 445 446 CP11X_LABEL(nand_controller): nand@720000 { 447 /* 448 * Due to the limitation of the pins available 449 * this controller is only usable on the CPM 450 * for A7K and on the CPS for A8K. 451 */ 452 compatible = "marvell,armada-8k-nand-controller", 453 "marvell,armada370-nand-controller"; 454 reg = <0x720000 0x54>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; 458 clock-names = "core", "reg"; 459 clocks = <&CP11X_LABEL(nand_clk)>, 460 <&CP11X_LABEL(x2core_clk)>; 461 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 462 status = "disabled"; 463 }; 464 465 CP11X_LABEL(trng): trng@760000 { 466 compatible = "marvell,armada-8k-rng", 467 "inside-secure,safexcel-eip76"; 468 reg = <0x760000 0x7d>; 469 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; 470 clock-names = "core", "reg"; 471 clocks = <&CP11X_LABEL(x2core_clk)>, 472 <&CP11X_LABEL(x2core_clk)>; 473 status = "okay"; 474 }; 475 476 CP11X_LABEL(sdhci0): sdhci@780000 { 477 compatible = "marvell,armada-cp110-sdhci"; 478 reg = <0x780000 0x300>; 479 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 480 clock-names = "core", "axi"; 481 clocks = <&CP11X_LABEL(sdio_clk)>, <&CP11X_LABEL(core_clk)>; 482 dma-coherent; 483 status = "disabled"; 484 }; 485 486 CP11X_LABEL(crypto): crypto@800000 { 487 compatible = "inside-secure,safexcel-eip197b"; 488 reg = <0x800000 0x200000>; 489 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, 490 <88 IRQ_TYPE_LEVEL_HIGH>, 491 <89 IRQ_TYPE_LEVEL_HIGH>, 492 <90 IRQ_TYPE_LEVEL_HIGH>, 493 <91 IRQ_TYPE_LEVEL_HIGH>, 494 <92 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "mem", "ring0", "ring1", 496 "ring2", "ring3", "eip"; 497 clock-names = "core", "reg"; 498 clocks = <&CP11X_LABEL(x2core_clk)>, 499 <&CP11X_LABEL(x2core_clk)>; 500 dma-coherent; 501 }; 502 }; 503 504 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { 505 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 506 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, 507 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; 508 reg-names = "ctrl", "config"; 509 #address-cells = <3>; 510 #size-cells = <2>; 511 #interrupt-cells = <1>; 512 device_type = "pci"; 513 dma-coherent; 514 msi-parent = <&gic_v2m0>; 515 516 bus-range = <0 0xff>; 517 /* non-prefetchable memory */ 518 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; 519 interrupt-map-mask = <0 0 0 0>; 520 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; 521 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 522 num-lanes = <1>; 523 clock-names = "core", "reg"; 524 clocks = <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_clk)>; 525 status = "disabled"; 526 }; 527 528 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { 529 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 530 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, 531 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; 532 reg-names = "ctrl", "config"; 533 #address-cells = <3>; 534 #size-cells = <2>; 535 #interrupt-cells = <1>; 536 device_type = "pci"; 537 dma-coherent; 538 msi-parent = <&gic_v2m0>; 539 540 bus-range = <0 0xff>; 541 /* non-prefetchable memory */ 542 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; 543 interrupt-map-mask = <0 0 0 0>; 544 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; 545 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 546 547 num-lanes = <1>; 548 clock-names = "core", "reg"; 549 clocks = <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_clk)>; 550 status = "disabled"; 551 }; 552 553 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { 554 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 555 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, 556 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; 557 reg-names = "ctrl", "config"; 558 #address-cells = <3>; 559 #size-cells = <2>; 560 #interrupt-cells = <1>; 561 device_type = "pci"; 562 dma-coherent; 563 msi-parent = <&gic_v2m0>; 564 565 bus-range = <0 0xff>; 566 /* non-prefetchable memory */ 567 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; 568 interrupt-map-mask = <0 0 0 0>; 569 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; 570 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 571 572 num-lanes = <1>; 573 clock-names = "core", "reg"; 574 clocks = <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_clk)>; 575 status = "disabled"; 576 }; 577 578 /* 1 GHz fixed main PLL */ 579 CP11X_LABEL(mainpll): CP11X_LABEL(mainpll) { 580 compatible = "fixed-clock"; 581 #clock-cells = <0>; 582 clock-frequency = <1000000000>; 583 }; 584 585 CP11X_LABEL(x2core_clk): CP11X_LABEL(x2core_clk) { 586 compatible = "fixed-factor-clock"; 587 clocks = <&CP11X_LABEL(mainpll)>; 588 #clock-cells = <0>; 589 clock-mult = <1>; 590 clock-div = <2>; 591 }; 592 593 CP11X_LABEL(core_clk): CP11X_LABEL(core_clk) { 594 compatible = "fixed-factor-clock"; 595 clocks = <&CP11X_LABEL(mainpll)>; 596 #clock-cells = <0>; 597 clock-mult = <1>; 598 clock-div = <2>; 599 }; 600 601 CP11X_LABEL(sdio_clk): CP11X_LABEL(sdio_clk) { 602 compatible = "fixed-factor-clock"; 603 clocks = <&CP11X_LABEL(mainpll)>; 604 #clock-cells = <0>; 605 clock-mult = <2>; 606 clock-div = <5>; 607 }; 608 609 CP11X_LABEL(nand_clk): CP11X_LABEL(nand_clk) { 610 compatible = "fixed-factor-clock"; 611 clocks = <&CP11X_LABEL(mainpll)>; 612 #clock-cells = <0>; 613 clock-mult = <2>; 614 clock-div = <5>; 615 }; 616 617 CP11X_LABEL(ppv2_clk): CP11X_LABEL(ppv2_clk) { 618 compatible = "fixed-factor-clock"; 619 clocks = <&CP11X_LABEL(mainpll)>; 620 #clock-cells = <0>; 621 clock-mult = <1>; 622 clock-div = <3>; 623 }; 624 625 CP11X_LABEL(slow_io_clk): CP11X_LABEL(slow_io_clk) { 626 compatible = "fixed-factor-clock"; 627 clocks = <&CP11X_LABEL(mainpll)>; 628 #clock-cells = <0>; 629 clock-mult = <1>; 630 clock-div = <4>; 631 }; 632}; 633